./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix015_tso.opt_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix015_tso.opt_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3faba64a95a7a6525bff53cd761fa3b6c1f38d68 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 13:13:03,623 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 13:13:03,624 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 13:13:03,631 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 13:13:03,631 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 13:13:03,632 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 13:13:03,633 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 13:13:03,634 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 13:13:03,635 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 13:13:03,636 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 13:13:03,636 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 13:13:03,637 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 13:13:03,637 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 13:13:03,638 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 13:13:03,639 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 13:13:03,639 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 13:13:03,640 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 13:13:03,641 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 13:13:03,643 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 13:13:03,644 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 13:13:03,645 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 13:13:03,646 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 13:13:03,647 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 13:13:03,647 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 13:13:03,648 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 13:13:03,648 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 13:13:03,649 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 13:13:03,650 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 13:13:03,650 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 13:13:03,651 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 13:13:03,651 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 13:13:03,652 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 13:13:03,652 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 13:13:03,652 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 13:13:03,653 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 13:13:03,653 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 13:13:03,653 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-23 13:13:03,663 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 13:13:03,663 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 13:13:03,663 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 13:13:03,663 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 13:13:03,664 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 13:13:03,664 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 13:13:03,664 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 13:13:03,664 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 13:13:03,665 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 13:13:03,665 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 13:13:03,665 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 13:13:03,665 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 13:13:03,665 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 13:13:03,665 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 13:13:03,666 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 13:13:03,666 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 13:13:03,666 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 13:13:03,666 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 13:13:03,666 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 13:13:03,666 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 13:13:03,667 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 13:13:03,667 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 13:13:03,667 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 13:13:03,667 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 13:13:03,667 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 13:13:03,667 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 13:13:03,667 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 13:13:03,668 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 13:13:03,668 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 13:13:03,668 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 13:13:03,668 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3faba64a95a7a6525bff53cd761fa3b6c1f38d68 [2018-11-23 13:13:03,687 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 13:13:03,696 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 13:13:03,699 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 13:13:03,700 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 13:13:03,700 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 13:13:03,701 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix015_tso.opt_false-unreach-call.i [2018-11-23 13:13:03,742 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer/data/ac696abb2/1d2869a9823249529e27bb108fbf1038/FLAG3db71ef25 [2018-11-23 13:13:04,195 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 13:13:04,195 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/sv-benchmarks/c/pthread-wmm/mix015_tso.opt_false-unreach-call.i [2018-11-23 13:13:04,203 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer/data/ac696abb2/1d2869a9823249529e27bb108fbf1038/FLAG3db71ef25 [2018-11-23 13:13:04,213 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer/data/ac696abb2/1d2869a9823249529e27bb108fbf1038 [2018-11-23 13:13:04,215 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 13:13:04,216 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 13:13:04,216 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 13:13:04,216 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 13:13:04,219 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 13:13:04,220 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 01:13:04" (1/1) ... [2018-11-23 13:13:04,222 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7befe0c1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04, skipping insertion in model container [2018-11-23 13:13:04,222 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 01:13:04" (1/1) ... [2018-11-23 13:13:04,228 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 13:13:04,260 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 13:13:04,512 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 13:13:04,522 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 13:13:04,622 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 13:13:04,664 INFO L195 MainTranslator]: Completed translation [2018-11-23 13:13:04,664 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04 WrapperNode [2018-11-23 13:13:04,664 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 13:13:04,665 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 13:13:04,665 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 13:13:04,665 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 13:13:04,672 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04" (1/1) ... [2018-11-23 13:13:04,687 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04" (1/1) ... [2018-11-23 13:13:04,711 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 13:13:04,711 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 13:13:04,711 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 13:13:04,711 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 13:13:04,718 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04" (1/1) ... [2018-11-23 13:13:04,718 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04" (1/1) ... [2018-11-23 13:13:04,722 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04" (1/1) ... [2018-11-23 13:13:04,722 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04" (1/1) ... [2018-11-23 13:13:04,733 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04" (1/1) ... [2018-11-23 13:13:04,736 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04" (1/1) ... [2018-11-23 13:13:04,739 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04" (1/1) ... [2018-11-23 13:13:04,743 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 13:13:04,743 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 13:13:04,743 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 13:13:04,743 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 13:13:04,744 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 13:13:04,793 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 13:13:04,793 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 13:13:04,793 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2018-11-23 13:13:04,794 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 13:13:04,794 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2018-11-23 13:13:04,794 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2018-11-23 13:13:04,794 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2018-11-23 13:13:04,795 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2018-11-23 13:13:04,795 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2018-11-23 13:13:04,795 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2018-11-23 13:13:04,795 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2018-11-23 13:13:04,795 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 13:13:04,795 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 13:13:04,797 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-23 13:13:05,394 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 13:13:05,394 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-23 13:13:05,395 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 01:13:05 BoogieIcfgContainer [2018-11-23 13:13:05,395 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 13:13:05,395 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 13:13:05,395 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 13:13:05,397 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 13:13:05,397 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 01:13:04" (1/3) ... [2018-11-23 13:13:05,398 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1a6b006d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 01:13:05, skipping insertion in model container [2018-11-23 13:13:05,398 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:13:04" (2/3) ... [2018-11-23 13:13:05,398 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1a6b006d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 01:13:05, skipping insertion in model container [2018-11-23 13:13:05,398 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 01:13:05" (3/3) ... [2018-11-23 13:13:05,400 INFO L112 eAbstractionObserver]: Analyzing ICFG mix015_tso.opt_false-unreach-call.i [2018-11-23 13:13:05,436 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,436 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,436 WARN L317 ript$VariableManager]: TermVariabe Thread2_P0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,437 WARN L317 ript$VariableManager]: TermVariabe Thread2_P0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,437 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P0_#t~nondet3.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,437 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P0_#t~nondet3.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,437 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,438 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,438 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P0_#t~nondet3.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,438 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P0_#t~nondet3.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,438 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet5.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet4.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet4.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet5.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet4.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,439 WARN L317 ript$VariableManager]: TermVariabe Thread0_P1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,439 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet5.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,439 WARN L317 ript$VariableManager]: TermVariabe Thread0_P1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,440 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet4.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,440 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet5.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,440 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,440 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,440 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,441 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,444 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,444 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,445 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,445 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,445 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,445 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,445 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,446 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,447 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,447 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,447 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,447 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,447 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,447 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,448 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,448 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,448 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,448 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,448 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,449 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,449 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,449 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,449 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,449 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,449 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,450 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,450 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,450 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,450 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,450 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,451 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,451 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,451 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,451 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,451 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,451 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,451 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,452 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,452 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,452 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,452 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,452 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,453 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,453 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,453 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,453 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,453 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,453 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,453 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,454 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,454 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,454 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,454 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,454 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,454 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,454 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,455 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,455 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,455 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,455 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,455 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,455 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,455 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,456 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,456 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,456 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,456 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,456 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,457 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,457 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,457 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,457 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,457 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,457 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,457 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,457 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet27.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,458 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet27.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,458 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,458 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,458 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet27.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,458 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet27.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,459 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,459 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,459 WARN L317 ript$VariableManager]: TermVariabe Thread1_P2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,459 WARN L317 ript$VariableManager]: TermVariabe Thread1_P2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,459 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,459 WARN L317 ript$VariableManager]: TermVariabe Thread1_P2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,459 WARN L317 ript$VariableManager]: TermVariabe Thread1_P2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,460 WARN L317 ript$VariableManager]: TermVariabe Thread1_P2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,460 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~nondet29.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,460 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~nondet28.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,460 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~nondet28.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,460 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~nondet29.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,460 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~nondet28.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,460 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~nondet29.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,460 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~nondet29.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,461 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~nondet28.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,461 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,461 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,461 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,461 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,461 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,461 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,462 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,462 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,462 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,462 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,462 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,462 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,462 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,462 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,463 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,463 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,463 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,463 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,463 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,463 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,464 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,464 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,464 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,464 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,464 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,464 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,465 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,465 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,465 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,465 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,465 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,465 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,466 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,466 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,466 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,466 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,466 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,466 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,466 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,467 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,467 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,467 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,467 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,467 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,467 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,467 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,467 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,468 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,468 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,468 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,468 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,468 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,468 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,468 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,469 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,469 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,469 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,469 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,469 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,469 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,469 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,469 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,470 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,470 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,470 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,470 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,470 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,470 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,470 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,471 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,471 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,471 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,471 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,471 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,471 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,471 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,472 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,472 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,472 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,472 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,472 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,472 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,472 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,472 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,473 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,473 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,473 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,473 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,473 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,473 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,473 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,474 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,474 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,474 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,474 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,474 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,474 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,474 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,474 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,475 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,475 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,475 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,475 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,475 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,475 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,475 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,476 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,476 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,476 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~nondet57.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,476 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~nondet57.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,476 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,476 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,476 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~nondet57.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,476 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P2_#t~nondet57.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 13:13:05,485 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-23 13:13:05,485 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 13:13:05,491 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2018-11-23 13:13:05,502 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2018-11-23 13:13:05,520 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 13:13:05,520 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 13:13:05,520 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 13:13:05,520 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 13:13:05,521 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 13:13:05,521 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 13:13:05,521 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 13:13:05,521 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 13:13:05,521 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 13:13:05,531 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 190places, 242 transitions [2018-11-23 13:16:18,732 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 445147 states. [2018-11-23 13:16:18,733 INFO L276 IsEmpty]: Start isEmpty. Operand 445147 states. [2018-11-23 13:16:18,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-23 13:16:18,743 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:16:18,743 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:16:18,745 INFO L423 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:16:18,749 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:16:18,750 INFO L82 PathProgramCache]: Analyzing trace with hash -339585471, now seen corresponding path program 1 times [2018-11-23 13:16:18,751 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:16:18,752 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:16:18,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:16:18,797 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:16:18,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:16:18,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:16:18,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:16:18,950 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:16:18,950 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 13:16:18,954 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 13:16:18,967 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 13:16:18,967 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 13:16:18,970 INFO L87 Difference]: Start difference. First operand 445147 states. Second operand 4 states. [2018-11-23 13:16:29,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:16:29,875 INFO L93 Difference]: Finished difference Result 810627 states and 3886644 transitions. [2018-11-23 13:16:29,876 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 13:16:29,877 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 48 [2018-11-23 13:16:29,878 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:16:31,725 INFO L225 Difference]: With dead ends: 810627 [2018-11-23 13:16:31,725 INFO L226 Difference]: Without dead ends: 530977 [2018-11-23 13:16:31,727 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 13:16:41,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 530977 states. [2018-11-23 13:16:48,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 530977 to 307957. [2018-11-23 13:16:48,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 307957 states. [2018-11-23 13:16:59,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307957 states to 307957 states and 1493658 transitions. [2018-11-23 13:16:59,579 INFO L78 Accepts]: Start accepts. Automaton has 307957 states and 1493658 transitions. Word has length 48 [2018-11-23 13:16:59,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:16:59,581 INFO L480 AbstractCegarLoop]: Abstraction has 307957 states and 1493658 transitions. [2018-11-23 13:16:59,581 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 13:16:59,581 INFO L276 IsEmpty]: Start isEmpty. Operand 307957 states and 1493658 transitions. [2018-11-23 13:16:59,597 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-23 13:16:59,598 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:16:59,598 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:16:59,598 INFO L423 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:16:59,598 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:16:59,599 INFO L82 PathProgramCache]: Analyzing trace with hash -48370061, now seen corresponding path program 1 times [2018-11-23 13:16:59,599 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:16:59,599 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:16:59,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:16:59,603 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:16:59,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:16:59,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:16:59,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:16:59,676 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:16:59,676 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:16:59,677 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 13:16:59,678 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:16:59,678 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:16:59,678 INFO L87 Difference]: Start difference. First operand 307957 states and 1493658 transitions. Second operand 3 states. [2018-11-23 13:17:01,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:17:01,626 INFO L93 Difference]: Finished difference Result 307957 states and 1492633 transitions. [2018-11-23 13:17:01,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:17:01,626 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2018-11-23 13:17:01,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:17:04,026 INFO L225 Difference]: With dead ends: 307957 [2018-11-23 13:17:04,026 INFO L226 Difference]: Without dead ends: 307957 [2018-11-23 13:17:04,026 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:17:16,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307957 states. [2018-11-23 13:17:20,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307957 to 307957. [2018-11-23 13:17:20,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 307957 states. [2018-11-23 13:17:22,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307957 states to 307957 states and 1492633 transitions. [2018-11-23 13:17:22,776 INFO L78 Accepts]: Start accepts. Automaton has 307957 states and 1492633 transitions. Word has length 56 [2018-11-23 13:17:22,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:17:22,777 INFO L480 AbstractCegarLoop]: Abstraction has 307957 states and 1492633 transitions. [2018-11-23 13:17:22,777 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 13:17:22,777 INFO L276 IsEmpty]: Start isEmpty. Operand 307957 states and 1492633 transitions. [2018-11-23 13:17:22,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-23 13:17:22,785 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:17:22,786 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:17:22,786 INFO L423 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:17:22,786 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:17:22,786 INFO L82 PathProgramCache]: Analyzing trace with hash 1694440274, now seen corresponding path program 1 times [2018-11-23 13:17:22,786 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:17:22,786 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:17:22,789 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:17:22,789 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:17:22,790 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:17:22,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:17:22,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:17:22,869 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:17:22,869 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 13:17:22,869 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 13:17:22,869 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 13:17:22,870 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 13:17:22,870 INFO L87 Difference]: Start difference. First operand 307957 states and 1492633 transitions. Second operand 4 states. [2018-11-23 13:17:25,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:17:25,594 INFO L93 Difference]: Finished difference Result 272411 states and 1286588 transitions. [2018-11-23 13:17:25,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 13:17:25,594 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 56 [2018-11-23 13:17:25,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:17:26,418 INFO L225 Difference]: With dead ends: 272411 [2018-11-23 13:17:26,418 INFO L226 Difference]: Without dead ends: 258311 [2018-11-23 13:17:26,418 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 13:17:38,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 258311 states. [2018-11-23 13:17:41,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 258311 to 258311. [2018-11-23 13:17:41,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 258311 states. [2018-11-23 13:17:43,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 258311 states to 258311 states and 1232395 transitions. [2018-11-23 13:17:43,297 INFO L78 Accepts]: Start accepts. Automaton has 258311 states and 1232395 transitions. Word has length 56 [2018-11-23 13:17:43,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:17:43,297 INFO L480 AbstractCegarLoop]: Abstraction has 258311 states and 1232395 transitions. [2018-11-23 13:17:43,298 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 13:17:43,298 INFO L276 IsEmpty]: Start isEmpty. Operand 258311 states and 1232395 transitions. [2018-11-23 13:17:43,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-23 13:17:43,308 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:17:43,308 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:17:43,308 INFO L423 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:17:43,308 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:17:43,308 INFO L82 PathProgramCache]: Analyzing trace with hash -1611734580, now seen corresponding path program 1 times [2018-11-23 13:17:43,309 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:17:43,309 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:17:43,311 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:17:43,311 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:17:43,311 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:17:43,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:17:43,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:17:43,387 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:17:43,387 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 13:17:43,387 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 13:17:43,387 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 13:17:43,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 13:17:43,387 INFO L87 Difference]: Start difference. First operand 258311 states and 1232395 transitions. Second operand 5 states. [2018-11-23 13:17:43,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:17:43,709 INFO L93 Difference]: Finished difference Result 61671 states and 252911 transitions. [2018-11-23 13:17:43,710 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 13:17:43,710 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 57 [2018-11-23 13:17:43,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:17:43,828 INFO L225 Difference]: With dead ends: 61671 [2018-11-23 13:17:43,828 INFO L226 Difference]: Without dead ends: 49979 [2018-11-23 13:17:43,829 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 13:17:44,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49979 states. [2018-11-23 13:17:44,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49979 to 49519. [2018-11-23 13:17:44,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49519 states. [2018-11-23 13:17:45,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49519 states to 49519 states and 199433 transitions. [2018-11-23 13:17:45,541 INFO L78 Accepts]: Start accepts. Automaton has 49519 states and 199433 transitions. Word has length 57 [2018-11-23 13:17:45,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:17:45,542 INFO L480 AbstractCegarLoop]: Abstraction has 49519 states and 199433 transitions. [2018-11-23 13:17:45,542 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 13:17:45,542 INFO L276 IsEmpty]: Start isEmpty. Operand 49519 states and 199433 transitions. [2018-11-23 13:17:45,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-23 13:17:45,545 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:17:45,545 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:17:45,545 INFO L423 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:17:45,545 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:17:45,546 INFO L82 PathProgramCache]: Analyzing trace with hash 828222952, now seen corresponding path program 1 times [2018-11-23 13:17:45,546 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:17:45,546 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:17:45,548 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:17:45,548 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:17:45,548 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:17:45,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:17:45,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:17:45,623 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:17:45,623 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 13:17:45,624 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 13:17:45,624 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 13:17:45,624 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 13:17:45,624 INFO L87 Difference]: Start difference. First operand 49519 states and 199433 transitions. Second operand 5 states. [2018-11-23 13:17:46,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:17:46,326 INFO L93 Difference]: Finished difference Result 100165 states and 398362 transitions. [2018-11-23 13:17:46,327 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 13:17:46,327 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 57 [2018-11-23 13:17:46,327 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:17:46,555 INFO L225 Difference]: With dead ends: 100165 [2018-11-23 13:17:46,556 INFO L226 Difference]: Without dead ends: 99790 [2018-11-23 13:17:46,556 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 13:17:46,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99790 states. [2018-11-23 13:17:48,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99790 to 66558. [2018-11-23 13:17:48,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66558 states. [2018-11-23 13:17:48,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66558 states to 66558 states and 261441 transitions. [2018-11-23 13:17:48,487 INFO L78 Accepts]: Start accepts. Automaton has 66558 states and 261441 transitions. Word has length 57 [2018-11-23 13:17:48,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:17:48,487 INFO L480 AbstractCegarLoop]: Abstraction has 66558 states and 261441 transitions. [2018-11-23 13:17:48,487 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 13:17:48,487 INFO L276 IsEmpty]: Start isEmpty. Operand 66558 states and 261441 transitions. [2018-11-23 13:17:48,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-11-23 13:17:48,491 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:17:48,491 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:17:48,491 INFO L423 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:17:48,491 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:17:48,491 INFO L82 PathProgramCache]: Analyzing trace with hash -2059079538, now seen corresponding path program 1 times [2018-11-23 13:17:48,491 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:17:48,492 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:17:48,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:17:48,493 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:17:48,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:17:48,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:17:48,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:17:48,540 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:17:48,540 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:17:48,540 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 13:17:48,540 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:17:48,540 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:17:48,541 INFO L87 Difference]: Start difference. First operand 66558 states and 261441 transitions. Second operand 3 states. [2018-11-23 13:17:49,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:17:49,101 INFO L93 Difference]: Finished difference Result 122934 states and 477436 transitions. [2018-11-23 13:17:49,101 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:17:49,101 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2018-11-23 13:17:49,102 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:17:49,387 INFO L225 Difference]: With dead ends: 122934 [2018-11-23 13:17:49,387 INFO L226 Difference]: Without dead ends: 122914 [2018-11-23 13:17:49,387 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:17:49,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122914 states. [2018-11-23 13:17:51,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122914 to 103769. [2018-11-23 13:17:51,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103769 states. [2018-11-23 13:17:51,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103769 states to 103769 states and 403303 transitions. [2018-11-23 13:17:51,612 INFO L78 Accepts]: Start accepts. Automaton has 103769 states and 403303 transitions. Word has length 59 [2018-11-23 13:17:51,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:17:51,613 INFO L480 AbstractCegarLoop]: Abstraction has 103769 states and 403303 transitions. [2018-11-23 13:17:51,613 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 13:17:51,613 INFO L276 IsEmpty]: Start isEmpty. Operand 103769 states and 403303 transitions. [2018-11-23 13:17:51,621 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-23 13:17:51,621 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:17:51,621 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:17:51,622 INFO L423 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:17:51,622 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:17:51,622 INFO L82 PathProgramCache]: Analyzing trace with hash 422957529, now seen corresponding path program 1 times [2018-11-23 13:17:51,622 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:17:51,622 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:17:51,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:17:51,624 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:17:51,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:17:51,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:17:51,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:17:51,723 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:17:51,723 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 13:17:51,723 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 13:17:51,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 13:17:51,724 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-11-23 13:17:51,724 INFO L87 Difference]: Start difference. First operand 103769 states and 403303 transitions. Second operand 8 states. [2018-11-23 13:17:52,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:17:52,962 INFO L93 Difference]: Finished difference Result 140479 states and 532646 transitions. [2018-11-23 13:17:52,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 13:17:52,963 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 63 [2018-11-23 13:17:52,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:17:53,284 INFO L225 Difference]: With dead ends: 140479 [2018-11-23 13:17:53,284 INFO L226 Difference]: Without dead ends: 140014 [2018-11-23 13:17:53,285 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=69, Invalid=203, Unknown=0, NotChecked=0, Total=272 [2018-11-23 13:17:54,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140014 states. [2018-11-23 13:17:55,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140014 to 105818. [2018-11-23 13:17:55,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105818 states. [2018-11-23 13:17:55,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105818 states to 105818 states and 410088 transitions. [2018-11-23 13:17:55,665 INFO L78 Accepts]: Start accepts. Automaton has 105818 states and 410088 transitions. Word has length 63 [2018-11-23 13:17:55,665 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:17:55,665 INFO L480 AbstractCegarLoop]: Abstraction has 105818 states and 410088 transitions. [2018-11-23 13:17:55,665 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 13:17:55,665 INFO L276 IsEmpty]: Start isEmpty. Operand 105818 states and 410088 transitions. [2018-11-23 13:17:55,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-11-23 13:17:55,696 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:17:55,696 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:17:55,696 INFO L423 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:17:55,696 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:17:55,696 INFO L82 PathProgramCache]: Analyzing trace with hash 1246120427, now seen corresponding path program 1 times [2018-11-23 13:17:55,696 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:17:55,696 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:17:55,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:17:55,698 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:17:55,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:17:55,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:17:55,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:17:55,777 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:17:55,777 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 13:17:55,777 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 13:17:55,777 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 13:17:55,777 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 13:17:55,777 INFO L87 Difference]: Start difference. First operand 105818 states and 410088 transitions. Second operand 6 states. [2018-11-23 13:17:57,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:17:57,606 INFO L93 Difference]: Finished difference Result 249350 states and 954618 transitions. [2018-11-23 13:17:57,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 13:17:57,607 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2018-11-23 13:17:57,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:17:58,234 INFO L225 Difference]: With dead ends: 249350 [2018-11-23 13:17:58,234 INFO L226 Difference]: Without dead ends: 249030 [2018-11-23 13:17:58,235 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2018-11-23 13:17:58,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249030 states. [2018-11-23 13:18:02,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249030 to 156108. [2018-11-23 13:18:02,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156108 states. [2018-11-23 13:18:02,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156108 states to 156108 states and 592792 transitions. [2018-11-23 13:18:02,717 INFO L78 Accepts]: Start accepts. Automaton has 156108 states and 592792 transitions. Word has length 74 [2018-11-23 13:18:02,717 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:02,717 INFO L480 AbstractCegarLoop]: Abstraction has 156108 states and 592792 transitions. [2018-11-23 13:18:02,718 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 13:18:02,718 INFO L276 IsEmpty]: Start isEmpty. Operand 156108 states and 592792 transitions. [2018-11-23 13:18:02,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-23 13:18:02,789 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:02,789 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:02,790 INFO L423 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:02,790 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:02,790 INFO L82 PathProgramCache]: Analyzing trace with hash 1848798614, now seen corresponding path program 1 times [2018-11-23 13:18:02,790 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:02,790 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:02,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:02,792 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:02,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:02,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:02,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:02,887 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:02,887 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 13:18:02,887 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 13:18:02,888 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 13:18:02,888 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-11-23 13:18:02,888 INFO L87 Difference]: Start difference. First operand 156108 states and 592792 transitions. Second operand 7 states. [2018-11-23 13:18:04,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:04,868 INFO L93 Difference]: Finished difference Result 242605 states and 920052 transitions. [2018-11-23 13:18:04,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 13:18:04,868 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 81 [2018-11-23 13:18:04,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:06,102 INFO L225 Difference]: With dead ends: 242605 [2018-11-23 13:18:06,102 INFO L226 Difference]: Without dead ends: 241357 [2018-11-23 13:18:06,102 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=81, Unknown=0, NotChecked=0, Total=110 [2018-11-23 13:18:06,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 241357 states. [2018-11-23 13:18:13,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 241357 to 221191. [2018-11-23 13:18:13,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221191 states. [2018-11-23 13:18:15,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221191 states to 221191 states and 838930 transitions. [2018-11-23 13:18:15,076 INFO L78 Accepts]: Start accepts. Automaton has 221191 states and 838930 transitions. Word has length 81 [2018-11-23 13:18:15,076 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:15,076 INFO L480 AbstractCegarLoop]: Abstraction has 221191 states and 838930 transitions. [2018-11-23 13:18:15,076 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 13:18:15,076 INFO L276 IsEmpty]: Start isEmpty. Operand 221191 states and 838930 transitions. [2018-11-23 13:18:15,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-23 13:18:15,196 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:15,196 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:15,197 INFO L423 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:15,197 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:15,197 INFO L82 PathProgramCache]: Analyzing trace with hash 51847255, now seen corresponding path program 1 times [2018-11-23 13:18:15,197 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:15,197 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:15,199 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:15,199 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:15,199 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:15,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:15,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:15,307 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:15,307 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 13:18:15,307 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 13:18:15,307 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 13:18:15,307 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-23 13:18:15,308 INFO L87 Difference]: Start difference. First operand 221191 states and 838930 transitions. Second operand 8 states. [2018-11-23 13:18:17,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:17,319 INFO L93 Difference]: Finished difference Result 264605 states and 995964 transitions. [2018-11-23 13:18:17,319 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 13:18:17,319 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 81 [2018-11-23 13:18:17,319 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:18,828 INFO L225 Difference]: With dead ends: 264605 [2018-11-23 13:18:18,829 INFO L226 Difference]: Without dead ends: 264605 [2018-11-23 13:18:18,829 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2018-11-23 13:18:19,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 264605 states. [2018-11-23 13:18:22,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 264605 to 234279. [2018-11-23 13:18:22,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234279 states. [2018-11-23 13:18:23,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234279 states to 234279 states and 886386 transitions. [2018-11-23 13:18:23,952 INFO L78 Accepts]: Start accepts. Automaton has 234279 states and 886386 transitions. Word has length 81 [2018-11-23 13:18:23,953 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:23,953 INFO L480 AbstractCegarLoop]: Abstraction has 234279 states and 886386 transitions. [2018-11-23 13:18:23,953 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 13:18:23,953 INFO L276 IsEmpty]: Start isEmpty. Operand 234279 states and 886386 transitions. [2018-11-23 13:18:24,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-23 13:18:24,061 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:24,062 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:24,062 INFO L423 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:24,062 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:24,062 INFO L82 PathProgramCache]: Analyzing trace with hash 939350936, now seen corresponding path program 1 times [2018-11-23 13:18:24,062 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:24,062 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:24,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:24,064 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:24,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:24,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:24,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:24,124 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:24,124 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 13:18:24,124 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 13:18:24,124 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 13:18:24,124 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 13:18:24,125 INFO L87 Difference]: Start difference. First operand 234279 states and 886386 transitions. Second operand 6 states. [2018-11-23 13:18:24,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:24,497 INFO L93 Difference]: Finished difference Result 73415 states and 243746 transitions. [2018-11-23 13:18:24,497 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 13:18:24,497 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 81 [2018-11-23 13:18:24,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:24,606 INFO L225 Difference]: With dead ends: 73415 [2018-11-23 13:18:24,606 INFO L226 Difference]: Without dead ends: 62727 [2018-11-23 13:18:24,606 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2018-11-23 13:18:24,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62727 states. [2018-11-23 13:18:25,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62727 to 42262. [2018-11-23 13:18:25,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42262 states. [2018-11-23 13:18:25,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42262 states to 42262 states and 141951 transitions. [2018-11-23 13:18:25,354 INFO L78 Accepts]: Start accepts. Automaton has 42262 states and 141951 transitions. Word has length 81 [2018-11-23 13:18:25,354 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:25,354 INFO L480 AbstractCegarLoop]: Abstraction has 42262 states and 141951 transitions. [2018-11-23 13:18:25,355 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 13:18:25,355 INFO L276 IsEmpty]: Start isEmpty. Operand 42262 states and 141951 transitions. [2018-11-23 13:18:25,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-23 13:18:25,403 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:25,403 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:25,403 INFO L423 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:25,403 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:25,404 INFO L82 PathProgramCache]: Analyzing trace with hash 2009048315, now seen corresponding path program 1 times [2018-11-23 13:18:25,404 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:25,404 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:25,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:25,406 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:25,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:25,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:25,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:25,472 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:25,472 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 13:18:25,472 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 13:18:25,474 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 13:18:25,474 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 13:18:25,474 INFO L87 Difference]: Start difference. First operand 42262 states and 141951 transitions. Second operand 4 states. [2018-11-23 13:18:26,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:26,630 INFO L93 Difference]: Finished difference Result 82705 states and 268032 transitions. [2018-11-23 13:18:26,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 13:18:26,630 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 109 [2018-11-23 13:18:26,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:26,755 INFO L225 Difference]: With dead ends: 82705 [2018-11-23 13:18:26,756 INFO L226 Difference]: Without dead ends: 82705 [2018-11-23 13:18:26,756 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 13:18:26,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82705 states. [2018-11-23 13:18:27,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82705 to 62851. [2018-11-23 13:18:27,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62851 states. [2018-11-23 13:18:27,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62851 states to 62851 states and 207437 transitions. [2018-11-23 13:18:27,774 INFO L78 Accepts]: Start accepts. Automaton has 62851 states and 207437 transitions. Word has length 109 [2018-11-23 13:18:27,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:27,774 INFO L480 AbstractCegarLoop]: Abstraction has 62851 states and 207437 transitions. [2018-11-23 13:18:27,774 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 13:18:27,774 INFO L276 IsEmpty]: Start isEmpty. Operand 62851 states and 207437 transitions. [2018-11-23 13:18:27,854 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-23 13:18:27,854 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:27,854 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:27,854 INFO L423 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:27,854 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:27,854 INFO L82 PathProgramCache]: Analyzing trace with hash 764283834, now seen corresponding path program 1 times [2018-11-23 13:18:27,854 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:27,855 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:27,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:27,856 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:27,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:27,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:27,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:27,921 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:27,921 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 13:18:27,921 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 13:18:27,921 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 13:18:27,921 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 13:18:27,922 INFO L87 Difference]: Start difference. First operand 62851 states and 207437 transitions. Second operand 4 states. [2018-11-23 13:18:28,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:28,314 INFO L93 Difference]: Finished difference Result 70247 states and 229701 transitions. [2018-11-23 13:18:28,314 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 13:18:28,314 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 109 [2018-11-23 13:18:28,315 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:28,425 INFO L225 Difference]: With dead ends: 70247 [2018-11-23 13:18:28,425 INFO L226 Difference]: Without dead ends: 70247 [2018-11-23 13:18:28,425 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 13:18:28,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70247 states. [2018-11-23 13:18:29,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70247 to 63521. [2018-11-23 13:18:29,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63521 states. [2018-11-23 13:18:29,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63521 states to 63521 states and 209723 transitions. [2018-11-23 13:18:29,685 INFO L78 Accepts]: Start accepts. Automaton has 63521 states and 209723 transitions. Word has length 109 [2018-11-23 13:18:29,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:29,685 INFO L480 AbstractCegarLoop]: Abstraction has 63521 states and 209723 transitions. [2018-11-23 13:18:29,686 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 13:18:29,686 INFO L276 IsEmpty]: Start isEmpty. Operand 63521 states and 209723 transitions. [2018-11-23 13:18:29,766 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-23 13:18:29,766 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:29,766 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:29,767 INFO L423 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:29,767 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:29,767 INFO L82 PathProgramCache]: Analyzing trace with hash -1312925509, now seen corresponding path program 1 times [2018-11-23 13:18:29,767 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:29,767 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:29,769 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:29,769 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:29,769 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:29,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:29,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:29,822 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:29,822 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:18:29,823 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 13:18:29,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:18:29,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:18:29,823 INFO L87 Difference]: Start difference. First operand 63521 states and 209723 transitions. Second operand 3 states. [2018-11-23 13:18:30,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:30,248 INFO L93 Difference]: Finished difference Result 69221 states and 225203 transitions. [2018-11-23 13:18:30,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:18:30,248 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 109 [2018-11-23 13:18:30,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:30,359 INFO L225 Difference]: With dead ends: 69221 [2018-11-23 13:18:30,359 INFO L226 Difference]: Without dead ends: 69221 [2018-11-23 13:18:30,359 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:18:30,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69221 states. [2018-11-23 13:18:31,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69221 to 64461. [2018-11-23 13:18:31,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64461 states. [2018-11-23 13:18:31,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64461 states to 64461 states and 210815 transitions. [2018-11-23 13:18:31,326 INFO L78 Accepts]: Start accepts. Automaton has 64461 states and 210815 transitions. Word has length 109 [2018-11-23 13:18:31,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:31,327 INFO L480 AbstractCegarLoop]: Abstraction has 64461 states and 210815 transitions. [2018-11-23 13:18:31,327 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 13:18:31,327 INFO L276 IsEmpty]: Start isEmpty. Operand 64461 states and 210815 transitions. [2018-11-23 13:18:31,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-23 13:18:31,409 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:31,410 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:31,410 INFO L423 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:31,410 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:31,410 INFO L82 PathProgramCache]: Analyzing trace with hash 637988787, now seen corresponding path program 2 times [2018-11-23 13:18:31,410 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:31,410 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:31,671 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:31,671 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:31,671 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:31,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:31,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:31,769 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:31,769 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 13:18:31,769 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 13:18:31,769 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 13:18:31,769 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-23 13:18:31,770 INFO L87 Difference]: Start difference. First operand 64461 states and 210815 transitions. Second operand 6 states. [2018-11-23 13:18:32,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:32,234 INFO L93 Difference]: Finished difference Result 75321 states and 245209 transitions. [2018-11-23 13:18:32,235 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 13:18:32,235 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 109 [2018-11-23 13:18:32,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:32,353 INFO L225 Difference]: With dead ends: 75321 [2018-11-23 13:18:32,353 INFO L226 Difference]: Without dead ends: 75193 [2018-11-23 13:18:32,353 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 13:18:32,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75193 states. [2018-11-23 13:18:33,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75193 to 68750. [2018-11-23 13:18:33,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68750 states. [2018-11-23 13:18:33,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68750 states to 68750 states and 224451 transitions. [2018-11-23 13:18:33,402 INFO L78 Accepts]: Start accepts. Automaton has 68750 states and 224451 transitions. Word has length 109 [2018-11-23 13:18:33,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:33,403 INFO L480 AbstractCegarLoop]: Abstraction has 68750 states and 224451 transitions. [2018-11-23 13:18:33,403 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 13:18:33,403 INFO L276 IsEmpty]: Start isEmpty. Operand 68750 states and 224451 transitions. [2018-11-23 13:18:33,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-23 13:18:33,489 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:33,489 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:33,489 INFO L423 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:33,489 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:33,489 INFO L82 PathProgramCache]: Analyzing trace with hash -1158962572, now seen corresponding path program 1 times [2018-11-23 13:18:33,490 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:33,490 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:33,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:33,491 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:18:33,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:33,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:33,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:33,586 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:33,586 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 13:18:33,587 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 13:18:33,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 13:18:33,587 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-11-23 13:18:33,587 INFO L87 Difference]: Start difference. First operand 68750 states and 224451 transitions. Second operand 7 states. [2018-11-23 13:18:34,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:34,332 INFO L93 Difference]: Finished difference Result 96766 states and 315157 transitions. [2018-11-23 13:18:34,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 13:18:34,333 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 109 [2018-11-23 13:18:34,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:34,492 INFO L225 Difference]: With dead ends: 96766 [2018-11-23 13:18:34,492 INFO L226 Difference]: Without dead ends: 96766 [2018-11-23 13:18:34,493 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=91, Unknown=0, NotChecked=0, Total=132 [2018-11-23 13:18:35,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96766 states. [2018-11-23 13:18:35,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96766 to 71185. [2018-11-23 13:18:35,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71185 states. [2018-11-23 13:18:36,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71185 states to 71185 states and 232917 transitions. [2018-11-23 13:18:36,006 INFO L78 Accepts]: Start accepts. Automaton has 71185 states and 232917 transitions. Word has length 109 [2018-11-23 13:18:36,007 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:36,007 INFO L480 AbstractCegarLoop]: Abstraction has 71185 states and 232917 transitions. [2018-11-23 13:18:36,007 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 13:18:36,007 INFO L276 IsEmpty]: Start isEmpty. Operand 71185 states and 232917 transitions. [2018-11-23 13:18:36,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-11-23 13:18:36,099 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:36,100 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:36,100 INFO L423 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:36,100 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:36,100 INFO L82 PathProgramCache]: Analyzing trace with hash -271458891, now seen corresponding path program 1 times [2018-11-23 13:18:36,100 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:36,100 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:36,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:36,101 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:36,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:36,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:36,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:36,210 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:36,210 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 13:18:36,210 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 13:18:36,210 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 13:18:36,210 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-23 13:18:36,210 INFO L87 Difference]: Start difference. First operand 71185 states and 232917 transitions. Second operand 6 states. [2018-11-23 13:18:36,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:36,935 INFO L93 Difference]: Finished difference Result 92552 states and 302905 transitions. [2018-11-23 13:18:36,936 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 13:18:36,936 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 109 [2018-11-23 13:18:36,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:37,088 INFO L225 Difference]: With dead ends: 92552 [2018-11-23 13:18:37,088 INFO L226 Difference]: Without dead ends: 92552 [2018-11-23 13:18:37,088 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-11-23 13:18:37,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92552 states. [2018-11-23 13:18:38,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92552 to 71275. [2018-11-23 13:18:38,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71275 states. [2018-11-23 13:18:38,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71275 states to 71275 states and 232859 transitions. [2018-11-23 13:18:38,457 INFO L78 Accepts]: Start accepts. Automaton has 71275 states and 232859 transitions. Word has length 109 [2018-11-23 13:18:38,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:38,457 INFO L480 AbstractCegarLoop]: Abstraction has 71275 states and 232859 transitions. [2018-11-23 13:18:38,457 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 13:18:38,457 INFO L276 IsEmpty]: Start isEmpty. Operand 71275 states and 232859 transitions. [2018-11-23 13:18:38,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-23 13:18:38,549 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:38,549 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:38,550 INFO L423 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:38,550 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:38,550 INFO L82 PathProgramCache]: Analyzing trace with hash -8687217, now seen corresponding path program 1 times [2018-11-23 13:18:38,550 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:38,550 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:38,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:38,551 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:38,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:38,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:38,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:38,643 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:38,643 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 13:18:38,644 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 13:18:38,644 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 13:18:38,644 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 13:18:38,644 INFO L87 Difference]: Start difference. First operand 71275 states and 232859 transitions. Second operand 7 states. [2018-11-23 13:18:39,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:39,379 INFO L93 Difference]: Finished difference Result 96605 states and 312333 transitions. [2018-11-23 13:18:39,379 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 13:18:39,379 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 111 [2018-11-23 13:18:39,380 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:39,535 INFO L225 Difference]: With dead ends: 96605 [2018-11-23 13:18:39,535 INFO L226 Difference]: Without dead ends: 96605 [2018-11-23 13:18:39,536 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2018-11-23 13:18:39,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96605 states. [2018-11-23 13:18:41,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96605 to 82155. [2018-11-23 13:18:41,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82155 states. [2018-11-23 13:18:41,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82155 states to 82155 states and 267998 transitions. [2018-11-23 13:18:41,198 INFO L78 Accepts]: Start accepts. Automaton has 82155 states and 267998 transitions. Word has length 111 [2018-11-23 13:18:41,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:41,199 INFO L480 AbstractCegarLoop]: Abstraction has 82155 states and 267998 transitions. [2018-11-23 13:18:41,199 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 13:18:41,199 INFO L276 IsEmpty]: Start isEmpty. Operand 82155 states and 267998 transitions. [2018-11-23 13:18:41,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-23 13:18:41,304 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:41,304 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:41,304 INFO L423 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:41,304 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:41,304 INFO L82 PathProgramCache]: Analyzing trace with hash -263423762, now seen corresponding path program 1 times [2018-11-23 13:18:41,304 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:41,304 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:41,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:41,305 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:41,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:41,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:41,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:41,437 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:41,438 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 13:18:41,439 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 13:18:41,439 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 13:18:41,439 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 13:18:41,439 INFO L87 Difference]: Start difference. First operand 82155 states and 267998 transitions. Second operand 6 states. [2018-11-23 13:18:41,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:41,915 INFO L93 Difference]: Finished difference Result 81067 states and 263374 transitions. [2018-11-23 13:18:41,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 13:18:41,915 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 111 [2018-11-23 13:18:41,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:42,047 INFO L225 Difference]: With dead ends: 81067 [2018-11-23 13:18:42,047 INFO L226 Difference]: Without dead ends: 81067 [2018-11-23 13:18:42,047 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-23 13:18:42,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81067 states. [2018-11-23 13:18:43,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81067 to 65493. [2018-11-23 13:18:43,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65493 states. [2018-11-23 13:18:43,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65493 states to 65493 states and 214190 transitions. [2018-11-23 13:18:43,182 INFO L78 Accepts]: Start accepts. Automaton has 65493 states and 214190 transitions. Word has length 111 [2018-11-23 13:18:43,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:43,182 INFO L480 AbstractCegarLoop]: Abstraction has 65493 states and 214190 transitions. [2018-11-23 13:18:43,182 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 13:18:43,183 INFO L276 IsEmpty]: Start isEmpty. Operand 65493 states and 214190 transitions. [2018-11-23 13:18:43,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-11-23 13:18:43,266 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:43,267 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:43,267 INFO L423 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:43,267 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:43,267 INFO L82 PathProgramCache]: Analyzing trace with hash -1037537284, now seen corresponding path program 1 times [2018-11-23 13:18:43,267 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:43,267 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:43,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:43,269 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:43,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:43,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:43,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:43,326 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:43,326 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 13:18:43,327 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 13:18:43,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 13:18:43,327 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 13:18:43,327 INFO L87 Difference]: Start difference. First operand 65493 states and 214190 transitions. Second operand 5 states. [2018-11-23 13:18:43,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:43,847 INFO L93 Difference]: Finished difference Result 80201 states and 258333 transitions. [2018-11-23 13:18:43,847 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 13:18:43,847 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2018-11-23 13:18:43,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:43,985 INFO L225 Difference]: With dead ends: 80201 [2018-11-23 13:18:43,985 INFO L226 Difference]: Without dead ends: 80201 [2018-11-23 13:18:43,986 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 13:18:44,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80201 states. [2018-11-23 13:18:45,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80201 to 68613. [2018-11-23 13:18:45,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68613 states. [2018-11-23 13:18:45,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68613 states to 68613 states and 223571 transitions. [2018-11-23 13:18:45,237 INFO L78 Accepts]: Start accepts. Automaton has 68613 states and 223571 transitions. Word has length 111 [2018-11-23 13:18:45,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:45,237 INFO L480 AbstractCegarLoop]: Abstraction has 68613 states and 223571 transitions. [2018-11-23 13:18:45,237 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 13:18:45,237 INFO L276 IsEmpty]: Start isEmpty. Operand 68613 states and 223571 transitions. [2018-11-23 13:18:45,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 13:18:45,326 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:45,326 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:45,326 INFO L423 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:45,327 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:45,327 INFO L82 PathProgramCache]: Analyzing trace with hash 1967475405, now seen corresponding path program 1 times [2018-11-23 13:18:45,327 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:45,327 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:45,328 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:45,328 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:45,328 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:45,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:45,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:45,443 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:45,444 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 13:18:45,444 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 13:18:45,444 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 13:18:45,444 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-23 13:18:45,444 INFO L87 Difference]: Start difference. First operand 68613 states and 223571 transitions. Second operand 7 states. [2018-11-23 13:18:45,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:45,868 INFO L93 Difference]: Finished difference Result 72385 states and 234886 transitions. [2018-11-23 13:18:45,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 13:18:45,868 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 113 [2018-11-23 13:18:45,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:45,985 INFO L225 Difference]: With dead ends: 72385 [2018-11-23 13:18:45,985 INFO L226 Difference]: Without dead ends: 72385 [2018-11-23 13:18:45,986 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=72, Unknown=0, NotChecked=0, Total=110 [2018-11-23 13:18:46,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72385 states. [2018-11-23 13:18:46,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72385 to 71576. [2018-11-23 13:18:46,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71576 states. [2018-11-23 13:18:47,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71576 states to 71576 states and 232637 transitions. [2018-11-23 13:18:47,032 INFO L78 Accepts]: Start accepts. Automaton has 71576 states and 232637 transitions. Word has length 113 [2018-11-23 13:18:47,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:47,032 INFO L480 AbstractCegarLoop]: Abstraction has 71576 states and 232637 transitions. [2018-11-23 13:18:47,032 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 13:18:47,032 INFO L276 IsEmpty]: Start isEmpty. Operand 71576 states and 232637 transitions. [2018-11-23 13:18:47,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 13:18:47,430 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:47,430 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:47,430 INFO L423 AbstractCegarLoop]: === Iteration 22 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:47,430 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:47,430 INFO L82 PathProgramCache]: Analyzing trace with hash -1439988210, now seen corresponding path program 1 times [2018-11-23 13:18:47,430 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:47,430 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:47,431 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:47,431 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:47,431 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:47,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:47,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:47,572 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:47,572 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-11-23 13:18:47,572 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 13:18:47,572 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 13:18:47,572 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2018-11-23 13:18:47,572 INFO L87 Difference]: Start difference. First operand 71576 states and 232637 transitions. Second operand 12 states. [2018-11-23 13:18:48,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:48,810 INFO L93 Difference]: Finished difference Result 140552 states and 452744 transitions. [2018-11-23 13:18:48,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-23 13:18:48,811 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 113 [2018-11-23 13:18:48,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:49,042 INFO L225 Difference]: With dead ends: 140552 [2018-11-23 13:18:49,042 INFO L226 Difference]: Without dead ends: 129220 [2018-11-23 13:18:49,042 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 138 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=144, Invalid=612, Unknown=0, NotChecked=0, Total=756 [2018-11-23 13:18:49,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129220 states. [2018-11-23 13:18:50,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129220 to 94011. [2018-11-23 13:18:50,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94011 states. [2018-11-23 13:18:50,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94011 states to 94011 states and 307100 transitions. [2018-11-23 13:18:50,845 INFO L78 Accepts]: Start accepts. Automaton has 94011 states and 307100 transitions. Word has length 113 [2018-11-23 13:18:50,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:50,845 INFO L480 AbstractCegarLoop]: Abstraction has 94011 states and 307100 transitions. [2018-11-23 13:18:50,845 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 13:18:50,845 INFO L276 IsEmpty]: Start isEmpty. Operand 94011 states and 307100 transitions. [2018-11-23 13:18:51,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 13:18:51,283 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:51,283 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:51,283 INFO L423 AbstractCegarLoop]: === Iteration 23 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:51,283 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:51,283 INFO L82 PathProgramCache]: Analyzing trace with hash 1682974836, now seen corresponding path program 2 times [2018-11-23 13:18:51,283 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:51,283 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:51,284 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:51,284 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:18:51,284 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:51,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:51,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:51,319 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:51,319 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:18:51,320 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 13:18:51,320 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:18:51,320 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:18:51,320 INFO L87 Difference]: Start difference. First operand 94011 states and 307100 transitions. Second operand 3 states. [2018-11-23 13:18:51,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:51,682 INFO L93 Difference]: Finished difference Result 98266 states and 319559 transitions. [2018-11-23 13:18:51,683 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:18:51,683 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2018-11-23 13:18:51,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:51,858 INFO L225 Difference]: With dead ends: 98266 [2018-11-23 13:18:51,859 INFO L226 Difference]: Without dead ends: 98266 [2018-11-23 13:18:51,859 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:18:52,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98266 states. [2018-11-23 13:18:53,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98266 to 97571. [2018-11-23 13:18:53,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97571 states. [2018-11-23 13:18:53,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97571 states to 97571 states and 317548 transitions. [2018-11-23 13:18:53,392 INFO L78 Accepts]: Start accepts. Automaton has 97571 states and 317548 transitions. Word has length 113 [2018-11-23 13:18:53,392 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:53,392 INFO L480 AbstractCegarLoop]: Abstraction has 97571 states and 317548 transitions. [2018-11-23 13:18:53,392 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 13:18:53,392 INFO L276 IsEmpty]: Start isEmpty. Operand 97571 states and 317548 transitions. [2018-11-23 13:18:53,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 13:18:53,537 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:53,537 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:53,537 INFO L423 AbstractCegarLoop]: === Iteration 24 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:53,537 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:53,538 INFO L82 PathProgramCache]: Analyzing trace with hash 1836320102, now seen corresponding path program 3 times [2018-11-23 13:18:53,538 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:53,538 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:53,539 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:53,539 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:18:53,539 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:53,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:53,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:53,683 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:53,683 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-11-23 13:18:53,683 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 13:18:53,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 13:18:53,683 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=132, Unknown=0, NotChecked=0, Total=156 [2018-11-23 13:18:53,683 INFO L87 Difference]: Start difference. First operand 97571 states and 317548 transitions. Second operand 13 states. [2018-11-23 13:18:55,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:55,964 INFO L93 Difference]: Finished difference Result 185992 states and 605755 transitions. [2018-11-23 13:18:55,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 13:18:55,964 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 113 [2018-11-23 13:18:55,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:56,258 INFO L225 Difference]: With dead ends: 185992 [2018-11-23 13:18:56,258 INFO L226 Difference]: Without dead ends: 159501 [2018-11-23 13:18:56,259 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 18 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=152, Invalid=778, Unknown=0, NotChecked=0, Total=930 [2018-11-23 13:18:56,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159501 states. [2018-11-23 13:18:58,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159501 to 127706. [2018-11-23 13:18:58,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127706 states. [2018-11-23 13:18:58,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127706 states to 127706 states and 418141 transitions. [2018-11-23 13:18:58,427 INFO L78 Accepts]: Start accepts. Automaton has 127706 states and 418141 transitions. Word has length 113 [2018-11-23 13:18:58,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:18:58,427 INFO L480 AbstractCegarLoop]: Abstraction has 127706 states and 418141 transitions. [2018-11-23 13:18:58,427 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 13:18:58,427 INFO L276 IsEmpty]: Start isEmpty. Operand 127706 states and 418141 transitions. [2018-11-23 13:18:58,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 13:18:58,626 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:18:58,626 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:18:58,626 INFO L423 AbstractCegarLoop]: === Iteration 25 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:18:58,626 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:18:58,626 INFO L82 PathProgramCache]: Analyzing trace with hash -89858118, now seen corresponding path program 4 times [2018-11-23 13:18:58,626 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:18:58,626 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:18:58,628 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:58,628 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:18:58,628 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:18:59,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:18:59,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:18:59,062 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:18:59,062 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 13:18:59,063 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 13:18:59,063 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 13:18:59,063 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:18:59,063 INFO L87 Difference]: Start difference. First operand 127706 states and 418141 transitions. Second operand 3 states. [2018-11-23 13:18:59,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:18:59,613 INFO L93 Difference]: Finished difference Result 146581 states and 479131 transitions. [2018-11-23 13:18:59,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 13:18:59,614 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2018-11-23 13:18:59,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:18:59,889 INFO L225 Difference]: With dead ends: 146581 [2018-11-23 13:18:59,889 INFO L226 Difference]: Without dead ends: 146581 [2018-11-23 13:18:59,890 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 13:19:00,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146581 states. [2018-11-23 13:19:01,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146581 to 146156. [2018-11-23 13:19:01,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146156 states. [2018-11-23 13:19:02,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146156 states to 146156 states and 477881 transitions. [2018-11-23 13:19:02,046 INFO L78 Accepts]: Start accepts. Automaton has 146156 states and 477881 transitions. Word has length 113 [2018-11-23 13:19:02,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:19:02,046 INFO L480 AbstractCegarLoop]: Abstraction has 146156 states and 477881 transitions. [2018-11-23 13:19:02,046 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 13:19:02,046 INFO L276 IsEmpty]: Start isEmpty. Operand 146156 states and 477881 transitions. [2018-11-23 13:19:02,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 13:19:02,277 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:19:02,277 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:19:02,277 INFO L423 AbstractCegarLoop]: === Iteration 26 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:19:02,277 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:19:02,278 INFO L82 PathProgramCache]: Analyzing trace with hash -78541991, now seen corresponding path program 1 times [2018-11-23 13:19:02,278 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:19:02,278 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:19:02,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:19:02,279 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:19:02,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:19:02,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:19:02,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:19:02,370 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:19:02,370 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 13:19:02,370 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 13:19:02,370 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 13:19:02,370 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 13:19:02,371 INFO L87 Difference]: Start difference. First operand 146156 states and 477881 transitions. Second operand 4 states. [2018-11-23 13:19:03,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:19:03,305 INFO L93 Difference]: Finished difference Result 149056 states and 484586 transitions. [2018-11-23 13:19:03,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 13:19:03,305 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 113 [2018-11-23 13:19:03,305 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:19:03,585 INFO L225 Difference]: With dead ends: 149056 [2018-11-23 13:19:03,585 INFO L226 Difference]: Without dead ends: 149056 [2018-11-23 13:19:03,585 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 13:19:03,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149056 states. [2018-11-23 13:19:05,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149056 to 146576. [2018-11-23 13:19:05,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146576 states. [2018-11-23 13:19:05,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146576 states to 146576 states and 477217 transitions. [2018-11-23 13:19:05,868 INFO L78 Accepts]: Start accepts. Automaton has 146576 states and 477217 transitions. Word has length 113 [2018-11-23 13:19:05,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:19:05,868 INFO L480 AbstractCegarLoop]: Abstraction has 146576 states and 477217 transitions. [2018-11-23 13:19:05,868 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 13:19:05,868 INFO L276 IsEmpty]: Start isEmpty. Operand 146576 states and 477217 transitions. [2018-11-23 13:19:06,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 13:19:06,609 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:19:06,609 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:19:06,609 INFO L423 AbstractCegarLoop]: === Iteration 27 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:19:06,609 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:19:06,609 INFO L82 PathProgramCache]: Analyzing trace with hash -1104033990, now seen corresponding path program 1 times [2018-11-23 13:19:06,609 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:19:06,609 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:19:06,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:19:06,610 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:19:06,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:19:06,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:19:06,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:19:06,740 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:19:06,740 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-23 13:19:06,741 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 13:19:06,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 13:19:06,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-11-23 13:19:06,741 INFO L87 Difference]: Start difference. First operand 146576 states and 477217 transitions. Second operand 10 states. [2018-11-23 13:19:07,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:19:07,952 INFO L93 Difference]: Finished difference Result 198892 states and 645258 transitions. [2018-11-23 13:19:07,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 13:19:07,952 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 113 [2018-11-23 13:19:07,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:19:08,068 INFO L225 Difference]: With dead ends: 198892 [2018-11-23 13:19:08,068 INFO L226 Difference]: Without dead ends: 68656 [2018-11-23 13:19:08,068 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=62, Invalid=148, Unknown=0, NotChecked=0, Total=210 [2018-11-23 13:19:08,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68656 states. [2018-11-23 13:19:08,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68656 to 68656. [2018-11-23 13:19:08,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68656 states. [2018-11-23 13:19:08,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68656 states to 68656 states and 208821 transitions. [2018-11-23 13:19:08,950 INFO L78 Accepts]: Start accepts. Automaton has 68656 states and 208821 transitions. Word has length 113 [2018-11-23 13:19:08,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:19:08,950 INFO L480 AbstractCegarLoop]: Abstraction has 68656 states and 208821 transitions. [2018-11-23 13:19:08,951 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 13:19:08,951 INFO L276 IsEmpty]: Start isEmpty. Operand 68656 states and 208821 transitions. [2018-11-23 13:19:09,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 13:19:09,031 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:19:09,032 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:19:09,032 INFO L423 AbstractCegarLoop]: === Iteration 28 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:19:09,032 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:19:09,032 INFO L82 PathProgramCache]: Analyzing trace with hash 652208486, now seen corresponding path program 2 times [2018-11-23 13:19:09,032 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:19:09,032 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:19:09,034 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:19:09,034 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:19:09,034 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:19:09,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:19:09,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:19:09,120 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:19:09,120 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 13:19:09,120 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 13:19:09,121 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 13:19:09,121 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-11-23 13:19:09,121 INFO L87 Difference]: Start difference. First operand 68656 states and 208821 transitions. Second operand 8 states. [2018-11-23 13:19:09,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:19:09,724 INFO L93 Difference]: Finished difference Result 86323 states and 265183 transitions. [2018-11-23 13:19:09,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 13:19:09,724 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 113 [2018-11-23 13:19:09,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:19:09,748 INFO L225 Difference]: With dead ends: 86323 [2018-11-23 13:19:09,748 INFO L226 Difference]: Without dead ends: 17258 [2018-11-23 13:19:09,749 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2018-11-23 13:19:09,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17258 states. [2018-11-23 13:19:09,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17258 to 17256. [2018-11-23 13:19:09,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17256 states. [2018-11-23 13:19:09,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17256 states to 17256 states and 55598 transitions. [2018-11-23 13:19:09,961 INFO L78 Accepts]: Start accepts. Automaton has 17256 states and 55598 transitions. Word has length 113 [2018-11-23 13:19:09,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:19:09,962 INFO L480 AbstractCegarLoop]: Abstraction has 17256 states and 55598 transitions. [2018-11-23 13:19:09,962 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 13:19:09,962 INFO L276 IsEmpty]: Start isEmpty. Operand 17256 states and 55598 transitions. [2018-11-23 13:19:09,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 13:19:09,979 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:19:09,979 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:19:09,979 INFO L423 AbstractCegarLoop]: === Iteration 29 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:19:09,979 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:19:09,979 INFO L82 PathProgramCache]: Analyzing trace with hash 626634804, now seen corresponding path program 1 times [2018-11-23 13:19:09,979 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:19:09,979 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:19:09,980 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:19:09,980 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 13:19:09,980 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:19:09,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:19:10,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:19:10,101 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:19:10,102 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 13:19:10,102 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 13:19:10,102 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 13:19:10,102 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-23 13:19:10,102 INFO L87 Difference]: Start difference. First operand 17256 states and 55598 transitions. Second operand 8 states. [2018-11-23 13:19:10,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:19:10,371 INFO L93 Difference]: Finished difference Result 19348 states and 61859 transitions. [2018-11-23 13:19:10,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-23 13:19:10,372 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 113 [2018-11-23 13:19:10,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:19:10,397 INFO L225 Difference]: With dead ends: 19348 [2018-11-23 13:19:10,397 INFO L226 Difference]: Without dead ends: 19348 [2018-11-23 13:19:10,397 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=107, Unknown=0, NotChecked=0, Total=156 [2018-11-23 13:19:10,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19348 states. [2018-11-23 13:19:10,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19348 to 17460. [2018-11-23 13:19:10,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17460 states. [2018-11-23 13:19:10,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17460 states to 17460 states and 56167 transitions. [2018-11-23 13:19:10,678 INFO L78 Accepts]: Start accepts. Automaton has 17460 states and 56167 transitions. Word has length 113 [2018-11-23 13:19:10,678 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:19:10,678 INFO L480 AbstractCegarLoop]: Abstraction has 17460 states and 56167 transitions. [2018-11-23 13:19:10,679 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 13:19:10,679 INFO L276 IsEmpty]: Start isEmpty. Operand 17460 states and 56167 transitions. [2018-11-23 13:19:10,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 13:19:10,697 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:19:10,697 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:19:10,697 INFO L423 AbstractCegarLoop]: === Iteration 30 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:19:10,697 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:19:10,697 INFO L82 PathProgramCache]: Analyzing trace with hash 1514138485, now seen corresponding path program 1 times [2018-11-23 13:19:10,697 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:19:10,697 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:19:10,699 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:19:10,699 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:19:10,699 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:19:10,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 13:19:10,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 13:19:10,862 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 13:19:10,862 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-11-23 13:19:10,862 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 13:19:10,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 13:19:10,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=132, Unknown=0, NotChecked=0, Total=156 [2018-11-23 13:19:10,863 INFO L87 Difference]: Start difference. First operand 17460 states and 56167 transitions. Second operand 13 states. [2018-11-23 13:19:11,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 13:19:11,399 INFO L93 Difference]: Finished difference Result 27740 states and 87973 transitions. [2018-11-23 13:19:11,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 13:19:11,399 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 113 [2018-11-23 13:19:11,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 13:19:11,427 INFO L225 Difference]: With dead ends: 27740 [2018-11-23 13:19:11,427 INFO L226 Difference]: Without dead ends: 20858 [2018-11-23 13:19:11,427 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=75, Invalid=387, Unknown=0, NotChecked=0, Total=462 [2018-11-23 13:19:11,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20858 states. [2018-11-23 13:19:11,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20858 to 17747. [2018-11-23 13:19:11,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17747 states. [2018-11-23 13:19:11,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17747 states to 17747 states and 56886 transitions. [2018-11-23 13:19:11,660 INFO L78 Accepts]: Start accepts. Automaton has 17747 states and 56886 transitions. Word has length 113 [2018-11-23 13:19:11,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 13:19:11,660 INFO L480 AbstractCegarLoop]: Abstraction has 17747 states and 56886 transitions. [2018-11-23 13:19:11,660 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 13:19:11,660 INFO L276 IsEmpty]: Start isEmpty. Operand 17747 states and 56886 transitions. [2018-11-23 13:19:11,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 13:19:11,679 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 13:19:11,679 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 13:19:11,679 INFO L423 AbstractCegarLoop]: === Iteration 31 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 13:19:11,679 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 13:19:11,680 INFO L82 PathProgramCache]: Analyzing trace with hash -1575828745, now seen corresponding path program 2 times [2018-11-23 13:19:11,680 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 13:19:11,680 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 13:19:11,680 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:19:11,681 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 13:19:11,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 13:19:11,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:19:11,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 13:19:11,743 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [646] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [486] L-1-->L672: Formula: (= |v_#valid_13| (store |v_#valid_14| 0 0)) InVars {#valid=|v_#valid_14|} OutVars{#valid=|v_#valid_13|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [615] L672-->L674: Formula: (= v_~__unbuffered_cnt~0_8 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_8} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [668] L674-->L676: Formula: (= v_~__unbuffered_p0_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 [472] L676-->L678: Formula: (= v_~__unbuffered_p0_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p0_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [?] -1 [567] L678-->L680: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [623] L680-->L682: Formula: (= v_~__unbuffered_p2_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p2_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 [702] L682-->L684: Formula: (= v_~__unbuffered_p2_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p2_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 [526] L684-->L685: Formula: (= v_~a~0_3 0) InVars {} OutVars{~a~0=v_~a~0_3} AuxVars[] AssignedVars[~a~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 [667] L685-->L686: Formula: (= v_~main$tmp_guard0~0_3 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [?] -1 [571] L686-->L688: Formula: (= v_~main$tmp_guard1~0_3 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [659] L688-->L690: Formula: (= v_~x~0_2 0) InVars {} OutVars{~x~0=v_~x~0_2} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [708] L690-->L692: Formula: (= v_~y~0_3 0) InVars {} OutVars{~y~0=v_~y~0_3} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 [534] L692-->L693: Formula: (= v_~z~0_17 0) InVars {} OutVars{~z~0=v_~z~0_17} AuxVars[] AssignedVars[~z~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [699] L693-->L694: Formula: (= v_~z$flush_delayed~0_9 0) InVars {} OutVars{~z$flush_delayed~0=v_~z$flush_delayed~0_9} AuxVars[] AssignedVars[~z$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 [613] L694-->L695: Formula: (= v_~z$mem_tmp~0_5 0) InVars {} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_5} AuxVars[] AssignedVars[~z$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 [524] L695-->L696: Formula: (= v_~z$r_buff0_thd0~0_13 0) InVars {} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_13} AuxVars[] AssignedVars[~z$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 [666] L696-->L697: Formula: (= v_~z$r_buff0_thd1~0_2 0) InVars {} OutVars{~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_2} AuxVars[] AssignedVars[~z$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 [570] L697-->L698: Formula: (= v_~z$r_buff0_thd2~0_32 0) InVars {} OutVars{~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32} AuxVars[] AssignedVars[~z$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 [503] L698-->L699: Formula: (= v_~z$r_buff0_thd3~0_44 0) InVars {} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_44} AuxVars[] AssignedVars[~z$r_buff0_thd3~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 [658] L699-->L700: Formula: (= v_~z$r_buff1_thd0~0_9 0) InVars {} OutVars{~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_9} AuxVars[] AssignedVars[~z$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 [566] L700-->L701: Formula: (= v_~z$r_buff1_thd1~0_2 0) InVars {} OutVars{~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_2} AuxVars[] AssignedVars[~z$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 [707] L701-->L702: Formula: (= v_~z$r_buff1_thd2~0_18 0) InVars {} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_18} AuxVars[] AssignedVars[~z$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 [619] L702-->L703: Formula: (= v_~z$r_buff1_thd3~0_25 0) InVars {} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_25} AuxVars[] AssignedVars[~z$r_buff1_thd3~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 [560] L703-->L704: Formula: (= v_~z$read_delayed~0_1 0) InVars {} OutVars{~z$read_delayed~0=v_~z$read_delayed~0_1} AuxVars[] AssignedVars[~z$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [698] L704-->L705: Formula: (and (= v_~z$read_delayed_var~0.offset_1 0) (= v_~z$read_delayed_var~0.base_1 0)) InVars {} OutVars{~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_1, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [612] L705-->L706: Formula: (= v_~z$w_buff0~0_16 0) InVars {} OutVars{~z$w_buff0~0=v_~z$w_buff0~0_16} AuxVars[] AssignedVars[~z$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [521] L706-->L707: Formula: (= v_~z$w_buff0_used~0_74 0) InVars {} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_74} AuxVars[] AssignedVars[~z$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [665] L707-->L708: Formula: (= v_~z$w_buff1~0_15 0) InVars {} OutVars{~z$w_buff1~0=v_~z$w_buff1~0_15} AuxVars[] AssignedVars[~z$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [569] L708-->L709: Formula: (= v_~z$w_buff1_used~0_41 0) InVars {} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_41} AuxVars[] AssignedVars[~z$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [499] L709-->L710: Formula: (= v_~weak$$choice0~0_3 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_3} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [657] L710-->L-1-1: Formula: (= v_~weak$$choice2~0_27 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_27} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [701] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [697] L-1-2-->L816: Formula: true InVars {} OutVars{ULTIMATE.start_main_~#t410~0.offset=|v_ULTIMATE.start_main_~#t410~0.offset_1|, ULTIMATE.start_main_#t~nondet58=|v_ULTIMATE.start_main_#t~nondet58_1|, ULTIMATE.start_main_~#t408~0.base=|v_ULTIMATE.start_main_~#t408~0.base_1|, ULTIMATE.start_main_~#t408~0.offset=|v_ULTIMATE.start_main_~#t408~0.offset_1|, ULTIMATE.start_main_#t~nondet60=|v_ULTIMATE.start_main_#t~nondet60_1|, ULTIMATE.start_main_#t~ite66=|v_ULTIMATE.start_main_#t~ite66_1|, ULTIMATE.start_main_#t~ite64=|v_ULTIMATE.start_main_#t~ite64_1|, ULTIMATE.start_main_#t~ite65=|v_ULTIMATE.start_main_#t~ite65_1|, ULTIMATE.start_main_#t~ite62=|v_ULTIMATE.start_main_#t~ite62_1|, ULTIMATE.start_main_#t~ite63=|v_ULTIMATE.start_main_#t~ite63_1|, ULTIMATE.start_main_#t~ite61=|v_ULTIMATE.start_main_#t~ite61_1|, ULTIMATE.start_main_~#t410~0.base=|v_ULTIMATE.start_main_~#t410~0.base_1|, ULTIMATE.start_main_~#t409~0.offset=|v_ULTIMATE.start_main_~#t409~0.offset_1|, ULTIMATE.start_main_#t~nondet59=|v_ULTIMATE.start_main_#t~nondet59_1|, ULTIMATE.start_main_~#t409~0.base=|v_ULTIMATE.start_main_~#t409~0.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t410~0.offset, ULTIMATE.start_main_#t~nondet58, ULTIMATE.start_main_~#t408~0.base, ULTIMATE.start_main_~#t408~0.offset, ULTIMATE.start_main_#t~nondet60, ULTIMATE.start_main_#t~ite66, ULTIMATE.start_main_#t~ite64, ULTIMATE.start_main_#t~ite65, ULTIMATE.start_main_#t~ite62, ULTIMATE.start_main_#t~ite63, ULTIMATE.start_main_#t~ite61, ULTIMATE.start_main_~#t410~0.base, ULTIMATE.start_main_~#t409~0.offset, ULTIMATE.start_main_#t~nondet59, ULTIMATE.start_main_~#t409~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [548] L816-->L816-1: Formula: (and (= |v_ULTIMATE.start_main_~#t408~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_main_~#t408~0.base_2|)) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t408~0.base_2|) 0) (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t408~0.base_2| 1) |v_#valid_1|) (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t408~0.base_2| 4) |v_#length_1|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{ULTIMATE.start_main_~#t408~0.offset=|v_ULTIMATE.start_main_~#t408~0.offset_2|, #length=|v_#length_1|, ULTIMATE.start_main_~#t408~0.base=|v_ULTIMATE.start_main_~#t408~0.base_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t408~0.base, #valid, ULTIMATE.start_main_~#t408~0.offset, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [554] L816-1-->L817: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t408~0.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t408~0.base_3|) |v_ULTIMATE.start_main_~#t408~0.offset_3| 0))) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t408~0.offset=|v_ULTIMATE.start_main_~#t408~0.offset_3|, ULTIMATE.start_main_~#t408~0.base=|v_ULTIMATE.start_main_~#t408~0.base_3|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t408~0.offset=|v_ULTIMATE.start_main_~#t408~0.offset_3|, ULTIMATE.start_main_~#t408~0.base=|v_ULTIMATE.start_main_~#t408~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [877] L817-->P0ENTRY: Formula: (and (= 0 |v_Thread2_P0_#in~arg.base_3|) (= |v_Thread2_P0_#in~arg.offset_3| 0) (= v_Thread2_P0_thidvar0_2 0)) InVars {} OutVars{Thread2_P0_#in~arg.base=|v_Thread2_P0_#in~arg.base_3|, Thread2_P0_thidvar0=v_Thread2_P0_thidvar0_2, Thread2_P0_#in~arg.offset=|v_Thread2_P0_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread2_P0_#in~arg.base, Thread2_P0_thidvar0, Thread2_P0_#in~arg.offset] VAL [Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [687] L817-1-->L818: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet58=|v_ULTIMATE.start_main_#t~nondet58_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet58] VAL [Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [592] L818-->L818-1: Formula: (and (not (= |v_ULTIMATE.start_main_~#t409~0.base_2| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t409~0.base_2| 4)) (= |v_ULTIMATE.start_main_~#t409~0.offset_2| 0) (= (select |v_#valid_4| |v_ULTIMATE.start_main_~#t409~0.base_2|) 0) (= |v_#valid_3| (store |v_#valid_4| |v_ULTIMATE.start_main_~#t409~0.base_2| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{ULTIMATE.start_main_~#t409~0.offset=|v_ULTIMATE.start_main_~#t409~0.offset_2|, #length=|v_#length_3|, #valid=|v_#valid_3|, ULTIMATE.start_main_~#t409~0.base=|v_ULTIMATE.start_main_~#t409~0.base_2|} AuxVars[] AssignedVars[#valid, ULTIMATE.start_main_~#t409~0.offset, #length, ULTIMATE.start_main_~#t409~0.base] VAL [Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [596] L818-1-->L819: Formula: (= |v_#memory_int_3| (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t409~0.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t409~0.base_3|) |v_ULTIMATE.start_main_~#t409~0.offset_3| 1))) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t409~0.offset=|v_ULTIMATE.start_main_~#t409~0.offset_3|, ULTIMATE.start_main_~#t409~0.base=|v_ULTIMATE.start_main_~#t409~0.base_3|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t409~0.offset=|v_ULTIMATE.start_main_~#t409~0.offset_3|, ULTIMATE.start_main_~#t409~0.base=|v_ULTIMATE.start_main_~#t409~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [875] L819-->P1ENTRY: Formula: (and (= 0 |v_Thread0_P1_#in~arg.offset_3|) (= 1 v_Thread0_P1_thidvar0_2) (= 0 |v_Thread0_P1_#in~arg.base_3|)) InVars {} OutVars{Thread0_P1_thidvar0=v_Thread0_P1_thidvar0_2, Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_3|, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P1_thidvar0, Thread0_P1_#in~arg.base, Thread0_P1_#in~arg.offset] VAL [Thread0_P1_thidvar0=1, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [494] L819-1-->L820: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet59=|v_ULTIMATE.start_main_#t~nondet59_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet59] VAL [Thread0_P1_thidvar0=1, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [643] L820-->L820-1: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t410~0.offset_2|) (= |v_#valid_5| (store |v_#valid_6| |v_ULTIMATE.start_main_~#t410~0.base_2| 1)) (= |v_#length_5| (store |v_#length_6| |v_ULTIMATE.start_main_~#t410~0.base_2| 4)) (= 0 (select |v_#valid_6| |v_ULTIMATE.start_main_~#t410~0.base_2|)) (not (= |v_ULTIMATE.start_main_~#t410~0.base_2| 0))) InVars {#length=|v_#length_6|, #valid=|v_#valid_6|} OutVars{#length=|v_#length_5|, ULTIMATE.start_main_~#t410~0.offset=|v_ULTIMATE.start_main_~#t410~0.offset_2|, ULTIMATE.start_main_~#t410~0.base=|v_ULTIMATE.start_main_~#t410~0.base_2|, #valid=|v_#valid_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t410~0.offset, ULTIMATE.start_main_~#t410~0.base, #valid, #length] VAL [Thread0_P1_thidvar0=1, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [649] L820-1-->L821: Formula: (= (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#t410~0.base_3| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#t410~0.base_3|) |v_ULTIMATE.start_main_~#t410~0.offset_3| 2)) |v_#memory_int_5|) InVars {#memory_int=|v_#memory_int_6|, ULTIMATE.start_main_~#t410~0.offset=|v_ULTIMATE.start_main_~#t410~0.offset_3|, ULTIMATE.start_main_~#t410~0.base=|v_ULTIMATE.start_main_~#t410~0.base_3|} OutVars{#memory_int=|v_#memory_int_5|, ULTIMATE.start_main_~#t410~0.offset=|v_ULTIMATE.start_main_~#t410~0.offset_3|, ULTIMATE.start_main_~#t410~0.base=|v_ULTIMATE.start_main_~#t410~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [Thread0_P1_thidvar0=1, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [876] L821-->P2ENTRY: Formula: (and (= |v_Thread1_P2_#in~arg.offset_3| 0) (= 2 v_Thread1_P2_thidvar0_2) (= 0 |v_Thread1_P2_#in~arg.base_3|)) InVars {} OutVars{Thread1_P2_#in~arg.base=|v_Thread1_P2_#in~arg.base_3|, Thread1_P2_thidvar0=v_Thread1_P2_thidvar0_2, Thread1_P2_#in~arg.offset=|v_Thread1_P2_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_P2_#in~arg.base, Thread1_P2_thidvar0, Thread1_P2_#in~arg.offset] VAL [Thread0_P1_thidvar0=1, Thread1_P2_thidvar0=2, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [785] P2ENTRY-->L4: Formula: (and (= v_Thread1_P2_~arg.offset_1 |v_Thread1_P2_#in~arg.offset_1|) (= v_Thread1_P2___VERIFIER_assert_~expression_1 |v_Thread1_P2___VERIFIER_assert_#in~expression_1|) (= v_Thread1_P2_~arg.base_1 |v_Thread1_P2_#in~arg.base_1|) (= v_~z$w_buff0_used~0_37 1) (= v_~z$w_buff0~0_7 1) (= v_~z$w_buff1~0_7 v_~z$w_buff0~0_8) (= v_~z$w_buff1_used~0_20 v_~z$w_buff0_used~0_38) (= |v_Thread1_P2___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~z$w_buff0_used~0_37 256))) (not (= (mod v_~z$w_buff1_used~0_20 256) 0)))) 1 0))) InVars {Thread1_P2_#in~arg.base=|v_Thread1_P2_#in~arg.base_1|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_38, ~z$w_buff0~0=v_~z$w_buff0~0_8, Thread1_P2_#in~arg.offset=|v_Thread1_P2_#in~arg.offset_1|} OutVars{Thread1_P2_#in~arg.base=|v_Thread1_P2_#in~arg.base_1|, Thread1_P2_~arg.offset=v_Thread1_P2_~arg.offset_1, Thread1_P2___VERIFIER_assert_~expression=v_Thread1_P2___VERIFIER_assert_~expression_1, Thread1_P2___VERIFIER_assert_#in~expression=|v_Thread1_P2___VERIFIER_assert_#in~expression_1|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_37, ~z$w_buff0~0=v_~z$w_buff0~0_7, Thread1_P2_~arg.base=v_Thread1_P2_~arg.base_1, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_20, ~z$w_buff1~0=v_~z$w_buff1~0_7, Thread1_P2_#in~arg.offset=|v_Thread1_P2_#in~arg.offset_1|} AuxVars[] AssignedVars[Thread1_P2_~arg.offset, Thread1_P2___VERIFIER_assert_~expression, Thread1_P2___VERIFIER_assert_#in~expression, ~z$w_buff0_used~0, ~z$w_buff0~0, Thread1_P2_~arg.base, ~z$w_buff1_used~0, ~z$w_buff1~0] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [787] L4-->L4-3: Formula: (not (= 0 v_Thread1_P2___VERIFIER_assert_~expression_3)) InVars {Thread1_P2___VERIFIER_assert_~expression=v_Thread1_P2___VERIFIER_assert_~expression_3} OutVars{Thread1_P2___VERIFIER_assert_~expression=v_Thread1_P2___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [790] L4-3-->L779: Formula: (and (= v_~z$r_buff1_thd2~0_17 v_~z$r_buff0_thd2~0_31) (= v_~z$flush_delayed~0_5 v_~weak$$choice2~0_18) (= v_~weak$$choice0~0_2 (ite (= 0 (+ |v_Thread1_P2_#t~nondet28.base_1| |v_Thread1_P2_#t~nondet28.offset_1|)) 0 1)) (= v_~weak$$choice2~0_18 (ite (= (+ |v_Thread1_P2_#t~nondet29.base_1| |v_Thread1_P2_#t~nondet29.offset_1|) 0) 0 1)) (= v_~z$r_buff1_thd1~0_1 v_~z$r_buff0_thd1~0_1) (= v_~z$mem_tmp~0_3 v_~z~0_7) (= v_~z$r_buff1_thd0~0_1 v_~z$r_buff0_thd0~0_1) (= v_~z$r_buff0_thd3~0_10 1) (= v_~z$r_buff1_thd3~0_5 v_~z$r_buff0_thd3~0_11)) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, Thread1_P2_#t~nondet29.offset=|v_Thread1_P2_#t~nondet29.offset_1|, Thread1_P2_#t~nondet28.base=|v_Thread1_P2_#t~nondet28.base_1|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_11, Thread1_P2_#t~nondet29.base=|v_Thread1_P2_#t~nondet29.base_1|, ~z~0=v_~z~0_7, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_1, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_31, Thread1_P2_#t~nondet28.offset=|v_Thread1_P2_#t~nondet28.offset_1|} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_3, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_5, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_17, Thread1_P2_#t~nondet28.base=|v_Thread1_P2_#t~nondet28.base_2|, Thread1_P2_#t~nondet29.base=|v_Thread1_P2_#t~nondet29.base_2|, ~z$flush_delayed~0=v_~z$flush_delayed~0_5, ~weak$$choice0~0=v_~weak$$choice0~0_2, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_1, Thread1_P2_#t~nondet29.offset=|v_Thread1_P2_#t~nondet29.offset_2|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_1, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_10, ~z~0=v_~z~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_18, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_1, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_31, Thread1_P2_#t~nondet28.offset=|v_Thread1_P2_#t~nondet28.offset_2|} AuxVars[] AssignedVars[~z$mem_tmp~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd2~0, Thread1_P2_#t~nondet28.base, Thread1_P2_#t~nondet29.base, ~z$flush_delayed~0, ~weak$$choice0~0, ~z$r_buff1_thd0~0, Thread1_P2_#t~nondet29.offset, ~z$r_buff1_thd1~0, ~z$r_buff0_thd3~0, ~weak$$choice2~0, Thread1_P2_#t~nondet28.offset] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [792] L779-->L779-2: Formula: (let ((.cse0 (not (= 0 (mod v_~z$r_buff0_thd3~0_15 256))))) (and (not (= 0 (mod v_~z$w_buff0_used~0_43 256))) (or .cse0 (not (= 0 (mod v_~z$w_buff1_used~0_24 256)))) (or (not (= (mod v_~z$r_buff1_thd3~0_8 256) 0)) .cse0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_24, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_15, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_43, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_8} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_24, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_15, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_43, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_8} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [794] L779-2-->L779-4: Formula: (and (= |v_Thread1_P2_#t~ite30_2| v_~z$w_buff0~0_9) (not (= 0 (mod v_~z$r_buff0_thd3~0_17 256))) (not (= 0 (mod v_~z$w_buff0_used~0_45 256)))) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_17, ~z$w_buff0~0=v_~z$w_buff0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_45} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_17, Thread1_P2_#t~ite30=|v_Thread1_P2_#t~ite30_2|, ~z$w_buff0~0=v_~z$w_buff0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_45} AuxVars[] AssignedVars[Thread1_P2_#t~ite30] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite30|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [798] L779-4-->L779-5: Formula: (= |v_Thread1_P2_#t~ite31_4| |v_Thread1_P2_#t~ite30_4|) InVars {Thread1_P2_#t~ite30=|v_Thread1_P2_#t~ite30_4|} OutVars{Thread1_P2_#t~ite30=|v_Thread1_P2_#t~ite30_4|, Thread1_P2_#t~ite31=|v_Thread1_P2_#t~ite31_4|} AuxVars[] AssignedVars[Thread1_P2_#t~ite31] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite30|=1, |Thread1_P2_#t~ite31|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [793] L779-5-->L780: Formula: (= v_~z~0_10 |v_Thread1_P2_#t~ite31_2|) InVars {Thread1_P2_#t~ite31=|v_Thread1_P2_#t~ite31_2|} OutVars{~z~0=v_~z~0_10, Thread1_P2_#t~ite30=|v_Thread1_P2_#t~ite30_1|, Thread1_P2_#t~ite31=|v_Thread1_P2_#t~ite31_3|} AuxVars[] AssignedVars[Thread1_P2_#t~ite30, Thread1_P2_#t~ite31, ~z~0] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [796] L780-->L780-8: Formula: (and (= |v_Thread1_P2_#t~ite34_1| v_~z$w_buff0~0_10) (not (= (mod v_~weak$$choice2~0_19 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_19, ~z$w_buff0~0=v_~z$w_buff0~0_10} OutVars{Thread1_P2_#t~ite34=|v_Thread1_P2_#t~ite34_1|, ~weak$$choice2~0=v_~weak$$choice2~0_19, ~z$w_buff0~0=v_~z$w_buff0~0_10} AuxVars[] AssignedVars[Thread1_P2_#t~ite34] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite34|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [799] L780-8-->L781: Formula: (= v_~z$w_buff0~0_15 |v_Thread1_P2_#t~ite34_2|) InVars {Thread1_P2_#t~ite34=|v_Thread1_P2_#t~ite34_2|} OutVars{Thread1_P2_#t~ite34=|v_Thread1_P2_#t~ite34_3|, Thread1_P2_#t~ite32=|v_Thread1_P2_#t~ite32_1|, Thread1_P2_#t~ite33=|v_Thread1_P2_#t~ite33_1|, ~z$w_buff0~0=v_~z$w_buff0~0_15} AuxVars[] AssignedVars[~z$w_buff0~0, Thread1_P2_#t~ite34, Thread1_P2_#t~ite32, Thread1_P2_#t~ite33] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [802] L781-->L781-8: Formula: (and (not (= (mod v_~weak$$choice2~0_21 256) 0)) (= |v_Thread1_P2_#t~ite37_1| v_~z$w_buff1~0_10)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_21, ~z$w_buff1~0=v_~z$w_buff1~0_10} OutVars{~z$w_buff1~0=v_~z$w_buff1~0_10, ~weak$$choice2~0=v_~weak$$choice2~0_21, Thread1_P2_#t~ite37=|v_Thread1_P2_#t~ite37_1|} AuxVars[] AssignedVars[Thread1_P2_#t~ite37] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite37|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [807] L781-8-->L782: Formula: (= v_~z$w_buff1~0_14 |v_Thread1_P2_#t~ite37_2|) InVars {Thread1_P2_#t~ite37=|v_Thread1_P2_#t~ite37_2|} OutVars{~z$w_buff1~0=v_~z$w_buff1~0_14, Thread1_P2_#t~ite35=|v_Thread1_P2_#t~ite35_1|, Thread1_P2_#t~ite36=|v_Thread1_P2_#t~ite36_1|, Thread1_P2_#t~ite37=|v_Thread1_P2_#t~ite37_3|} AuxVars[] AssignedVars[~z$w_buff1~0, Thread1_P2_#t~ite35, Thread1_P2_#t~ite36, Thread1_P2_#t~ite37] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [811] L782-->L782-8: Formula: (and (= |v_Thread1_P2_#t~ite40_1| v_~z$w_buff0_used~0_65) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_23, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_65} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_23, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_65, Thread1_P2_#t~ite40=|v_Thread1_P2_#t~ite40_1|} AuxVars[] AssignedVars[Thread1_P2_#t~ite40] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite40|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [816] L782-8-->L783: Formula: (= v_~z$w_buff0_used~0_71 |v_Thread1_P2_#t~ite40_2|) InVars {Thread1_P2_#t~ite40=|v_Thread1_P2_#t~ite40_2|} OutVars{Thread1_P2_#t~ite38=|v_Thread1_P2_#t~ite38_1|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_71, Thread1_P2_#t~ite39=|v_Thread1_P2_#t~ite39_1|, Thread1_P2_#t~ite40=|v_Thread1_P2_#t~ite40_3|} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread1_P2_#t~ite40, Thread1_P2_#t~ite38, Thread1_P2_#t~ite39] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [820] L783-->L783-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_25 256))) (= |v_Thread1_P2_#t~ite43_1| v_~z$w_buff1_used~0_38)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_38, ~weak$$choice2~0=v_~weak$$choice2~0_25} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_38, Thread1_P2_#t~ite43=|v_Thread1_P2_#t~ite43_1|, ~weak$$choice2~0=v_~weak$$choice2~0_25} AuxVars[] AssignedVars[Thread1_P2_#t~ite43] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite43|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [825] L783-8-->L784: Formula: (= v_~z$w_buff1_used~0_17 |v_Thread1_P2_#t~ite43_2|) InVars {Thread1_P2_#t~ite43=|v_Thread1_P2_#t~ite43_2|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, Thread1_P2_#t~ite43=|v_Thread1_P2_#t~ite43_3|, Thread1_P2_#t~ite41=|v_Thread1_P2_#t~ite41_1|, Thread1_P2_#t~ite42=|v_Thread1_P2_#t~ite42_1|} AuxVars[] AssignedVars[Thread1_P2_#t~ite41, Thread1_P2_#t~ite42, ~z$w_buff1_used~0, Thread1_P2_#t~ite43] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [829] L784-->L784-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_14 256))) (= |v_Thread1_P2_#t~ite46_1| v_~z$r_buff0_thd3~0_3)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_14, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_3} OutVars{Thread1_P2_#t~ite46=|v_Thread1_P2_#t~ite46_1|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_3, ~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[Thread1_P2_#t~ite46] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite46|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [834] L784-8-->L785: Formula: (= v_~z$r_buff0_thd3~0_8 |v_Thread1_P2_#t~ite46_2|) InVars {Thread1_P2_#t~ite46=|v_Thread1_P2_#t~ite46_2|} OutVars{Thread1_P2_#t~ite45=|v_Thread1_P2_#t~ite45_1|, Thread1_P2_#t~ite46=|v_Thread1_P2_#t~ite46_3|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_8, Thread1_P2_#t~ite44=|v_Thread1_P2_#t~ite44_1|} AuxVars[] AssignedVars[Thread1_P2_#t~ite45, Thread1_P2_#t~ite46, ~z$r_buff0_thd3~0, Thread1_P2_#t~ite44] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [838] L785-->L785-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_16 256))) (= |v_Thread1_P2_#t~ite49_1| v_~z$r_buff1_thd3~0_3)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_16, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_3} OutVars{Thread1_P2_#t~ite49=|v_Thread1_P2_#t~ite49_1|, ~weak$$choice2~0=v_~weak$$choice2~0_16, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_3} AuxVars[] AssignedVars[Thread1_P2_#t~ite49] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite49|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [843] L785-8-->L787: Formula: (and (= v_~z$r_buff1_thd3~0_9 |v_Thread1_P2_#t~ite49_2|) (= v_~__unbuffered_p2_EAX~0_1 v_~z~0_9)) InVars {Thread1_P2_#t~ite49=|v_Thread1_P2_#t~ite49_2|, ~z~0=v_~z~0_9} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_9, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_1, ~z~0=v_~z~0_9, Thread1_P2_#t~ite49=|v_Thread1_P2_#t~ite49_3|, Thread1_P2_#t~ite47=|v_Thread1_P2_#t~ite47_1|, Thread1_P2_#t~ite48=|v_Thread1_P2_#t~ite48_1|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, ~__unbuffered_p2_EAX~0, Thread1_P2_#t~ite49, Thread1_P2_#t~ite47, Thread1_P2_#t~ite48] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [847] L787-->L787-2: Formula: (and (not (= (mod v_~z$flush_delayed~0_6 256) 0)) (= |v_Thread1_P2_#t~ite50_1| v_~z$mem_tmp~0_4)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_4, ~z$flush_delayed~0=v_~z$flush_delayed~0_6} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_4, ~z$flush_delayed~0=v_~z$flush_delayed~0_6, Thread1_P2_#t~ite50=|v_Thread1_P2_#t~ite50_1|} AuxVars[] AssignedVars[Thread1_P2_#t~ite50] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite50|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [852] L787-2-->L794: Formula: (and (= v_~__unbuffered_p2_EBX~0_1 v_~a~0_2) (= v_~z~0_12 |v_Thread1_P2_#t~ite50_3|) (= v_~z$flush_delayed~0_8 0)) InVars {~a~0=v_~a~0_2, Thread1_P2_#t~ite50=|v_Thread1_P2_#t~ite50_3|} OutVars{~a~0=v_~a~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_1, ~z$flush_delayed~0=v_~z$flush_delayed~0_8, ~z~0=v_~z~0_12, Thread1_P2_#t~ite50=|v_Thread1_P2_#t~ite50_4|} AuxVars[] AssignedVars[~__unbuffered_p2_EBX~0, Thread1_P2_#t~ite50, ~z$flush_delayed~0, ~z~0] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [854] L794-->L794-5: Formula: (and (= |v_Thread1_P2_#t~ite52_1| v_~z$w_buff0~0_12) (not (= 0 (mod v_~z$w_buff0_used~0_48 256))) (not (= 0 (mod v_~z$r_buff0_thd3~0_20 256)))) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_20, ~z$w_buff0~0=v_~z$w_buff0~0_12, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_48} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_20, Thread1_P2_#t~ite52=|v_Thread1_P2_#t~ite52_1|, ~z$w_buff0~0=v_~z$w_buff0~0_12, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_48} AuxVars[] AssignedVars[Thread1_P2_#t~ite52] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [714] P0ENTRY-->L730: Formula: (and (= v_~a~0_1 1) (= v_Thread2_P0_~arg.base_1 |v_Thread2_P0_#in~arg.base_1|) (= v_Thread2_P0_~arg.offset_1 |v_Thread2_P0_#in~arg.offset_1|) (= v_~__unbuffered_p0_EAX~0_1 v_~x~0_1) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1)) (= v_~x~0_1 1) (= v_~__unbuffered_p0_EBX~0_1 v_~y~0_1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2, Thread2_P0_#in~arg.base=|v_Thread2_P0_#in~arg.base_1|, ~y~0=v_~y~0_1, Thread2_P0_#in~arg.offset=|v_Thread2_P0_#in~arg.offset_1|} OutVars{~a~0=v_~a~0_1, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_1, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_1, Thread2_P0_#in~arg.base=|v_Thread2_P0_#in~arg.base_1|, Thread2_P0_~arg.offset=v_Thread2_P0_~arg.offset_1, Thread2_P0_~arg.base=v_Thread2_P0_~arg.base_1, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~y~0=v_~y~0_1, ~x~0=v_~x~0_1, Thread2_P0_#in~arg.offset=|v_Thread2_P0_#in~arg.offset_1|} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p0_EAX~0, ~__unbuffered_p0_EBX~0, Thread2_P0_~arg.offset, Thread2_P0_~arg.base, ~__unbuffered_cnt~0, ~x~0] VAL [Thread0_P1_thidvar0=1, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [718] P1ENTRY-->L742: Formula: (and (= v_Thread0_P1_~arg.offset_1 |v_Thread0_P1_#in~arg.offset_1|) (= v_~z$mem_tmp~0_1 v_~z~0_1) (= v_~weak$$choice2~0_2 (ite (= (+ |v_Thread0_P1_#t~nondet5.base_1| |v_Thread0_P1_#t~nondet5.offset_1|) 0) 0 1)) (= v_Thread0_P1_~arg.base_1 |v_Thread0_P1_#in~arg.base_1|) (= v_~weak$$choice0~0_1 (ite (= (+ |v_Thread0_P1_#t~nondet4.base_1| |v_Thread0_P1_#t~nondet4.offset_1|) 0) 0 1)) (= v_~z$flush_delayed~0_1 v_~weak$$choice2~0_2) (= v_~y~0_2 1)) InVars {Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_1|, Thread0_P1_#t~nondet4.base=|v_Thread0_P1_#t~nondet4.base_1|, Thread0_P1_#t~nondet5.offset=|v_Thread0_P1_#t~nondet5.offset_1|, Thread0_P1_#t~nondet5.base=|v_Thread0_P1_#t~nondet5.base_1|, Thread0_P1_#t~nondet4.offset=|v_Thread0_P1_#t~nondet4.offset_1|, ~z~0=v_~z~0_1, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_1|} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_1, Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_1|, Thread0_P1_~arg.offset=v_Thread0_P1_~arg.offset_1, Thread0_P1_#t~nondet4.offset=|v_Thread0_P1_#t~nondet4.offset_2|, ~z$flush_delayed~0=v_~z$flush_delayed~0_1, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_1|, ~weak$$choice0~0=v_~weak$$choice0~0_1, Thread0_P1_#t~nondet4.base=|v_Thread0_P1_#t~nondet4.base_2|, Thread0_P1_~arg.base=v_Thread0_P1_~arg.base_1, Thread0_P1_#t~nondet5.offset=|v_Thread0_P1_#t~nondet5.offset_2|, Thread0_P1_#t~nondet5.base=|v_Thread0_P1_#t~nondet5.base_2|, ~z~0=v_~z~0_1, ~weak$$choice2~0=v_~weak$$choice2~0_2, ~y~0=v_~y~0_2} AuxVars[] AssignedVars[~z$mem_tmp~0, ~weak$$choice0~0, Thread0_P1_~arg.offset, Thread0_P1_#t~nondet4.base, Thread0_P1_~arg.base, Thread0_P1_#t~nondet5.offset, Thread0_P1_#t~nondet4.offset, Thread0_P1_#t~nondet5.base, ~z$flush_delayed~0, ~weak$$choice2~0, ~y~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [719] L742-->L742-5: Formula: (and (let ((.cse0 (= (mod v_~z$r_buff0_thd2~0_3 256) 0))) (or (and .cse0 (= 0 (mod v_~z$r_buff1_thd2~0_3 256))) (= (mod v_~z$w_buff0_used~0_3 256) 0) (and (= 0 (mod v_~z$w_buff1_used~0_3 256)) .cse0))) (= |v_Thread0_P1_#t~ite7_1| v_~z~0_2)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_3, ~z~0=v_~z~0_2, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_3, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_3, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_3} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_3, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_3, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_3, Thread0_P1_#t~ite7=|v_Thread0_P1_#t~ite7_1|, ~z~0=v_~z~0_2, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_3} AuxVars[] AssignedVars[Thread0_P1_#t~ite7] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite7|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [721] L742-5-->L743: Formula: (= v_~z~0_4 |v_Thread0_P1_#t~ite7_2|) InVars {Thread0_P1_#t~ite7=|v_Thread0_P1_#t~ite7_2|} OutVars{Thread0_P1_#t~ite7=|v_Thread0_P1_#t~ite7_3|, ~z~0=v_~z~0_4, Thread0_P1_#t~ite6=|v_Thread0_P1_#t~ite6_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite7, ~z~0, Thread0_P1_#t~ite6] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [724] L743-->L743-8: Formula: (and (= |v_Thread0_P1_#t~ite10_1| v_~z$w_buff0~0_2) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_2} OutVars{Thread0_P1_#t~ite10=|v_Thread0_P1_#t~ite10_1|, ~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_2} AuxVars[] AssignedVars[Thread0_P1_#t~ite10] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite10|=1, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [727] L743-8-->L744: Formula: (= v_~z$w_buff0~0_6 |v_Thread0_P1_#t~ite10_2|) InVars {Thread0_P1_#t~ite10=|v_Thread0_P1_#t~ite10_2|} OutVars{Thread0_P1_#t~ite10=|v_Thread0_P1_#t~ite10_3|, Thread0_P1_#t~ite8=|v_Thread0_P1_#t~ite8_1|, Thread0_P1_#t~ite9=|v_Thread0_P1_#t~ite9_1|, ~z$w_buff0~0=v_~z$w_buff0~0_6} AuxVars[] AssignedVars[Thread0_P1_#t~ite9, ~z$w_buff0~0, Thread0_P1_#t~ite10, Thread0_P1_#t~ite8] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [730] L744-->L744-8: Formula: (and (= |v_Thread0_P1_#t~ite13_1| v_~z$w_buff1~0_2) (not (= 0 (mod v_~weak$$choice2~0_5 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~z$w_buff1~0=v_~z$w_buff1~0_2} OutVars{~z$w_buff1~0=v_~z$w_buff1~0_2, Thread0_P1_#t~ite13=|v_Thread0_P1_#t~ite13_1|, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[Thread0_P1_#t~ite13] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite13|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [735] L744-8-->L745: Formula: (= v_~z$w_buff1~0_6 |v_Thread0_P1_#t~ite13_2|) InVars {Thread0_P1_#t~ite13=|v_Thread0_P1_#t~ite13_2|} OutVars{Thread0_P1_#t~ite11=|v_Thread0_P1_#t~ite11_1|, ~z$w_buff1~0=v_~z$w_buff1~0_6, Thread0_P1_#t~ite12=|v_Thread0_P1_#t~ite12_1|, Thread0_P1_#t~ite13=|v_Thread0_P1_#t~ite13_3|} AuxVars[] AssignedVars[Thread0_P1_#t~ite11, ~z$w_buff1~0, Thread0_P1_#t~ite12, Thread0_P1_#t~ite13] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [739] L745-->L745-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_7 256))) (= |v_Thread0_P1_#t~ite16_1| v_~z$w_buff0_used~0_17)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_17} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_17, Thread0_P1_#t~ite16=|v_Thread0_P1_#t~ite16_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite16] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [744] L745-8-->L746: Formula: (= v_~z$w_buff0_used~0_22 |v_Thread0_P1_#t~ite16_2|) InVars {Thread0_P1_#t~ite16=|v_Thread0_P1_#t~ite16_2|} OutVars{Thread0_P1_#t~ite14=|v_Thread0_P1_#t~ite14_1|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_22, Thread0_P1_#t~ite15=|v_Thread0_P1_#t~ite15_1|, Thread0_P1_#t~ite16=|v_Thread0_P1_#t~ite16_3|} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread0_P1_#t~ite14, Thread0_P1_#t~ite15, Thread0_P1_#t~ite16] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [748] L746-->L746-8: Formula: (and (= |v_Thread0_P1_#t~ite19_1| v_~z$w_buff1_used~0_11) (not (= (mod v_~weak$$choice2~0_9 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_11, ~weak$$choice2~0=v_~weak$$choice2~0_9} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_11, Thread0_P1_#t~ite19=|v_Thread0_P1_#t~ite19_1|, ~weak$$choice2~0=v_~weak$$choice2~0_9} AuxVars[] AssignedVars[Thread0_P1_#t~ite19] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite19|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [753] L746-8-->L747: Formula: (= v_~z$w_buff1_used~0_14 |v_Thread0_P1_#t~ite19_2|) InVars {Thread0_P1_#t~ite19=|v_Thread0_P1_#t~ite19_2|} OutVars{Thread0_P1_#t~ite18=|v_Thread0_P1_#t~ite18_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_14, Thread0_P1_#t~ite19=|v_Thread0_P1_#t~ite19_3|, Thread0_P1_#t~ite17=|v_Thread0_P1_#t~ite17_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite18, Thread0_P1_#t~ite19, ~z$w_buff1_used~0, Thread0_P1_#t~ite17] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [757] L747-->L747-8: Formula: (and (not (= (mod v_~weak$$choice2~0_11 256) 0)) (= |v_Thread0_P1_#t~ite22_1| v_~z$r_buff0_thd2~0_25)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_11, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} OutVars{Thread0_P1_#t~ite22=|v_Thread0_P1_#t~ite22_1|, ~weak$$choice2~0=v_~weak$$choice2~0_11, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} AuxVars[] AssignedVars[Thread0_P1_#t~ite22] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite22|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [762] L747-8-->L748: Formula: (= v_~z$r_buff0_thd2~0_30 |v_Thread0_P1_#t~ite22_2|) InVars {Thread0_P1_#t~ite22=|v_Thread0_P1_#t~ite22_2|} OutVars{Thread0_P1_#t~ite22=|v_Thread0_P1_#t~ite22_3|, Thread0_P1_#t~ite21=|v_Thread0_P1_#t~ite21_1|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_30, Thread0_P1_#t~ite20=|v_Thread0_P1_#t~ite20_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite20, Thread0_P1_#t~ite22, Thread0_P1_#t~ite21, ~z$r_buff0_thd2~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [766] L748-->L748-8: Formula: (and (not (= (mod v_~weak$$choice2~0_13 256) 0)) (= |v_Thread0_P1_#t~ite25_1| v_~z$r_buff1_thd2~0_16)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_13, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_16} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_13, Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_1|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_16} AuxVars[] AssignedVars[Thread0_P1_#t~ite25] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite25|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [771] L748-8-->L750: Formula: (and (= v_~__unbuffered_p1_EAX~0_1 v_~z~0_3) (= v_~z$r_buff1_thd2~0_5 |v_Thread0_P1_#t~ite25_2|)) InVars {Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_2|, ~z~0=v_~z~0_3} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_5, Thread0_P1_#t~ite24=|v_Thread0_P1_#t~ite24_1|, Thread0_P1_#t~ite23=|v_Thread0_P1_#t~ite23_1|, ~z~0=v_~z~0_3, Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_3|} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0, ~z$r_buff1_thd2~0, Thread0_P1_#t~ite24, Thread0_P1_#t~ite23, Thread0_P1_#t~ite25] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [775] L750-->L750-2: Formula: (and (not (= (mod v_~z$flush_delayed~0_2 256) 0)) (= |v_Thread0_P1_#t~ite26_1| v_~z$mem_tmp~0_2)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_2, ~z$flush_delayed~0=v_~z$flush_delayed~0_2} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_2, ~z$flush_delayed~0=v_~z$flush_delayed~0_2, Thread0_P1_#t~ite26=|v_Thread0_P1_#t~ite26_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite26] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite26|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite52|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [856] L794-5-->L795: Formula: (= v_~z~0_14 |v_Thread1_P2_#t~ite52_2|) InVars {Thread1_P2_#t~ite52=|v_Thread1_P2_#t~ite52_2|} OutVars{~z~0=v_~z~0_14, Thread1_P2_#t~ite52=|v_Thread1_P2_#t~ite52_3|, Thread1_P2_#t~ite51=|v_Thread1_P2_#t~ite51_1|} AuxVars[] AssignedVars[Thread1_P2_#t~ite52, Thread1_P2_#t~ite51, ~z~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite26|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [859] L795-->L795-2: Formula: (and (not (= (mod v_~z$w_buff0_used~0_53 256) 0)) (not (= 0 (mod v_~z$r_buff0_thd3~0_25 256))) (= |v_Thread1_P2_#t~ite53_1| 0)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_53, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_25} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_25, Thread1_P2_#t~ite53=|v_Thread1_P2_#t~ite53_1|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_53} AuxVars[] AssignedVars[Thread1_P2_#t~ite53] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite26|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite53|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 [780] L750-2-->L758: Formula: (and (= v_~z~0_6 |v_Thread0_P1_#t~ite26_3|) (= v_~z$flush_delayed~0_4 0) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {Thread0_P1_#t~ite26=|v_Thread0_P1_#t~ite26_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, ~z$flush_delayed~0=v_~z$flush_delayed~0_4, ~z~0=v_~z~0_6, Thread0_P1_#t~ite26=|v_Thread0_P1_#t~ite26_4|} AuxVars[] AssignedVars[~__unbuffered_cnt~0, ~z$flush_delayed~0, ~z~0, Thread0_P1_#t~ite26] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite53|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [862] L795-2-->L796: Formula: (= v_~z$w_buff0_used~0_55 |v_Thread1_P2_#t~ite53_3|) InVars {Thread1_P2_#t~ite53=|v_Thread1_P2_#t~ite53_3|} OutVars{Thread1_P2_#t~ite53=|v_Thread1_P2_#t~ite53_4|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_55} AuxVars[] AssignedVars[Thread1_P2_#t~ite53, ~z$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [864] L796-->L796-2: Formula: (and (= |v_Thread1_P2_#t~ite54_2| v_~z$w_buff1_used~0_32) (or (= 0 (mod v_~z$w_buff1_used~0_32 256)) (= 0 (mod v_~z$r_buff1_thd3~0_17 256))) (or (= (mod v_~z$w_buff0_used~0_59 256) 0) (= (mod v_~z$r_buff0_thd3~0_30 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_32, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_30, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_59, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_17} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_32, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_30, Thread1_P2_#t~ite54=|v_Thread1_P2_#t~ite54_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_59, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_17} AuxVars[] AssignedVars[Thread1_P2_#t~ite54] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite54|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [865] L796-2-->L797: Formula: (= v_~z$w_buff1_used~0_33 |v_Thread1_P2_#t~ite54_3|) InVars {Thread1_P2_#t~ite54=|v_Thread1_P2_#t~ite54_3|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_33, Thread1_P2_#t~ite54=|v_Thread1_P2_#t~ite54_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread1_P2_#t~ite54] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [867] L797-->L797-2: Formula: (and (or (= (mod v_~z$r_buff0_thd3~0_34 256) 0) (= 0 (mod v_~z$w_buff0_used~0_63 256))) (= |v_Thread1_P2_#t~ite55_2| v_~z$r_buff0_thd3~0_34)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_63, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_34} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_34, Thread1_P2_#t~ite55=|v_Thread1_P2_#t~ite55_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_63} AuxVars[] AssignedVars[Thread1_P2_#t~ite55] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite55|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [868] L797-2-->L798: Formula: (= v_~z$r_buff0_thd3~0_35 |v_Thread1_P2_#t~ite55_3|) InVars {Thread1_P2_#t~ite55=|v_Thread1_P2_#t~ite55_3|} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_35, Thread1_P2_#t~ite55=|v_Thread1_P2_#t~ite55_4|} AuxVars[] AssignedVars[~z$r_buff0_thd3~0, Thread1_P2_#t~ite55] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [870] L798-->L798-2: Formula: (and (or (= (mod v_~z$w_buff1_used~0_35 256) 0) (= 0 (mod v_~z$r_buff1_thd3~0_19 256))) (= |v_Thread1_P2_#t~ite56_2| v_~z$r_buff1_thd3~0_19) (or (= (mod v_~z$r_buff0_thd3~0_37 256) 0) (= (mod v_~z$w_buff0_used~0_66 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_35, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_37, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_66, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_19} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_35, Thread1_P2_#t~ite56=|v_Thread1_P2_#t~ite56_2|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_37, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_66, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_19} AuxVars[] AssignedVars[Thread1_P2_#t~ite56] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite56|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [871] L798-2-->L803: Formula: (and (= v_~z$r_buff1_thd3~0_20 |v_Thread1_P2_#t~ite56_3|) (= v_~__unbuffered_cnt~0_5 (+ v_~__unbuffered_cnt~0_6 1))) InVars {Thread1_P2_#t~ite56=|v_Thread1_P2_#t~ite56_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} OutVars{Thread1_P2_#t~ite56=|v_Thread1_P2_#t~ite56_4|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_20} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, Thread1_P2_#t~ite56, ~__unbuffered_cnt~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [561] L821-1-->L825: Formula: (= v_~main$tmp_guard0~0_1 (ite (= (ite (= v_~__unbuffered_cnt~0_7 3) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_7} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_7, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_1, ULTIMATE.start_main_#t~nondet60=|v_ULTIMATE.start_main_#t~nondet60_2|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet60] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [693] L825-->L827: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_2 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [547] L827-->L827-2: Formula: (or (= 0 (mod v_~z$w_buff0_used~0_76 256)) (= (mod v_~z$r_buff0_thd0~0_3 256) 0)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_76, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_3} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_76, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [513] L827-2-->L827-4: Formula: (and (= |v_ULTIMATE.start_main_#t~ite61_3| v_~z~0_15) (or (= (mod v_~z$w_buff1_used~0_43 256) 0) (= (mod v_~z$r_buff1_thd0~0_3 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_43, ~z~0=v_~z~0_15, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_3} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_43, ULTIMATE.start_main_#t~ite61=|v_ULTIMATE.start_main_#t~ite61_3|, ~z~0=v_~z~0_15, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite61] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite61|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [525] L827-4-->L827-5: Formula: (= |v_ULTIMATE.start_main_#t~ite62_3| |v_ULTIMATE.start_main_#t~ite61_4|) InVars {ULTIMATE.start_main_#t~ite61=|v_ULTIMATE.start_main_#t~ite61_4|} OutVars{ULTIMATE.start_main_#t~ite62=|v_ULTIMATE.start_main_#t~ite62_3|, ULTIMATE.start_main_#t~ite61=|v_ULTIMATE.start_main_#t~ite61_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite62] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite61|=0, |ULTIMATE.start_main_#t~ite62|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [529] L827-5-->L828: Formula: (= v_~z~0_16 |v_ULTIMATE.start_main_#t~ite62_5|) InVars {ULTIMATE.start_main_#t~ite62=|v_ULTIMATE.start_main_#t~ite62_5|} OutVars{ULTIMATE.start_main_#t~ite62=|v_ULTIMATE.start_main_#t~ite62_4|, ULTIMATE.start_main_#t~ite61=|v_ULTIMATE.start_main_#t~ite61_5|, ~z~0=v_~z~0_16} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite62, ULTIMATE.start_main_#t~ite61, ~z~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [680] L828-->L828-2: Formula: (and (or (= (mod v_~z$r_buff0_thd0~0_5 256) 0) (= 0 (mod v_~z$w_buff0_used~0_78 256))) (= |v_ULTIMATE.start_main_#t~ite63_3| v_~z$w_buff0_used~0_78)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_78, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_5} OutVars{ULTIMATE.start_main_#t~ite63=|v_ULTIMATE.start_main_#t~ite63_3|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_5, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_78} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite63] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite63|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [689] L828-2-->L829: Formula: (= v_~z$w_buff0_used~0_79 |v_ULTIMATE.start_main_#t~ite63_5|) InVars {ULTIMATE.start_main_#t~ite63=|v_ULTIMATE.start_main_#t~ite63_5|} OutVars{ULTIMATE.start_main_#t~ite63=|v_ULTIMATE.start_main_#t~ite63_4|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_79} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite63, ~z$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [591] L829-->L829-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite64_3| v_~z$w_buff1_used~0_45) (or (= (mod v_~z$r_buff1_thd0~0_5 256) 0) (= 0 (mod v_~z$w_buff1_used~0_45 256))) (or (= 0 (mod v_~z$r_buff0_thd0~0_7 256)) (= (mod v_~z$w_buff0_used~0_81 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_45, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_81, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_5} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_45, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_81, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_5, ULTIMATE.start_main_#t~ite64=|v_ULTIMATE.start_main_#t~ite64_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite64] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite64|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [598] L829-2-->L830: Formula: (= v_~z$w_buff1_used~0_46 |v_ULTIMATE.start_main_#t~ite64_5|) InVars {ULTIMATE.start_main_#t~ite64=|v_ULTIMATE.start_main_#t~ite64_5|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_46, ULTIMATE.start_main_#t~ite64=|v_ULTIMATE.start_main_#t~ite64_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite64] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [490] L830-->L830-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd0~0_9 256)) (= 0 (mod v_~z$w_buff0_used~0_83 256))) (= |v_ULTIMATE.start_main_#t~ite65_3| v_~z$r_buff0_thd0~0_9)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_83, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_9} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_83, ULTIMATE.start_main_#t~ite65=|v_ULTIMATE.start_main_#t~ite65_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite65] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite65|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [496] L830-2-->L831: Formula: (= v_~z$r_buff0_thd0~0_10 |v_ULTIMATE.start_main_#t~ite65_5|) InVars {ULTIMATE.start_main_#t~ite65=|v_ULTIMATE.start_main_#t~ite65_5|} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_10, ULTIMATE.start_main_#t~ite65=|v_ULTIMATE.start_main_#t~ite65_4|} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite65] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [674] L831-->L831-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite66_3| v_~z$r_buff1_thd0~0_7) (or (= (mod v_~z$r_buff1_thd0~0_7 256) 0) (= (mod v_~z$w_buff1_used~0_48 256) 0)) (or (= 0 (mod v_~z$w_buff0_used~0_85 256)) (= (mod v_~z$r_buff0_thd0~0_12 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_48, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_12, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_85, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_7} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_48, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_12, ULTIMATE.start_main_#t~ite66=|v_ULTIMATE.start_main_#t~ite66_3|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_85, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite66] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite66|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [650] L831-2-->L836: Formula: (and (= v_~z$r_buff1_thd0~0_8 |v_ULTIMATE.start_main_#t~ite66_5|) (= v_~main$tmp_guard1~0_1 (ite (= (ite (not (and (= v_~__unbuffered_p2_EBX~0_2 0) (= 0 v_~__unbuffered_p1_EAX~0_2) (= v_~__unbuffered_p0_EBX~0_2 0) (= v_~__unbuffered_p0_EAX~0_2 1) (= v_~__unbuffered_p2_EAX~0_2 1))) 1 0) 0) 0 1))) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_2, ULTIMATE.start_main_#t~ite66=|v_ULTIMATE.start_main_#t~ite66_5|} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_8, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_1, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_2, ULTIMATE.start_main_#t~ite66=|v_ULTIMATE.start_main_#t~ite66_4|} AuxVars[] AssignedVars[~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite66] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [690] L836-->L836-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_2 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [694] L836-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [555] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [549] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [544] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58, main_#t~nondet59, main_#t~nondet60, main_#t~ite62, main_#t~ite61, main_#t~ite63, main_#t~ite64, main_#t~ite65, main_#t~ite66, main_~#t408~0.base, main_~#t408~0.offset, main_~#t409~0.base, main_~#t409~0.offset, main_~#t410~0.base, main_~#t410~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t408~0.base, main_~#t408~0.offset := #Ultimate.alloc(4); srcloc: L816 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t408~0.base, main_~#t408~0.offset, 4); srcloc: L816-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t409~0.base, main_~#t409~0.offset := #Ultimate.alloc(4); srcloc: L818 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t409~0.base, main_~#t409~0.offset, 4); srcloc: L818-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet59; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t410~0.base, main_~#t410~0.offset := #Ultimate.alloc(4); srcloc: L820 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(2, main_~#t410~0.base, main_~#t410~0.offset, 4); srcloc: L820-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 2 P2(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0;~z$r_buff0_thd3~0 := 1;~weak$$choice0~0 := (if 0 == #t~nondet28.base + #t~nondet28.offset then 0 else 1);havoc #t~nondet28.base, #t~nondet28.offset;~weak$$choice2~0 := (if 0 == #t~nondet29.base + #t~nondet29.offset then 0 else 1);havoc #t~nondet29.base, #t~nondet29.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite30 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 #t~ite31 := #t~ite30; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=1, |P2_#t~ite31|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite31;havoc #t~ite31;havoc #t~ite30; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite34 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite34|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0~0 := #t~ite34;havoc #t~ite32;havoc #t~ite34;havoc #t~ite33; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite37 := ~z$w_buff1~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite37|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1~0 := #t~ite37;havoc #t~ite35;havoc #t~ite36;havoc #t~ite37; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite40 := ~z$w_buff0_used~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite40|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite40;havoc #t~ite40;havoc #t~ite38;havoc #t~ite39; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite43 := ~z$w_buff1_used~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite43|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite43;havoc #t~ite43;havoc #t~ite41;havoc #t~ite42; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite46 := ~z$r_buff0_thd3~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite46|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd3~0 := #t~ite46;havoc #t~ite46;havoc #t~ite45;havoc #t~ite44; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite49 := ~z$r_buff1_thd3~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite49|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd3~0 := #t~ite49;havoc #t~ite48;havoc #t~ite47;havoc #t~ite49;~__unbuffered_p2_EAX~0 := ~z~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$flush_delayed~0 % 256;#t~ite50 := ~z$mem_tmp~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite50|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z~0 := #t~ite50;havoc #t~ite50;~z$flush_delayed~0 := 0;~__unbuffered_p2_EBX~0 := ~a~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite52 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~a~0 := 1;~x~0 := 1;~__unbuffered_p0_EAX~0 := ~x~0;~__unbuffered_p0_EBX~0 := ~y~0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 1;~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1);havoc #t~nondet4.base, #t~nondet4.offset;~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1);havoc #t~nondet5.base, #t~nondet5.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite7 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z~0 := #t~ite7;havoc #t~ite6;havoc #t~ite7; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite10 := ~z$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite10|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0~0 := #t~ite10;havoc #t~ite8;havoc #t~ite10;havoc #t~ite9; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite13 := ~z$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1~0 := #t~ite13;havoc #t~ite11;havoc #t~ite13;havoc #t~ite12; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0_used~0 := #t~ite16;havoc #t~ite15;havoc #t~ite16;havoc #t~ite14; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1_used~0 := #t~ite19;havoc #t~ite19;havoc #t~ite18;havoc #t~ite17; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff0_thd2~0 := #t~ite22;havoc #t~ite20;havoc #t~ite21;havoc #t~ite22; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff1_thd2~0 := #t~ite25;havoc #t~ite25;havoc #t~ite23;havoc #t~ite24;~__unbuffered_p1_EAX~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~z$flush_delayed~0 % 256;#t~ite26 := ~z$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite52;havoc #t~ite51;havoc #t~ite52; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite53 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite53|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 ~z~0 := #t~ite26;havoc #t~ite26;~z$flush_delayed~0 := 0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite53|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$w_buff0_used~0 := #t~ite53;havoc #t~ite53; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite54 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite54|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$w_buff1_used~0 := #t~ite54;havoc #t~ite54; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256);#t~ite55 := ~z$r_buff0_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite55|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff0_thd3~0 := #t~ite55;havoc #t~ite55; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite56 := ~z$r_buff1_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite56|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd3~0 := #t~ite56;havoc #t~ite56;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet60;~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite61 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite61|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite62 := main_#t~ite61; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite61|=0, |ULTIMATE.start_main_#t~ite62|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite62;havoc main_#t~ite62;havoc main_#t~ite61; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite63 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite63|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite63;havoc main_#t~ite63; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite64 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite64|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite64;havoc main_#t~ite64; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite65 := ~z$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite65|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite65;havoc main_#t~ite65; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite66 := ~z$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite66|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite66;havoc main_#t~ite66;~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58, main_#t~nondet59, main_#t~nondet60, main_#t~ite62, main_#t~ite61, main_#t~ite63, main_#t~ite64, main_#t~ite65, main_#t~ite66, main_~#t408~0.base, main_~#t408~0.offset, main_~#t409~0.base, main_~#t409~0.offset, main_~#t410~0.base, main_~#t410~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t408~0.base, main_~#t408~0.offset := #Ultimate.alloc(4); srcloc: L816 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t408~0.base, main_~#t408~0.offset, 4); srcloc: L816-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t409~0.base, main_~#t409~0.offset := #Ultimate.alloc(4); srcloc: L818 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t409~0.base, main_~#t409~0.offset, 4); srcloc: L818-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet59; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t410~0.base, main_~#t410~0.offset := #Ultimate.alloc(4); srcloc: L820 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(2, main_~#t410~0.base, main_~#t410~0.offset, 4); srcloc: L820-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 2 P2(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0;~z$r_buff0_thd3~0 := 1;~weak$$choice0~0 := (if 0 == #t~nondet28.base + #t~nondet28.offset then 0 else 1);havoc #t~nondet28.base, #t~nondet28.offset;~weak$$choice2~0 := (if 0 == #t~nondet29.base + #t~nondet29.offset then 0 else 1);havoc #t~nondet29.base, #t~nondet29.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite30 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 #t~ite31 := #t~ite30; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=1, |P2_#t~ite31|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite31;havoc #t~ite31;havoc #t~ite30; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite34 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite34|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0~0 := #t~ite34;havoc #t~ite32;havoc #t~ite34;havoc #t~ite33; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite37 := ~z$w_buff1~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite37|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1~0 := #t~ite37;havoc #t~ite35;havoc #t~ite36;havoc #t~ite37; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite40 := ~z$w_buff0_used~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite40|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite40;havoc #t~ite40;havoc #t~ite38;havoc #t~ite39; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite43 := ~z$w_buff1_used~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite43|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite43;havoc #t~ite43;havoc #t~ite41;havoc #t~ite42; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite46 := ~z$r_buff0_thd3~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite46|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd3~0 := #t~ite46;havoc #t~ite46;havoc #t~ite45;havoc #t~ite44; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite49 := ~z$r_buff1_thd3~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite49|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd3~0 := #t~ite49;havoc #t~ite48;havoc #t~ite47;havoc #t~ite49;~__unbuffered_p2_EAX~0 := ~z~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$flush_delayed~0 % 256;#t~ite50 := ~z$mem_tmp~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite50|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z~0 := #t~ite50;havoc #t~ite50;~z$flush_delayed~0 := 0;~__unbuffered_p2_EBX~0 := ~a~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite52 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~a~0 := 1;~x~0 := 1;~__unbuffered_p0_EAX~0 := ~x~0;~__unbuffered_p0_EBX~0 := ~y~0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 1;~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1);havoc #t~nondet4.base, #t~nondet4.offset;~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1);havoc #t~nondet5.base, #t~nondet5.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite7 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z~0 := #t~ite7;havoc #t~ite6;havoc #t~ite7; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite10 := ~z$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite10|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0~0 := #t~ite10;havoc #t~ite8;havoc #t~ite10;havoc #t~ite9; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite13 := ~z$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1~0 := #t~ite13;havoc #t~ite11;havoc #t~ite13;havoc #t~ite12; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0_used~0 := #t~ite16;havoc #t~ite15;havoc #t~ite16;havoc #t~ite14; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1_used~0 := #t~ite19;havoc #t~ite19;havoc #t~ite18;havoc #t~ite17; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff0_thd2~0 := #t~ite22;havoc #t~ite20;havoc #t~ite21;havoc #t~ite22; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff1_thd2~0 := #t~ite25;havoc #t~ite25;havoc #t~ite23;havoc #t~ite24;~__unbuffered_p1_EAX~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~z$flush_delayed~0 % 256;#t~ite26 := ~z$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite52;havoc #t~ite51;havoc #t~ite52; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite53 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite53|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 ~z~0 := #t~ite26;havoc #t~ite26;~z$flush_delayed~0 := 0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite53|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$w_buff0_used~0 := #t~ite53;havoc #t~ite53; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite54 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite54|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$w_buff1_used~0 := #t~ite54;havoc #t~ite54; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256);#t~ite55 := ~z$r_buff0_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite55|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff0_thd3~0 := #t~ite55;havoc #t~ite55; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite56 := ~z$r_buff1_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite56|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd3~0 := #t~ite56;havoc #t~ite56;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet60;~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite61 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite61|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite62 := main_#t~ite61; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite61|=0, |ULTIMATE.start_main_#t~ite62|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite62;havoc main_#t~ite62;havoc main_#t~ite61; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite63 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite63|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite63;havoc main_#t~ite63; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite64 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite64|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite64;havoc main_#t~ite64; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite65 := ~z$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite65|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite65;havoc main_#t~ite65; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite66 := ~z$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite66|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite66;havoc main_#t~ite66;~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L676] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L678] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [L682] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L684] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58, main_#t~nondet59, main_#t~nondet60, main_#t~ite62, main_#t~ite61, main_#t~ite63, main_#t~ite64, main_#t~ite65, main_#t~ite66, main_~#t408~0.base, main_~#t408~0.offset, main_~#t409~0.base, main_~#t409~0.offset, main_~#t410~0.base, main_~#t410~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L816] -1 call main_~#t408~0.base, main_~#t408~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 call write~int(0, main_~#t408~0.base, main_~#t408~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 havoc main_#t~nondet58; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 call main_~#t409~0.base, main_~#t409~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 call write~int(1, main_~#t409~0.base, main_~#t409~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 havoc main_#t~nondet59; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 call main_~#t410~0.base, main_~#t410~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 call write~int(2, main_~#t410~0.base, main_~#t410~0.offset, 4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FORK -1 fork 2 P2(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L804] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~weak$$choice0~0 := (if 0 == #t~nondet28.base + #t~nondet28.offset then 0 else 1); [L775] 0 havoc #t~nondet28.base, #t~nondet28.offset; [L776] 0 ~weak$$choice2~0 := (if 0 == #t~nondet29.base + #t~nondet29.offset then 0 else 1); [L776] 0 havoc #t~nondet29.base, #t~nondet29.offset; [L777] 0 ~z$flush_delayed~0 := ~weak$$choice2~0; [L778] 0 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 assume !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L779] 0 #t~ite30 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 #t~ite31 := #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=1, #t~ite31=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 ~z~0 := #t~ite31; [L779] 0 havoc #t~ite31; [L779] 0 havoc #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 assume 0 != ~weak$$choice2~0 % 256; [L780] 0 #t~ite34 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite34=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 ~z$w_buff0~0 := #t~ite34; [L780] 0 havoc #t~ite32; [L780] 0 havoc #t~ite34; [L780] 0 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 assume 0 != ~weak$$choice2~0 % 256; [L781] 0 #t~ite37 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 ~z$w_buff1~0 := #t~ite37; [L781] 0 havoc #t~ite35; [L781] 0 havoc #t~ite36; [L781] 0 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 assume 0 != ~weak$$choice2~0 % 256; [L782] 0 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite40=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 ~z$w_buff0_used~0 := #t~ite40; [L782] 0 havoc #t~ite40; [L782] 0 havoc #t~ite38; [L782] 0 havoc #t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 assume 0 != ~weak$$choice2~0 % 256; [L783] 0 #t~ite43 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite43=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 ~z$w_buff1_used~0 := #t~ite43; [L783] 0 havoc #t~ite43; [L783] 0 havoc #t~ite41; [L783] 0 havoc #t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 assume 0 != ~weak$$choice2~0 % 256; [L784] 0 #t~ite46 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite46=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 ~z$r_buff0_thd3~0 := #t~ite46; [L784] 0 havoc #t~ite46; [L784] 0 havoc #t~ite45; [L784] 0 havoc #t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 assume 0 != ~weak$$choice2~0 % 256; [L785] 0 #t~ite49 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite49=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$r_buff1_thd3~0 := #t~ite49; [L785] 0 havoc #t~ite48; [L785] 0 havoc #t~ite47; [L785] 0 havoc #t~ite49; [L786] 0 ~__unbuffered_p2_EAX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 assume 0 != ~z$flush_delayed~0 % 256; [L787] 0 #t~ite50 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite50=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z~0 := #t~ite50; [L787] 0 havoc #t~ite50; [L788] 0 ~z$flush_delayed~0 := 0; [L791] 0 ~__unbuffered_p2_EBX~0 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L794] 0 #t~ite52 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L731] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L714] 1 ~a~0 := 1; [L717] 1 ~x~0 := 1; [L720] 1 ~__unbuffered_p0_EAX~0 := ~x~0; [L723] 1 ~__unbuffered_p0_EBX~0 := ~y~0; [L728] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L732-L759] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L735] 2 ~y~0 := 1; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1); [L738] 2 havoc #t~nondet4.base, #t~nondet4.offset; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1); [L739] 2 havoc #t~nondet5.base, #t~nondet5.offset; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite6; [L742] 2 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 assume 0 != ~weak$$choice2~0 % 256; [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite10=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite8; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite9; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 assume 0 != ~weak$$choice2~0 % 256; [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite11; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 assume 0 != ~weak$$choice2~0 % 256; [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; [L745] 2 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 assume 0 != ~weak$$choice2~0 % 256; [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 assume 0 != ~weak$$choice2~0 % 256; [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite20; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 assume 0 != ~weak$$choice2~0 % 256; [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L748] 2 havoc #t~ite24; [L749] 2 ~__unbuffered_p1_EAX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 assume 0 != ~z$flush_delayed~0 % 256; [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 ~z~0 := #t~ite52; [L794] 0 havoc #t~ite51; [L794] 0 havoc #t~ite52; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L795] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L795] 0 #t~ite53 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L795] 0 ~z$w_buff0_used~0 := #t~ite53; [L795] 0 havoc #t~ite53; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L796] 0 #t~ite54 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite54=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 ~z$w_buff1_used~0 := #t~ite54; [L796] 0 havoc #t~ite54; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256); [L797] 0 #t~ite55 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite55=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 ~z$r_buff0_thd3~0 := #t~ite55; [L797] 0 havoc #t~ite55; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L798] 0 #t~ite56 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite56=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 ~z$r_buff1_thd3~0 := #t~ite56; [L798] 0 havoc #t~ite56; [L801] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 havoc main_#t~nondet60; [L823] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L825] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L827] -1 main_#t~ite61 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 main_#t~ite62 := main_#t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_#t~ite62=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 ~z~0 := main_#t~ite62; [L827] -1 havoc main_#t~ite62; [L827] -1 havoc main_#t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L828] -1 main_#t~ite63 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite63=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 ~z$w_buff0_used~0 := main_#t~ite63; [L828] -1 havoc main_#t~ite63; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L829] -1 main_#t~ite64 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite64=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 ~z$w_buff1_used~0 := main_#t~ite64; [L829] -1 havoc main_#t~ite64; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L830] -1 main_#t~ite65 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite65=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 ~z$r_buff0_thd0~0 := main_#t~ite65; [L830] -1 havoc main_#t~ite65; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L831] -1 main_#t~ite66 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite66=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 ~z$r_buff1_thd0~0 := main_#t~ite66; [L831] -1 havoc main_#t~ite66; [L834] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L676] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L678] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [L682] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L684] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58, main_#t~nondet59, main_#t~nondet60, main_#t~ite62, main_#t~ite61, main_#t~ite63, main_#t~ite64, main_#t~ite65, main_#t~ite66, main_~#t408~0.base, main_~#t408~0.offset, main_~#t409~0.base, main_~#t409~0.offset, main_~#t410~0.base, main_~#t410~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L816] -1 call main_~#t408~0.base, main_~#t408~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 call write~int(0, main_~#t408~0.base, main_~#t408~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 havoc main_#t~nondet58; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 call main_~#t409~0.base, main_~#t409~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 call write~int(1, main_~#t409~0.base, main_~#t409~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 havoc main_#t~nondet59; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 call main_~#t410~0.base, main_~#t410~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 call write~int(2, main_~#t410~0.base, main_~#t410~0.offset, 4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FORK -1 fork 2 P2(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L804] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~weak$$choice0~0 := (if 0 == #t~nondet28.base + #t~nondet28.offset then 0 else 1); [L775] 0 havoc #t~nondet28.base, #t~nondet28.offset; [L776] 0 ~weak$$choice2~0 := (if 0 == #t~nondet29.base + #t~nondet29.offset then 0 else 1); [L776] 0 havoc #t~nondet29.base, #t~nondet29.offset; [L777] 0 ~z$flush_delayed~0 := ~weak$$choice2~0; [L778] 0 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 assume !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L779] 0 #t~ite30 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 #t~ite31 := #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=1, #t~ite31=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 ~z~0 := #t~ite31; [L779] 0 havoc #t~ite31; [L779] 0 havoc #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 assume 0 != ~weak$$choice2~0 % 256; [L780] 0 #t~ite34 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite34=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 ~z$w_buff0~0 := #t~ite34; [L780] 0 havoc #t~ite32; [L780] 0 havoc #t~ite34; [L780] 0 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 assume 0 != ~weak$$choice2~0 % 256; [L781] 0 #t~ite37 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 ~z$w_buff1~0 := #t~ite37; [L781] 0 havoc #t~ite35; [L781] 0 havoc #t~ite36; [L781] 0 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 assume 0 != ~weak$$choice2~0 % 256; [L782] 0 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite40=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 ~z$w_buff0_used~0 := #t~ite40; [L782] 0 havoc #t~ite40; [L782] 0 havoc #t~ite38; [L782] 0 havoc #t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 assume 0 != ~weak$$choice2~0 % 256; [L783] 0 #t~ite43 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite43=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 ~z$w_buff1_used~0 := #t~ite43; [L783] 0 havoc #t~ite43; [L783] 0 havoc #t~ite41; [L783] 0 havoc #t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 assume 0 != ~weak$$choice2~0 % 256; [L784] 0 #t~ite46 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite46=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 ~z$r_buff0_thd3~0 := #t~ite46; [L784] 0 havoc #t~ite46; [L784] 0 havoc #t~ite45; [L784] 0 havoc #t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 assume 0 != ~weak$$choice2~0 % 256; [L785] 0 #t~ite49 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite49=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$r_buff1_thd3~0 := #t~ite49; [L785] 0 havoc #t~ite48; [L785] 0 havoc #t~ite47; [L785] 0 havoc #t~ite49; [L786] 0 ~__unbuffered_p2_EAX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 assume 0 != ~z$flush_delayed~0 % 256; [L787] 0 #t~ite50 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite50=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z~0 := #t~ite50; [L787] 0 havoc #t~ite50; [L788] 0 ~z$flush_delayed~0 := 0; [L791] 0 ~__unbuffered_p2_EBX~0 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L794] 0 #t~ite52 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L731] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L714] 1 ~a~0 := 1; [L717] 1 ~x~0 := 1; [L720] 1 ~__unbuffered_p0_EAX~0 := ~x~0; [L723] 1 ~__unbuffered_p0_EBX~0 := ~y~0; [L728] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L732-L759] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L735] 2 ~y~0 := 1; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1); [L738] 2 havoc #t~nondet4.base, #t~nondet4.offset; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1); [L739] 2 havoc #t~nondet5.base, #t~nondet5.offset; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite6; [L742] 2 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 assume 0 != ~weak$$choice2~0 % 256; [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite10=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite8; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite9; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 assume 0 != ~weak$$choice2~0 % 256; [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite11; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 assume 0 != ~weak$$choice2~0 % 256; [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; [L745] 2 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 assume 0 != ~weak$$choice2~0 % 256; [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 assume 0 != ~weak$$choice2~0 % 256; [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite20; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 assume 0 != ~weak$$choice2~0 % 256; [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L748] 2 havoc #t~ite24; [L749] 2 ~__unbuffered_p1_EAX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 assume 0 != ~z$flush_delayed~0 % 256; [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 ~z~0 := #t~ite52; [L794] 0 havoc #t~ite51; [L794] 0 havoc #t~ite52; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L795] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L795] 0 #t~ite53 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L795] 0 ~z$w_buff0_used~0 := #t~ite53; [L795] 0 havoc #t~ite53; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L796] 0 #t~ite54 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite54=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 ~z$w_buff1_used~0 := #t~ite54; [L796] 0 havoc #t~ite54; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256); [L797] 0 #t~ite55 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite55=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 ~z$r_buff0_thd3~0 := #t~ite55; [L797] 0 havoc #t~ite55; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L798] 0 #t~ite56 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite56=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 ~z$r_buff1_thd3~0 := #t~ite56; [L798] 0 havoc #t~ite56; [L801] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 havoc main_#t~nondet60; [L823] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L825] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L827] -1 main_#t~ite61 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 main_#t~ite62 := main_#t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_#t~ite62=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 ~z~0 := main_#t~ite62; [L827] -1 havoc main_#t~ite62; [L827] -1 havoc main_#t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L828] -1 main_#t~ite63 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite63=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 ~z$w_buff0_used~0 := main_#t~ite63; [L828] -1 havoc main_#t~ite63; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L829] -1 main_#t~ite64 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite64=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 ~z$w_buff1_used~0 := main_#t~ite64; [L829] -1 havoc main_#t~ite64; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L830] -1 main_#t~ite65 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite65=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 ~z$r_buff0_thd0~0 := main_#t~ite65; [L830] -1 havoc main_#t~ite65; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L831] -1 main_#t~ite66 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite66=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 ~z$r_buff1_thd0~0 := main_#t~ite66; [L831] -1 havoc main_#t~ite66; [L834] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L676] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L678] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [L682] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L684] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58, main_#t~nondet59, main_#t~nondet60, main_#t~ite62, main_#t~ite61, main_#t~ite63, main_#t~ite64, main_#t~ite65, main_#t~ite66, main_~#t408~0, main_~#t409~0, main_~#t410~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L816] FCALL -1 call main_~#t408~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FCALL -1 call write~int(0, main_~#t408~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 havoc main_#t~nondet58; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] FCALL -1 call main_~#t409~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FCALL -1 call write~int(1, main_~#t409~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 havoc main_#t~nondet59; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] FCALL -1 call main_~#t410~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FCALL -1 call write~int(2, main_~#t410~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L804] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~weak$$choice0~0 := (if 0 == #t~nondet28!base + #t~nondet28!offset then 0 else 1); [L775] 0 havoc #t~nondet28; [L776] 0 ~weak$$choice2~0 := (if 0 == #t~nondet29!base + #t~nondet29!offset then 0 else 1); [L776] 0 havoc #t~nondet29; [L777] 0 ~z$flush_delayed~0 := ~weak$$choice2~0; [L778] 0 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] COND FALSE 0 !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L779] 0 #t~ite30 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 #t~ite31 := #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=1, #t~ite31=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 ~z~0 := #t~ite31; [L779] 0 havoc #t~ite31; [L779] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L780] 0 #t~ite34 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite34=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 ~z$w_buff0~0 := #t~ite34; [L780] 0 havoc #t~ite32; [L780] 0 havoc #t~ite34; [L780] 0 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L781] 0 #t~ite37 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 ~z$w_buff1~0 := #t~ite37; [L781] 0 havoc #t~ite35; [L781] 0 havoc #t~ite36; [L781] 0 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L782] 0 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite40=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 ~z$w_buff0_used~0 := #t~ite40; [L782] 0 havoc #t~ite40; [L782] 0 havoc #t~ite38; [L782] 0 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L783] 0 #t~ite43 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite43=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 ~z$w_buff1_used~0 := #t~ite43; [L783] 0 havoc #t~ite43; [L783] 0 havoc #t~ite41; [L783] 0 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L784] 0 #t~ite46 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite46=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 ~z$r_buff0_thd3~0 := #t~ite46; [L784] 0 havoc #t~ite46; [L784] 0 havoc #t~ite45; [L784] 0 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L785] 0 #t~ite49 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite49=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$r_buff1_thd3~0 := #t~ite49; [L785] 0 havoc #t~ite48; [L785] 0 havoc #t~ite47; [L785] 0 havoc #t~ite49; [L786] 0 ~__unbuffered_p2_EAX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND TRUE 0 0 != ~z$flush_delayed~0 % 256 [L787] 0 #t~ite50 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite50=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z~0 := #t~ite50; [L787] 0 havoc #t~ite50; [L788] 0 ~z$flush_delayed~0 := 0; [L791] 0 ~__unbuffered_p2_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L794] 0 #t~ite52 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L731] 1 ~arg := #in~arg; [L714] 1 ~a~0 := 1; [L717] 1 ~x~0 := 1; [L720] 1 ~__unbuffered_p0_EAX~0 := ~x~0; [L723] 1 ~__unbuffered_p0_EBX~0 := ~y~0; [L728] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L732-L759] 2 ~arg := #in~arg; [L735] 2 ~y~0 := 1; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite6; [L742] 2 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite8; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite9; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite11; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; [L745] 2 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite20; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L748] 2 havoc #t~ite24; [L749] 2 ~__unbuffered_p1_EAX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 ~z~0 := #t~ite52; [L794] 0 havoc #t~ite51; [L794] 0 havoc #t~ite52; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L795] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L795] 0 #t~ite53 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L795] 0 ~z$w_buff0_used~0 := #t~ite53; [L795] 0 havoc #t~ite53; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L796] 0 #t~ite54 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite54=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 ~z$w_buff1_used~0 := #t~ite54; [L796] 0 havoc #t~ite54; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L797] 0 #t~ite55 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite55=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 ~z$r_buff0_thd3~0 := #t~ite55; [L797] 0 havoc #t~ite55; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L798] 0 #t~ite56 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite56=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 ~z$r_buff1_thd3~0 := #t~ite56; [L798] 0 havoc #t~ite56; [L801] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 havoc main_#t~nondet60; [L823] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L825] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L827] -1 main_#t~ite61 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 main_#t~ite62 := main_#t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_#t~ite62=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 ~z~0 := main_#t~ite62; [L827] -1 havoc main_#t~ite62; [L827] -1 havoc main_#t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L828] -1 main_#t~ite63 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite63=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 ~z$w_buff0_used~0 := main_#t~ite63; [L828] -1 havoc main_#t~ite63; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L829] -1 main_#t~ite64 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite64=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 ~z$w_buff1_used~0 := main_#t~ite64; [L829] -1 havoc main_#t~ite64; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L830] -1 main_#t~ite65 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite65=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 ~z$r_buff0_thd0~0 := main_#t~ite65; [L830] -1 havoc main_#t~ite65; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L831] -1 main_#t~ite66 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite66=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 ~z$r_buff1_thd0~0 := main_#t~ite66; [L831] -1 havoc main_#t~ite66; [L834] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L676] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L678] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [L682] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L684] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58, main_#t~nondet59, main_#t~nondet60, main_#t~ite62, main_#t~ite61, main_#t~ite63, main_#t~ite64, main_#t~ite65, main_#t~ite66, main_~#t408~0, main_~#t409~0, main_~#t410~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L816] FCALL -1 call main_~#t408~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FCALL -1 call write~int(0, main_~#t408~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 havoc main_#t~nondet58; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] FCALL -1 call main_~#t409~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FCALL -1 call write~int(1, main_~#t409~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 havoc main_#t~nondet59; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] FCALL -1 call main_~#t410~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FCALL -1 call write~int(2, main_~#t410~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L804] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~weak$$choice0~0 := (if 0 == #t~nondet28!base + #t~nondet28!offset then 0 else 1); [L775] 0 havoc #t~nondet28; [L776] 0 ~weak$$choice2~0 := (if 0 == #t~nondet29!base + #t~nondet29!offset then 0 else 1); [L776] 0 havoc #t~nondet29; [L777] 0 ~z$flush_delayed~0 := ~weak$$choice2~0; [L778] 0 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] COND FALSE 0 !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L779] 0 #t~ite30 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 #t~ite31 := #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=1, #t~ite31=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 ~z~0 := #t~ite31; [L779] 0 havoc #t~ite31; [L779] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L780] 0 #t~ite34 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite34=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 ~z$w_buff0~0 := #t~ite34; [L780] 0 havoc #t~ite32; [L780] 0 havoc #t~ite34; [L780] 0 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L781] 0 #t~ite37 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 ~z$w_buff1~0 := #t~ite37; [L781] 0 havoc #t~ite35; [L781] 0 havoc #t~ite36; [L781] 0 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L782] 0 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite40=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 ~z$w_buff0_used~0 := #t~ite40; [L782] 0 havoc #t~ite40; [L782] 0 havoc #t~ite38; [L782] 0 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L783] 0 #t~ite43 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite43=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 ~z$w_buff1_used~0 := #t~ite43; [L783] 0 havoc #t~ite43; [L783] 0 havoc #t~ite41; [L783] 0 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L784] 0 #t~ite46 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite46=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 ~z$r_buff0_thd3~0 := #t~ite46; [L784] 0 havoc #t~ite46; [L784] 0 havoc #t~ite45; [L784] 0 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L785] 0 #t~ite49 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite49=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$r_buff1_thd3~0 := #t~ite49; [L785] 0 havoc #t~ite48; [L785] 0 havoc #t~ite47; [L785] 0 havoc #t~ite49; [L786] 0 ~__unbuffered_p2_EAX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND TRUE 0 0 != ~z$flush_delayed~0 % 256 [L787] 0 #t~ite50 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite50=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z~0 := #t~ite50; [L787] 0 havoc #t~ite50; [L788] 0 ~z$flush_delayed~0 := 0; [L791] 0 ~__unbuffered_p2_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L794] 0 #t~ite52 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L731] 1 ~arg := #in~arg; [L714] 1 ~a~0 := 1; [L717] 1 ~x~0 := 1; [L720] 1 ~__unbuffered_p0_EAX~0 := ~x~0; [L723] 1 ~__unbuffered_p0_EBX~0 := ~y~0; [L728] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; WARNING: YOUR LOGFILE WAS TOO LONG, SOME LINES IN THE MIDDLE WERE REMOVED. [?] 0 [862] L795-2-->L796: Formula: (= v_~z$w_buff0_used~0_55 |v_Thread1_P2_#t~ite53_3|) InVars {Thread1_P2_#t~ite53=|v_Thread1_P2_#t~ite53_3|} OutVars{Thread1_P2_#t~ite53=|v_Thread1_P2_#t~ite53_4|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_55} AuxVars[] AssignedVars[Thread1_P2_#t~ite53, ~z$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [864] L796-->L796-2: Formula: (and (= |v_Thread1_P2_#t~ite54_2| v_~z$w_buff1_used~0_32) (or (= 0 (mod v_~z$w_buff1_used~0_32 256)) (= 0 (mod v_~z$r_buff1_thd3~0_17 256))) (or (= (mod v_~z$w_buff0_used~0_59 256) 0) (= (mod v_~z$r_buff0_thd3~0_30 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_32, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_30, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_59, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_17} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_32, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_30, Thread1_P2_#t~ite54=|v_Thread1_P2_#t~ite54_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_59, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_17} AuxVars[] AssignedVars[Thread1_P2_#t~ite54] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite54|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [865] L796-2-->L797: Formula: (= v_~z$w_buff1_used~0_33 |v_Thread1_P2_#t~ite54_3|) InVars {Thread1_P2_#t~ite54=|v_Thread1_P2_#t~ite54_3|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_33, Thread1_P2_#t~ite54=|v_Thread1_P2_#t~ite54_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread1_P2_#t~ite54] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [867] L797-->L797-2: Formula: (and (or (= (mod v_~z$r_buff0_thd3~0_34 256) 0) (= 0 (mod v_~z$w_buff0_used~0_63 256))) (= |v_Thread1_P2_#t~ite55_2| v_~z$r_buff0_thd3~0_34)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_63, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_34} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_34, Thread1_P2_#t~ite55=|v_Thread1_P2_#t~ite55_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_63} AuxVars[] AssignedVars[Thread1_P2_#t~ite55] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite55|=1, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [868] L797-2-->L798: Formula: (= v_~z$r_buff0_thd3~0_35 |v_Thread1_P2_#t~ite55_3|) InVars {Thread1_P2_#t~ite55=|v_Thread1_P2_#t~ite55_3|} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_35, Thread1_P2_#t~ite55=|v_Thread1_P2_#t~ite55_4|} AuxVars[] AssignedVars[~z$r_buff0_thd3~0, Thread1_P2_#t~ite55] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [870] L798-->L798-2: Formula: (and (or (= (mod v_~z$w_buff1_used~0_35 256) 0) (= 0 (mod v_~z$r_buff1_thd3~0_19 256))) (= |v_Thread1_P2_#t~ite56_2| v_~z$r_buff1_thd3~0_19) (or (= (mod v_~z$r_buff0_thd3~0_37 256) 0) (= (mod v_~z$w_buff0_used~0_66 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_35, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_37, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_66, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_19} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_35, Thread1_P2_#t~ite56=|v_Thread1_P2_#t~ite56_2|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_37, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_66, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_19} AuxVars[] AssignedVars[Thread1_P2_#t~ite56] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2_#t~ite56|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [871] L798-2-->L803: Formula: (and (= v_~z$r_buff1_thd3~0_20 |v_Thread1_P2_#t~ite56_3|) (= v_~__unbuffered_cnt~0_5 (+ v_~__unbuffered_cnt~0_6 1))) InVars {Thread1_P2_#t~ite56=|v_Thread1_P2_#t~ite56_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} OutVars{Thread1_P2_#t~ite56=|v_Thread1_P2_#t~ite56_4|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_20} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, Thread1_P2_#t~ite56, ~__unbuffered_cnt~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [561] L821-1-->L825: Formula: (= v_~main$tmp_guard0~0_1 (ite (= (ite (= v_~__unbuffered_cnt~0_7 3) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_7} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_7, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_1, ULTIMATE.start_main_#t~nondet60=|v_ULTIMATE.start_main_#t~nondet60_2|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet60] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [693] L825-->L827: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_2 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [547] L827-->L827-2: Formula: (or (= 0 (mod v_~z$w_buff0_used~0_76 256)) (= (mod v_~z$r_buff0_thd0~0_3 256) 0)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_76, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_3} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_76, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [513] L827-2-->L827-4: Formula: (and (= |v_ULTIMATE.start_main_#t~ite61_3| v_~z~0_15) (or (= (mod v_~z$w_buff1_used~0_43 256) 0) (= (mod v_~z$r_buff1_thd0~0_3 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_43, ~z~0=v_~z~0_15, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_3} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_43, ULTIMATE.start_main_#t~ite61=|v_ULTIMATE.start_main_#t~ite61_3|, ~z~0=v_~z~0_15, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite61] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite61|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [525] L827-4-->L827-5: Formula: (= |v_ULTIMATE.start_main_#t~ite62_3| |v_ULTIMATE.start_main_#t~ite61_4|) InVars {ULTIMATE.start_main_#t~ite61=|v_ULTIMATE.start_main_#t~ite61_4|} OutVars{ULTIMATE.start_main_#t~ite62=|v_ULTIMATE.start_main_#t~ite62_3|, ULTIMATE.start_main_#t~ite61=|v_ULTIMATE.start_main_#t~ite61_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite62] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite61|=0, |ULTIMATE.start_main_#t~ite62|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [529] L827-5-->L828: Formula: (= v_~z~0_16 |v_ULTIMATE.start_main_#t~ite62_5|) InVars {ULTIMATE.start_main_#t~ite62=|v_ULTIMATE.start_main_#t~ite62_5|} OutVars{ULTIMATE.start_main_#t~ite62=|v_ULTIMATE.start_main_#t~ite62_4|, ULTIMATE.start_main_#t~ite61=|v_ULTIMATE.start_main_#t~ite61_5|, ~z~0=v_~z~0_16} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite62, ULTIMATE.start_main_#t~ite61, ~z~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [680] L828-->L828-2: Formula: (and (or (= (mod v_~z$r_buff0_thd0~0_5 256) 0) (= 0 (mod v_~z$w_buff0_used~0_78 256))) (= |v_ULTIMATE.start_main_#t~ite63_3| v_~z$w_buff0_used~0_78)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_78, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_5} OutVars{ULTIMATE.start_main_#t~ite63=|v_ULTIMATE.start_main_#t~ite63_3|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_5, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_78} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite63] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite63|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [689] L828-2-->L829: Formula: (= v_~z$w_buff0_used~0_79 |v_ULTIMATE.start_main_#t~ite63_5|) InVars {ULTIMATE.start_main_#t~ite63=|v_ULTIMATE.start_main_#t~ite63_5|} OutVars{ULTIMATE.start_main_#t~ite63=|v_ULTIMATE.start_main_#t~ite63_4|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_79} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite63, ~z$w_buff0_used~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [591] L829-->L829-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite64_3| v_~z$w_buff1_used~0_45) (or (= (mod v_~z$r_buff1_thd0~0_5 256) 0) (= 0 (mod v_~z$w_buff1_used~0_45 256))) (or (= 0 (mod v_~z$r_buff0_thd0~0_7 256)) (= (mod v_~z$w_buff0_used~0_81 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_45, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_81, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_5} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_45, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_81, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_5, ULTIMATE.start_main_#t~ite64=|v_ULTIMATE.start_main_#t~ite64_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite64] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite64|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [598] L829-2-->L830: Formula: (= v_~z$w_buff1_used~0_46 |v_ULTIMATE.start_main_#t~ite64_5|) InVars {ULTIMATE.start_main_#t~ite64=|v_ULTIMATE.start_main_#t~ite64_5|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_46, ULTIMATE.start_main_#t~ite64=|v_ULTIMATE.start_main_#t~ite64_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite64] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [490] L830-->L830-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd0~0_9 256)) (= 0 (mod v_~z$w_buff0_used~0_83 256))) (= |v_ULTIMATE.start_main_#t~ite65_3| v_~z$r_buff0_thd0~0_9)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_83, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_9} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_83, ULTIMATE.start_main_#t~ite65=|v_ULTIMATE.start_main_#t~ite65_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite65] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite65|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [496] L830-2-->L831: Formula: (= v_~z$r_buff0_thd0~0_10 |v_ULTIMATE.start_main_#t~ite65_5|) InVars {ULTIMATE.start_main_#t~ite65=|v_ULTIMATE.start_main_#t~ite65_5|} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_10, ULTIMATE.start_main_#t~ite65=|v_ULTIMATE.start_main_#t~ite65_4|} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite65] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [674] L831-->L831-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite66_3| v_~z$r_buff1_thd0~0_7) (or (= (mod v_~z$r_buff1_thd0~0_7 256) 0) (= (mod v_~z$w_buff1_used~0_48 256) 0)) (or (= 0 (mod v_~z$w_buff0_used~0_85 256)) (= (mod v_~z$r_buff0_thd0~0_12 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_48, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_12, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_85, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_7} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_48, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_12, ULTIMATE.start_main_#t~ite66=|v_ULTIMATE.start_main_#t~ite66_3|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_85, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite66] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite66|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [650] L831-2-->L836: Formula: (and (= v_~z$r_buff1_thd0~0_8 |v_ULTIMATE.start_main_#t~ite66_5|) (= v_~main$tmp_guard1~0_1 (ite (= (ite (not (and (= v_~__unbuffered_p2_EBX~0_2 0) (= 0 v_~__unbuffered_p1_EAX~0_2) (= v_~__unbuffered_p0_EBX~0_2 0) (= v_~__unbuffered_p0_EAX~0_2 1) (= v_~__unbuffered_p2_EAX~0_2 1))) 1 0) 0) 0 1))) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_2, ULTIMATE.start_main_#t~ite66=|v_ULTIMATE.start_main_#t~ite66_5|} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_8, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_1, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_2, ULTIMATE.start_main_#t~ite66=|v_ULTIMATE.start_main_#t~ite66_4|} AuxVars[] AssignedVars[~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite66] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [690] L836-->L836-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_2 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [694] L836-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [555] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [549] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [544] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P2___VERIFIER_assert_~expression=1, Thread1_P2_thidvar0=2, Thread1_P2_~arg.base=0, Thread1_P2_~arg.offset=0, Thread2_P0_thidvar0=0, Thread2_P0_~arg.base=0, Thread2_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P2_#in~arg.base|=0, |Thread1_P2_#in~arg.offset|=0, |Thread1_P2___VERIFIER_assert_#in~expression|=1, |Thread2_P0_#in~arg.base|=0, |Thread2_P0_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58, main_#t~nondet59, main_#t~nondet60, main_#t~ite62, main_#t~ite61, main_#t~ite63, main_#t~ite64, main_#t~ite65, main_#t~ite66, main_~#t408~0.base, main_~#t408~0.offset, main_~#t409~0.base, main_~#t409~0.offset, main_~#t410~0.base, main_~#t410~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t408~0.base, main_~#t408~0.offset := #Ultimate.alloc(4); srcloc: L816 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t408~0.base, main_~#t408~0.offset, 4); srcloc: L816-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t409~0.base, main_~#t409~0.offset := #Ultimate.alloc(4); srcloc: L818 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t409~0.base, main_~#t409~0.offset, 4); srcloc: L818-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet59; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t410~0.base, main_~#t410~0.offset := #Ultimate.alloc(4); srcloc: L820 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(2, main_~#t410~0.base, main_~#t410~0.offset, 4); srcloc: L820-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 2 P2(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0;~z$r_buff0_thd3~0 := 1;~weak$$choice0~0 := (if 0 == #t~nondet28.base + #t~nondet28.offset then 0 else 1);havoc #t~nondet28.base, #t~nondet28.offset;~weak$$choice2~0 := (if 0 == #t~nondet29.base + #t~nondet29.offset then 0 else 1);havoc #t~nondet29.base, #t~nondet29.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite30 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 #t~ite31 := #t~ite30; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=1, |P2_#t~ite31|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite31;havoc #t~ite31;havoc #t~ite30; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite34 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite34|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0~0 := #t~ite34;havoc #t~ite32;havoc #t~ite34;havoc #t~ite33; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite37 := ~z$w_buff1~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite37|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1~0 := #t~ite37;havoc #t~ite35;havoc #t~ite36;havoc #t~ite37; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite40 := ~z$w_buff0_used~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite40|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite40;havoc #t~ite40;havoc #t~ite38;havoc #t~ite39; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite43 := ~z$w_buff1_used~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite43|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite43;havoc #t~ite43;havoc #t~ite41;havoc #t~ite42; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite46 := ~z$r_buff0_thd3~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite46|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd3~0 := #t~ite46;havoc #t~ite46;havoc #t~ite45;havoc #t~ite44; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite49 := ~z$r_buff1_thd3~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite49|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd3~0 := #t~ite49;havoc #t~ite48;havoc #t~ite47;havoc #t~ite49;~__unbuffered_p2_EAX~0 := ~z~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$flush_delayed~0 % 256;#t~ite50 := ~z$mem_tmp~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite50|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z~0 := #t~ite50;havoc #t~ite50;~z$flush_delayed~0 := 0;~__unbuffered_p2_EBX~0 := ~a~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite52 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~a~0 := 1;~x~0 := 1;~__unbuffered_p0_EAX~0 := ~x~0;~__unbuffered_p0_EBX~0 := ~y~0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 1;~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1);havoc #t~nondet4.base, #t~nondet4.offset;~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1);havoc #t~nondet5.base, #t~nondet5.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite7 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z~0 := #t~ite7;havoc #t~ite6;havoc #t~ite7; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite10 := ~z$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite10|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0~0 := #t~ite10;havoc #t~ite8;havoc #t~ite10;havoc #t~ite9; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite13 := ~z$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1~0 := #t~ite13;havoc #t~ite11;havoc #t~ite13;havoc #t~ite12; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0_used~0 := #t~ite16;havoc #t~ite15;havoc #t~ite16;havoc #t~ite14; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1_used~0 := #t~ite19;havoc #t~ite19;havoc #t~ite18;havoc #t~ite17; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff0_thd2~0 := #t~ite22;havoc #t~ite20;havoc #t~ite21;havoc #t~ite22; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff1_thd2~0 := #t~ite25;havoc #t~ite25;havoc #t~ite23;havoc #t~ite24;~__unbuffered_p1_EAX~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~z$flush_delayed~0 % 256;#t~ite26 := ~z$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite52;havoc #t~ite51;havoc #t~ite52; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite53 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite53|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 ~z~0 := #t~ite26;havoc #t~ite26;~z$flush_delayed~0 := 0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite53|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$w_buff0_used~0 := #t~ite53;havoc #t~ite53; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite54 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite54|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$w_buff1_used~0 := #t~ite54;havoc #t~ite54; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256);#t~ite55 := ~z$r_buff0_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite55|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff0_thd3~0 := #t~ite55;havoc #t~ite55; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite56 := ~z$r_buff1_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite56|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd3~0 := #t~ite56;havoc #t~ite56;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet60;~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite61 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite61|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite62 := main_#t~ite61; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite61|=0, |ULTIMATE.start_main_#t~ite62|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite62;havoc main_#t~ite62;havoc main_#t~ite61; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite63 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite63|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite63;havoc main_#t~ite63; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite64 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite64|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite64;havoc main_#t~ite64; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite65 := ~z$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite65|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite65;havoc main_#t~ite65; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite66 := ~z$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite66|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite66;havoc main_#t~ite66;~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58, main_#t~nondet59, main_#t~nondet60, main_#t~ite62, main_#t~ite61, main_#t~ite63, main_#t~ite64, main_#t~ite65, main_#t~ite66, main_~#t408~0.base, main_~#t408~0.offset, main_~#t409~0.base, main_~#t409~0.offset, main_~#t410~0.base, main_~#t410~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t408~0.base, main_~#t408~0.offset := #Ultimate.alloc(4); srcloc: L816 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t408~0.base, main_~#t408~0.offset, 4); srcloc: L816-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t409~0.base, main_~#t409~0.offset := #Ultimate.alloc(4); srcloc: L818 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t409~0.base, main_~#t409~0.offset, 4); srcloc: L818-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet59; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t410~0.base, main_~#t410~0.offset := #Ultimate.alloc(4); srcloc: L820 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(2, main_~#t410~0.base, main_~#t410~0.offset, 4); srcloc: L820-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 2 P2(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0;~z$r_buff0_thd3~0 := 1;~weak$$choice0~0 := (if 0 == #t~nondet28.base + #t~nondet28.offset then 0 else 1);havoc #t~nondet28.base, #t~nondet28.offset;~weak$$choice2~0 := (if 0 == #t~nondet29.base + #t~nondet29.offset then 0 else 1);havoc #t~nondet29.base, #t~nondet29.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite30 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 #t~ite31 := #t~ite30; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=1, |P2_#t~ite31|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite31;havoc #t~ite31;havoc #t~ite30; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite34 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite34|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0~0 := #t~ite34;havoc #t~ite32;havoc #t~ite34;havoc #t~ite33; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite37 := ~z$w_buff1~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite37|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1~0 := #t~ite37;havoc #t~ite35;havoc #t~ite36;havoc #t~ite37; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite40 := ~z$w_buff0_used~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite40|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite40;havoc #t~ite40;havoc #t~ite38;havoc #t~ite39; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite43 := ~z$w_buff1_used~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite43|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite43;havoc #t~ite43;havoc #t~ite41;havoc #t~ite42; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite46 := ~z$r_buff0_thd3~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite46|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd3~0 := #t~ite46;havoc #t~ite46;havoc #t~ite45;havoc #t~ite44; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~weak$$choice2~0 % 256;#t~ite49 := ~z$r_buff1_thd3~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite49|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd3~0 := #t~ite49;havoc #t~ite48;havoc #t~ite47;havoc #t~ite49;~__unbuffered_p2_EAX~0 := ~z~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$flush_delayed~0 % 256;#t~ite50 := ~z$mem_tmp~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite50|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z~0 := #t~ite50;havoc #t~ite50;~z$flush_delayed~0 := 0;~__unbuffered_p2_EBX~0 := ~a~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite52 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~a~0 := 1;~x~0 := 1;~__unbuffered_p0_EAX~0 := ~x~0;~__unbuffered_p0_EBX~0 := ~y~0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 1;~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1);havoc #t~nondet4.base, #t~nondet4.offset;~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1);havoc #t~nondet5.base, #t~nondet5.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite7 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z~0 := #t~ite7;havoc #t~ite6;havoc #t~ite7; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite10 := ~z$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite10|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0~0 := #t~ite10;havoc #t~ite8;havoc #t~ite10;havoc #t~ite9; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite13 := ~z$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1~0 := #t~ite13;havoc #t~ite11;havoc #t~ite13;havoc #t~ite12; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0_used~0 := #t~ite16;havoc #t~ite15;havoc #t~ite16;havoc #t~ite14; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1_used~0 := #t~ite19;havoc #t~ite19;havoc #t~ite18;havoc #t~ite17; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff0_thd2~0 := #t~ite22;havoc #t~ite20;havoc #t~ite21;havoc #t~ite22; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff1_thd2~0 := #t~ite25;havoc #t~ite25;havoc #t~ite23;havoc #t~ite24;~__unbuffered_p1_EAX~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~z$flush_delayed~0 % 256;#t~ite26 := ~z$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite52|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite52;havoc #t~ite51;havoc #t~ite52; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite53 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite53|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 ~z~0 := #t~ite26;havoc #t~ite26;~z$flush_delayed~0 := 0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite53|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$w_buff0_used~0 := #t~ite53;havoc #t~ite53; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite54 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite54|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$w_buff1_used~0 := #t~ite54;havoc #t~ite54; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256);#t~ite55 := ~z$r_buff0_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite55|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff0_thd3~0 := #t~ite55;havoc #t~ite55; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite56 := ~z$r_buff1_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite56|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd3~0 := #t~ite56;havoc #t~ite56;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet60;~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite61 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite61|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite62 := main_#t~ite61; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite61|=0, |ULTIMATE.start_main_#t~ite62|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite62;havoc main_#t~ite62;havoc main_#t~ite61; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite63 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite63|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite63;havoc main_#t~ite63; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite64 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite64|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite64;havoc main_#t~ite64; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite65 := ~z$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite65|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite65;havoc main_#t~ite65; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite66 := ~z$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite66|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite66;havoc main_#t~ite66;~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t408~0.base|=5, |ULTIMATE.start_main_~#t408~0.offset|=0, |ULTIMATE.start_main_~#t409~0.base|=7, |ULTIMATE.start_main_~#t409~0.offset|=0, |ULTIMATE.start_main_~#t410~0.base|=6, |ULTIMATE.start_main_~#t410~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L676] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L678] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [L682] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L684] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58, main_#t~nondet59, main_#t~nondet60, main_#t~ite62, main_#t~ite61, main_#t~ite63, main_#t~ite64, main_#t~ite65, main_#t~ite66, main_~#t408~0.base, main_~#t408~0.offset, main_~#t409~0.base, main_~#t409~0.offset, main_~#t410~0.base, main_~#t410~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L816] -1 call main_~#t408~0.base, main_~#t408~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 call write~int(0, main_~#t408~0.base, main_~#t408~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 havoc main_#t~nondet58; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 call main_~#t409~0.base, main_~#t409~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 call write~int(1, main_~#t409~0.base, main_~#t409~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 havoc main_#t~nondet59; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 call main_~#t410~0.base, main_~#t410~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 call write~int(2, main_~#t410~0.base, main_~#t410~0.offset, 4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FORK -1 fork 2 P2(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L804] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~weak$$choice0~0 := (if 0 == #t~nondet28.base + #t~nondet28.offset then 0 else 1); [L775] 0 havoc #t~nondet28.base, #t~nondet28.offset; [L776] 0 ~weak$$choice2~0 := (if 0 == #t~nondet29.base + #t~nondet29.offset then 0 else 1); [L776] 0 havoc #t~nondet29.base, #t~nondet29.offset; [L777] 0 ~z$flush_delayed~0 := ~weak$$choice2~0; [L778] 0 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 assume !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L779] 0 #t~ite30 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 #t~ite31 := #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=1, #t~ite31=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 ~z~0 := #t~ite31; [L779] 0 havoc #t~ite31; [L779] 0 havoc #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 assume 0 != ~weak$$choice2~0 % 256; [L780] 0 #t~ite34 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite34=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 ~z$w_buff0~0 := #t~ite34; [L780] 0 havoc #t~ite32; [L780] 0 havoc #t~ite34; [L780] 0 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 assume 0 != ~weak$$choice2~0 % 256; [L781] 0 #t~ite37 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 ~z$w_buff1~0 := #t~ite37; [L781] 0 havoc #t~ite35; [L781] 0 havoc #t~ite36; [L781] 0 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 assume 0 != ~weak$$choice2~0 % 256; [L782] 0 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite40=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 ~z$w_buff0_used~0 := #t~ite40; [L782] 0 havoc #t~ite40; [L782] 0 havoc #t~ite38; [L782] 0 havoc #t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 assume 0 != ~weak$$choice2~0 % 256; [L783] 0 #t~ite43 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite43=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 ~z$w_buff1_used~0 := #t~ite43; [L783] 0 havoc #t~ite43; [L783] 0 havoc #t~ite41; [L783] 0 havoc #t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 assume 0 != ~weak$$choice2~0 % 256; [L784] 0 #t~ite46 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite46=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 ~z$r_buff0_thd3~0 := #t~ite46; [L784] 0 havoc #t~ite46; [L784] 0 havoc #t~ite45; [L784] 0 havoc #t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 assume 0 != ~weak$$choice2~0 % 256; [L785] 0 #t~ite49 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite49=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$r_buff1_thd3~0 := #t~ite49; [L785] 0 havoc #t~ite48; [L785] 0 havoc #t~ite47; [L785] 0 havoc #t~ite49; [L786] 0 ~__unbuffered_p2_EAX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 assume 0 != ~z$flush_delayed~0 % 256; [L787] 0 #t~ite50 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite50=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z~0 := #t~ite50; [L787] 0 havoc #t~ite50; [L788] 0 ~z$flush_delayed~0 := 0; [L791] 0 ~__unbuffered_p2_EBX~0 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L794] 0 #t~ite52 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L731] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L714] 1 ~a~0 := 1; [L717] 1 ~x~0 := 1; [L720] 1 ~__unbuffered_p0_EAX~0 := ~x~0; [L723] 1 ~__unbuffered_p0_EBX~0 := ~y~0; [L728] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L732-L759] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L735] 2 ~y~0 := 1; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1); [L738] 2 havoc #t~nondet4.base, #t~nondet4.offset; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1); [L739] 2 havoc #t~nondet5.base, #t~nondet5.offset; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite6; [L742] 2 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 assume 0 != ~weak$$choice2~0 % 256; [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite10=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite8; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite9; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 assume 0 != ~weak$$choice2~0 % 256; [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite11; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 assume 0 != ~weak$$choice2~0 % 256; [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; [L745] 2 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 assume 0 != ~weak$$choice2~0 % 256; [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 assume 0 != ~weak$$choice2~0 % 256; [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite20; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 assume 0 != ~weak$$choice2~0 % 256; [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L748] 2 havoc #t~ite24; [L749] 2 ~__unbuffered_p1_EAX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 assume 0 != ~z$flush_delayed~0 % 256; [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 ~z~0 := #t~ite52; [L794] 0 havoc #t~ite51; [L794] 0 havoc #t~ite52; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L795] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L795] 0 #t~ite53 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L795] 0 ~z$w_buff0_used~0 := #t~ite53; [L795] 0 havoc #t~ite53; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L796] 0 #t~ite54 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite54=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 ~z$w_buff1_used~0 := #t~ite54; [L796] 0 havoc #t~ite54; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256); [L797] 0 #t~ite55 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite55=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 ~z$r_buff0_thd3~0 := #t~ite55; [L797] 0 havoc #t~ite55; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L798] 0 #t~ite56 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite56=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 ~z$r_buff1_thd3~0 := #t~ite56; [L798] 0 havoc #t~ite56; [L801] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 havoc main_#t~nondet60; [L823] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L825] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L827] -1 main_#t~ite61 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 main_#t~ite62 := main_#t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_#t~ite62=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 ~z~0 := main_#t~ite62; [L827] -1 havoc main_#t~ite62; [L827] -1 havoc main_#t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L828] -1 main_#t~ite63 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite63=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 ~z$w_buff0_used~0 := main_#t~ite63; [L828] -1 havoc main_#t~ite63; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L829] -1 main_#t~ite64 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite64=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 ~z$w_buff1_used~0 := main_#t~ite64; [L829] -1 havoc main_#t~ite64; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L830] -1 main_#t~ite65 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite65=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 ~z$r_buff0_thd0~0 := main_#t~ite65; [L830] -1 havoc main_#t~ite65; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L831] -1 main_#t~ite66 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite66=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 ~z$r_buff1_thd0~0 := main_#t~ite66; [L831] -1 havoc main_#t~ite66; [L834] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L676] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L678] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [L682] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L684] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58, main_#t~nondet59, main_#t~nondet60, main_#t~ite62, main_#t~ite61, main_#t~ite63, main_#t~ite64, main_#t~ite65, main_#t~ite66, main_~#t408~0.base, main_~#t408~0.offset, main_~#t409~0.base, main_~#t409~0.offset, main_~#t410~0.base, main_~#t410~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L816] -1 call main_~#t408~0.base, main_~#t408~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 call write~int(0, main_~#t408~0.base, main_~#t408~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 havoc main_#t~nondet58; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 call main_~#t409~0.base, main_~#t409~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 call write~int(1, main_~#t409~0.base, main_~#t409~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 havoc main_#t~nondet59; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 call main_~#t410~0.base, main_~#t410~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 call write~int(2, main_~#t410~0.base, main_~#t410~0.offset, 4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FORK -1 fork 2 P2(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L804] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~weak$$choice0~0 := (if 0 == #t~nondet28.base + #t~nondet28.offset then 0 else 1); [L775] 0 havoc #t~nondet28.base, #t~nondet28.offset; [L776] 0 ~weak$$choice2~0 := (if 0 == #t~nondet29.base + #t~nondet29.offset then 0 else 1); [L776] 0 havoc #t~nondet29.base, #t~nondet29.offset; [L777] 0 ~z$flush_delayed~0 := ~weak$$choice2~0; [L778] 0 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 assume !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L779] 0 #t~ite30 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 #t~ite31 := #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=1, #t~ite31=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 ~z~0 := #t~ite31; [L779] 0 havoc #t~ite31; [L779] 0 havoc #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 assume 0 != ~weak$$choice2~0 % 256; [L780] 0 #t~ite34 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite34=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 ~z$w_buff0~0 := #t~ite34; [L780] 0 havoc #t~ite32; [L780] 0 havoc #t~ite34; [L780] 0 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 assume 0 != ~weak$$choice2~0 % 256; [L781] 0 #t~ite37 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 ~z$w_buff1~0 := #t~ite37; [L781] 0 havoc #t~ite35; [L781] 0 havoc #t~ite36; [L781] 0 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 assume 0 != ~weak$$choice2~0 % 256; [L782] 0 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite40=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 ~z$w_buff0_used~0 := #t~ite40; [L782] 0 havoc #t~ite40; [L782] 0 havoc #t~ite38; [L782] 0 havoc #t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 assume 0 != ~weak$$choice2~0 % 256; [L783] 0 #t~ite43 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite43=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 ~z$w_buff1_used~0 := #t~ite43; [L783] 0 havoc #t~ite43; [L783] 0 havoc #t~ite41; [L783] 0 havoc #t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 assume 0 != ~weak$$choice2~0 % 256; [L784] 0 #t~ite46 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite46=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 ~z$r_buff0_thd3~0 := #t~ite46; [L784] 0 havoc #t~ite46; [L784] 0 havoc #t~ite45; [L784] 0 havoc #t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 assume 0 != ~weak$$choice2~0 % 256; [L785] 0 #t~ite49 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite49=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$r_buff1_thd3~0 := #t~ite49; [L785] 0 havoc #t~ite48; [L785] 0 havoc #t~ite47; [L785] 0 havoc #t~ite49; [L786] 0 ~__unbuffered_p2_EAX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 assume 0 != ~z$flush_delayed~0 % 256; [L787] 0 #t~ite50 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite50=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z~0 := #t~ite50; [L787] 0 havoc #t~ite50; [L788] 0 ~z$flush_delayed~0 := 0; [L791] 0 ~__unbuffered_p2_EBX~0 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L794] 0 #t~ite52 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L731] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L714] 1 ~a~0 := 1; [L717] 1 ~x~0 := 1; [L720] 1 ~__unbuffered_p0_EAX~0 := ~x~0; [L723] 1 ~__unbuffered_p0_EBX~0 := ~y~0; [L728] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L732-L759] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L735] 2 ~y~0 := 1; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1); [L738] 2 havoc #t~nondet4.base, #t~nondet4.offset; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1); [L739] 2 havoc #t~nondet5.base, #t~nondet5.offset; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite6; [L742] 2 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 assume 0 != ~weak$$choice2~0 % 256; [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite10=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite8; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite9; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 assume 0 != ~weak$$choice2~0 % 256; [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite11; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 assume 0 != ~weak$$choice2~0 % 256; [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; [L745] 2 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 assume 0 != ~weak$$choice2~0 % 256; [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 assume 0 != ~weak$$choice2~0 % 256; [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite20; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 assume 0 != ~weak$$choice2~0 % 256; [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L748] 2 havoc #t~ite24; [L749] 2 ~__unbuffered_p1_EAX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 assume 0 != ~z$flush_delayed~0 % 256; [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 ~z~0 := #t~ite52; [L794] 0 havoc #t~ite51; [L794] 0 havoc #t~ite52; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L795] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L795] 0 #t~ite53 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L795] 0 ~z$w_buff0_used~0 := #t~ite53; [L795] 0 havoc #t~ite53; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L796] 0 #t~ite54 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite54=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 ~z$w_buff1_used~0 := #t~ite54; [L796] 0 havoc #t~ite54; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256); [L797] 0 #t~ite55 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite55=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 ~z$r_buff0_thd3~0 := #t~ite55; [L797] 0 havoc #t~ite55; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L798] 0 #t~ite56 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite56=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 ~z$r_buff1_thd3~0 := #t~ite56; [L798] 0 havoc #t~ite56; [L801] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 havoc main_#t~nondet60; [L823] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L825] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L827] -1 main_#t~ite61 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 main_#t~ite62 := main_#t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_#t~ite62=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 ~z~0 := main_#t~ite62; [L827] -1 havoc main_#t~ite62; [L827] -1 havoc main_#t~ite61; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L828] -1 main_#t~ite63 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite63=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 ~z$w_buff0_used~0 := main_#t~ite63; [L828] -1 havoc main_#t~ite63; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L829] -1 main_#t~ite64 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite64=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 ~z$w_buff1_used~0 := main_#t~ite64; [L829] -1 havoc main_#t~ite64; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L830] -1 main_#t~ite65 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite65=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 ~z$r_buff0_thd0~0 := main_#t~ite65; [L830] -1 havoc main_#t~ite65; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L831] -1 main_#t~ite66 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite66=0, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 ~z$r_buff1_thd0~0 := main_#t~ite66; [L831] -1 havoc main_#t~ite66; [L834] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0.base=5, main_~#t408~0.offset=0, main_~#t409~0.base=7, main_~#t409~0.offset=0, main_~#t410~0.base=6, main_~#t410~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L676] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L678] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [L682] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L684] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58, main_#t~nondet59, main_#t~nondet60, main_#t~ite62, main_#t~ite61, main_#t~ite63, main_#t~ite64, main_#t~ite65, main_#t~ite66, main_~#t408~0, main_~#t409~0, main_~#t410~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L816] FCALL -1 call main_~#t408~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FCALL -1 call write~int(0, main_~#t408~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 havoc main_#t~nondet58; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] FCALL -1 call main_~#t409~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FCALL -1 call write~int(1, main_~#t409~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 havoc main_#t~nondet59; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] FCALL -1 call main_~#t410~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FCALL -1 call write~int(2, main_~#t410~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L804] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~weak$$choice0~0 := (if 0 == #t~nondet28!base + #t~nondet28!offset then 0 else 1); [L775] 0 havoc #t~nondet28; [L776] 0 ~weak$$choice2~0 := (if 0 == #t~nondet29!base + #t~nondet29!offset then 0 else 1); [L776] 0 havoc #t~nondet29; [L777] 0 ~z$flush_delayed~0 := ~weak$$choice2~0; [L778] 0 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] COND FALSE 0 !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L779] 0 #t~ite30 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 #t~ite31 := #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=1, #t~ite31=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 ~z~0 := #t~ite31; [L779] 0 havoc #t~ite31; [L779] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L780] 0 #t~ite34 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite34=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 ~z$w_buff0~0 := #t~ite34; [L780] 0 havoc #t~ite32; [L780] 0 havoc #t~ite34; [L780] 0 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L781] 0 #t~ite37 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 ~z$w_buff1~0 := #t~ite37; [L781] 0 havoc #t~ite35; [L781] 0 havoc #t~ite36; [L781] 0 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L782] 0 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite40=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 ~z$w_buff0_used~0 := #t~ite40; [L782] 0 havoc #t~ite40; [L782] 0 havoc #t~ite38; [L782] 0 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L783] 0 #t~ite43 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite43=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 ~z$w_buff1_used~0 := #t~ite43; [L783] 0 havoc #t~ite43; [L783] 0 havoc #t~ite41; [L783] 0 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L784] 0 #t~ite46 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite46=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 ~z$r_buff0_thd3~0 := #t~ite46; [L784] 0 havoc #t~ite46; [L784] 0 havoc #t~ite45; [L784] 0 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L785] 0 #t~ite49 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite49=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$r_buff1_thd3~0 := #t~ite49; [L785] 0 havoc #t~ite48; [L785] 0 havoc #t~ite47; [L785] 0 havoc #t~ite49; [L786] 0 ~__unbuffered_p2_EAX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND TRUE 0 0 != ~z$flush_delayed~0 % 256 [L787] 0 #t~ite50 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite50=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z~0 := #t~ite50; [L787] 0 havoc #t~ite50; [L788] 0 ~z$flush_delayed~0 := 0; [L791] 0 ~__unbuffered_p2_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L794] 0 #t~ite52 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L731] 1 ~arg := #in~arg; [L714] 1 ~a~0 := 1; [L717] 1 ~x~0 := 1; [L720] 1 ~__unbuffered_p0_EAX~0 := ~x~0; [L723] 1 ~__unbuffered_p0_EBX~0 := ~y~0; [L728] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L732-L759] 2 ~arg := #in~arg; [L735] 2 ~y~0 := 1; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite6; [L742] 2 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite8; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite9; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite11; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; [L745] 2 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite20; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L748] 2 havoc #t~ite24; [L749] 2 ~__unbuffered_p1_EAX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 ~z~0 := #t~ite52; [L794] 0 havoc #t~ite51; [L794] 0 havoc #t~ite52; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L795] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L795] 0 #t~ite53 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L795] 0 ~z$w_buff0_used~0 := #t~ite53; [L795] 0 havoc #t~ite53; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L796] 0 #t~ite54 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite54=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 ~z$w_buff1_used~0 := #t~ite54; [L796] 0 havoc #t~ite54; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L797] 0 #t~ite55 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite55=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 ~z$r_buff0_thd3~0 := #t~ite55; [L797] 0 havoc #t~ite55; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L798] 0 #t~ite56 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite56=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 ~z$r_buff1_thd3~0 := #t~ite56; [L798] 0 havoc #t~ite56; [L801] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 havoc main_#t~nondet60; [L823] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L825] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L827] -1 main_#t~ite61 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 main_#t~ite62 := main_#t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_#t~ite62=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 ~z~0 := main_#t~ite62; [L827] -1 havoc main_#t~ite62; [L827] -1 havoc main_#t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L828] -1 main_#t~ite63 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite63=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 ~z$w_buff0_used~0 := main_#t~ite63; [L828] -1 havoc main_#t~ite63; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L829] -1 main_#t~ite64 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite64=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 ~z$w_buff1_used~0 := main_#t~ite64; [L829] -1 havoc main_#t~ite64; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L830] -1 main_#t~ite65 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite65=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 ~z$r_buff0_thd0~0 := main_#t~ite65; [L830] -1 havoc main_#t~ite65; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L831] -1 main_#t~ite66 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite66=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 ~z$r_buff1_thd0~0 := main_#t~ite66; [L831] -1 havoc main_#t~ite66; [L834] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L676] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L678] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [L682] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L684] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet58, main_#t~nondet59, main_#t~nondet60, main_#t~ite62, main_#t~ite61, main_#t~ite63, main_#t~ite64, main_#t~ite65, main_#t~ite66, main_~#t408~0, main_~#t409~0, main_~#t410~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L816] FCALL -1 call main_~#t408~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FCALL -1 call write~int(0, main_~#t408~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 havoc main_#t~nondet58; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] FCALL -1 call main_~#t409~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FCALL -1 call write~int(1, main_~#t409~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 havoc main_#t~nondet59; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] FCALL -1 call main_~#t410~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FCALL -1 call write~int(2, main_~#t410~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L804] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~weak$$choice0~0 := (if 0 == #t~nondet28!base + #t~nondet28!offset then 0 else 1); [L775] 0 havoc #t~nondet28; [L776] 0 ~weak$$choice2~0 := (if 0 == #t~nondet29!base + #t~nondet29!offset then 0 else 1); [L776] 0 havoc #t~nondet29; [L777] 0 ~z$flush_delayed~0 := ~weak$$choice2~0; [L778] 0 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] COND FALSE 0 !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L779] 0 #t~ite30 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 #t~ite31 := #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=1, #t~ite31=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 ~z~0 := #t~ite31; [L779] 0 havoc #t~ite31; [L779] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L780] 0 #t~ite34 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite34=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 ~z$w_buff0~0 := #t~ite34; [L780] 0 havoc #t~ite32; [L780] 0 havoc #t~ite34; [L780] 0 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L781] 0 #t~ite37 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 ~z$w_buff1~0 := #t~ite37; [L781] 0 havoc #t~ite35; [L781] 0 havoc #t~ite36; [L781] 0 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L782] 0 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite40=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 ~z$w_buff0_used~0 := #t~ite40; [L782] 0 havoc #t~ite40; [L782] 0 havoc #t~ite38; [L782] 0 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L783] 0 #t~ite43 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite43=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 ~z$w_buff1_used~0 := #t~ite43; [L783] 0 havoc #t~ite43; [L783] 0 havoc #t~ite41; [L783] 0 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L784] 0 #t~ite46 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite46=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 ~z$r_buff0_thd3~0 := #t~ite46; [L784] 0 havoc #t~ite46; [L784] 0 havoc #t~ite45; [L784] 0 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L785] 0 #t~ite49 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite49=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$r_buff1_thd3~0 := #t~ite49; [L785] 0 havoc #t~ite48; [L785] 0 havoc #t~ite47; [L785] 0 havoc #t~ite49; [L786] 0 ~__unbuffered_p2_EAX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND TRUE 0 0 != ~z$flush_delayed~0 % 256 [L787] 0 #t~ite50 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite50=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z~0 := #t~ite50; [L787] 0 havoc #t~ite50; [L788] 0 ~z$flush_delayed~0 := 0; [L791] 0 ~__unbuffered_p2_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L794] 0 #t~ite52 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L731] 1 ~arg := #in~arg; [L714] 1 ~a~0 := 1; [L717] 1 ~x~0 := 1; [L720] 1 ~__unbuffered_p0_EAX~0 := ~x~0; [L723] 1 ~__unbuffered_p0_EBX~0 := ~y~0; [L728] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L732-L759] 2 ~arg := #in~arg; [L735] 2 ~y~0 := 1; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite6; [L742] 2 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite8; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite9; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite11; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; [L745] 2 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite20; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L748] 2 havoc #t~ite24; [L749] 2 ~__unbuffered_p1_EAX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, #t~ite52=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 ~z~0 := #t~ite52; [L794] 0 havoc #t~ite51; [L794] 0 havoc #t~ite52; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L795] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L795] 0 #t~ite53 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite53=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L795] 0 ~z$w_buff0_used~0 := #t~ite53; [L795] 0 havoc #t~ite53; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L796] 0 #t~ite54 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite54=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 ~z$w_buff1_used~0 := #t~ite54; [L796] 0 havoc #t~ite54; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L797] 0 #t~ite55 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite55=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 ~z$r_buff0_thd3~0 := #t~ite55; [L797] 0 havoc #t~ite55; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L798] 0 #t~ite56 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite56=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 ~z$r_buff1_thd3~0 := #t~ite56; [L798] 0 havoc #t~ite56; [L801] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 havoc main_#t~nondet60; [L823] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L825] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L827] -1 main_#t~ite61 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 main_#t~ite62 := main_#t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite61=0, main_#t~ite62=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 ~z~0 := main_#t~ite62; [L827] -1 havoc main_#t~ite62; [L827] -1 havoc main_#t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L828] -1 main_#t~ite63 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite63=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 ~z$w_buff0_used~0 := main_#t~ite63; [L828] -1 havoc main_#t~ite63; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L829] -1 main_#t~ite64 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite64=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 ~z$w_buff1_used~0 := main_#t~ite64; [L829] -1 havoc main_#t~ite64; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L830] -1 main_#t~ite65 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite65=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 ~z$r_buff0_thd0~0 := main_#t~ite65; [L830] -1 havoc main_#t~ite65; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L831] -1 main_#t~ite66 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite66=0, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 ~z$r_buff1_thd0~0 := main_#t~ite66; [L831] -1 havoc main_#t~ite66; [L834] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L836] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t408~0!base=5, main_~#t408~0!offset=0, main_~#t409~0!base=7, main_~#t409~0!offset=0, main_~#t410~0!base=6, main_~#t410~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L676] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L678] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [L682] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L684] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L816] FCALL -1 call ~#t408~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FCALL -1 call write~int(0, ~#t408~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 havoc #t~nondet58; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] FCALL -1 call ~#t409~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FCALL -1 call write~int(1, ~#t409~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 havoc #t~nondet59; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] FCALL -1 call ~#t410~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FCALL -1 call write~int(2, ~#t410~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L804] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~weak$$choice0~0 := (if 0 == #t~nondet28!base + #t~nondet28!offset then 0 else 1); [L775] 0 havoc #t~nondet28; [L776] 0 ~weak$$choice2~0 := (if 0 == #t~nondet29!base + #t~nondet29!offset then 0 else 1); [L776] 0 havoc #t~nondet29; [L777] 0 ~z$flush_delayed~0 := ~weak$$choice2~0; [L778] 0 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] COND FALSE 0 !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L779] 0 #t~ite30 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 #t~ite31 := #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 ~z~0 := #t~ite31; [L779] 0 havoc #t~ite31; [L779] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L780] 0 #t~ite34 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 ~z$w_buff0~0 := #t~ite34; [L780] 0 havoc #t~ite32; [L780] 0 havoc #t~ite34; [L780] 0 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L781] 0 #t~ite37 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 ~z$w_buff1~0 := #t~ite37; [L781] 0 havoc #t~ite35; [L781] 0 havoc #t~ite36; [L781] 0 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L782] 0 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 ~z$w_buff0_used~0 := #t~ite40; [L782] 0 havoc #t~ite40; [L782] 0 havoc #t~ite38; [L782] 0 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L783] 0 #t~ite43 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 ~z$w_buff1_used~0 := #t~ite43; [L783] 0 havoc #t~ite43; [L783] 0 havoc #t~ite41; [L783] 0 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L784] 0 #t~ite46 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 ~z$r_buff0_thd3~0 := #t~ite46; [L784] 0 havoc #t~ite46; [L784] 0 havoc #t~ite45; [L784] 0 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L785] 0 #t~ite49 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$r_buff1_thd3~0 := #t~ite49; [L785] 0 havoc #t~ite48; [L785] 0 havoc #t~ite47; [L785] 0 havoc #t~ite49; [L786] 0 ~__unbuffered_p2_EAX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND TRUE 0 0 != ~z$flush_delayed~0 % 256 [L787] 0 #t~ite50 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z~0 := #t~ite50; [L787] 0 havoc #t~ite50; [L788] 0 ~z$flush_delayed~0 := 0; [L791] 0 ~__unbuffered_p2_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L794] 0 #t~ite52 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L731] 1 ~arg := #in~arg; [L714] 1 ~a~0 := 1; [L717] 1 ~x~0 := 1; [L720] 1 ~__unbuffered_p0_EAX~0 := ~x~0; [L723] 1 ~__unbuffered_p0_EBX~0 := ~y~0; [L728] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L732-L759] 2 ~arg := #in~arg; [L735] 2 ~y~0 := 1; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite6; [L742] 2 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite8; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite9; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite11; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; [L745] 2 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite20; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L748] 2 havoc #t~ite24; [L749] 2 ~__unbuffered_p1_EAX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 ~z~0 := #t~ite52; [L794] 0 havoc #t~ite51; [L794] 0 havoc #t~ite52; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L795] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L795] 0 #t~ite53 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L795] 0 ~z$w_buff0_used~0 := #t~ite53; [L795] 0 havoc #t~ite53; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L796] 0 #t~ite54 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 ~z$w_buff1_used~0 := #t~ite54; [L796] 0 havoc #t~ite54; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L797] 0 #t~ite55 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 ~z$r_buff0_thd3~0 := #t~ite55; [L797] 0 havoc #t~ite55; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L798] 0 #t~ite56 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 ~z$r_buff1_thd3~0 := #t~ite56; [L798] 0 havoc #t~ite56; [L801] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 havoc #t~nondet60; [L823] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L825] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L827] -1 #t~ite61 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 #t~ite62 := #t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 ~z~0 := #t~ite62; [L827] -1 havoc #t~ite62; [L827] -1 havoc #t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L828] -1 #t~ite63 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 ~z$w_buff0_used~0 := #t~ite63; [L828] -1 havoc #t~ite63; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L829] -1 #t~ite64 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 ~z$w_buff1_used~0 := #t~ite64; [L829] -1 havoc #t~ite64; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L830] -1 #t~ite65 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 ~z$r_buff0_thd0~0 := #t~ite65; [L830] -1 havoc #t~ite65; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L831] -1 #t~ite66 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 ~z$r_buff1_thd0~0 := #t~ite66; [L831] -1 havoc #t~ite66; [L834] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L676] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L678] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L680] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0] [L682] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L684] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L816] FCALL -1 call ~#t408~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FCALL -1 call write~int(0, ~#t408~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 havoc #t~nondet58; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] FCALL -1 call ~#t409~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FCALL -1 call write~int(1, ~#t409~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 havoc #t~nondet59; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] FCALL -1 call ~#t410~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FCALL -1 call write~int(2, ~#t410~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L804] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~weak$$choice0~0 := (if 0 == #t~nondet28!base + #t~nondet28!offset then 0 else 1); [L775] 0 havoc #t~nondet28; [L776] 0 ~weak$$choice2~0 := (if 0 == #t~nondet29!base + #t~nondet29!offset then 0 else 1); [L776] 0 havoc #t~nondet29; [L777] 0 ~z$flush_delayed~0 := ~weak$$choice2~0; [L778] 0 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] COND FALSE 0 !((0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd3~0 % 256 && 0 == ~z$r_buff1_thd3~0 % 256)) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L779] 0 #t~ite30 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 #t~ite31 := #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L779] 0 ~z~0 := #t~ite31; [L779] 0 havoc #t~ite31; [L779] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L780] 0 #t~ite34 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L780] 0 ~z$w_buff0~0 := #t~ite34; [L780] 0 havoc #t~ite32; [L780] 0 havoc #t~ite34; [L780] 0 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L781] 0 #t~ite37 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L781] 0 ~z$w_buff1~0 := #t~ite37; [L781] 0 havoc #t~ite35; [L781] 0 havoc #t~ite36; [L781] 0 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L782] 0 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L782] 0 ~z$w_buff0_used~0 := #t~ite40; [L782] 0 havoc #t~ite40; [L782] 0 havoc #t~ite38; [L782] 0 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L783] 0 #t~ite43 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L783] 0 ~z$w_buff1_used~0 := #t~ite43; [L783] 0 havoc #t~ite43; [L783] 0 havoc #t~ite41; [L783] 0 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L784] 0 #t~ite46 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L784] 0 ~z$r_buff0_thd3~0 := #t~ite46; [L784] 0 havoc #t~ite46; [L784] 0 havoc #t~ite45; [L784] 0 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~weak$$choice2~0 % 256 [L785] 0 #t~ite49 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$r_buff1_thd3~0 := #t~ite49; [L785] 0 havoc #t~ite48; [L785] 0 havoc #t~ite47; [L785] 0 havoc #t~ite49; [L786] 0 ~__unbuffered_p2_EAX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND TRUE 0 0 != ~z$flush_delayed~0 % 256 [L787] 0 #t~ite50 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z~0 := #t~ite50; [L787] 0 havoc #t~ite50; [L788] 0 ~z$flush_delayed~0 := 0; [L791] 0 ~__unbuffered_p2_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L794] 0 #t~ite52 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L731] 1 ~arg := #in~arg; [L714] 1 ~a~0 := 1; [L717] 1 ~x~0 := 1; [L720] 1 ~__unbuffered_p0_EAX~0 := ~x~0; [L723] 1 ~__unbuffered_p0_EBX~0 := ~y~0; [L728] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L732-L759] 2 ~arg := #in~arg; [L735] 2 ~y~0 := 1; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite6; [L742] 2 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite8; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite9; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite11; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; [L745] 2 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite20; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L748] 2 havoc #t~ite24; [L749] 2 ~__unbuffered_p1_EAX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L794] 0 ~z~0 := #t~ite52; [L794] 0 havoc #t~ite51; [L794] 0 havoc #t~ite52; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L795] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L795] 0 #t~ite53 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L795] 0 ~z$w_buff0_used~0 := #t~ite53; [L795] 0 havoc #t~ite53; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L796] 0 #t~ite54 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L796] 0 ~z$w_buff1_used~0 := #t~ite54; [L796] 0 havoc #t~ite54; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L797] 0 #t~ite55 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L797] 0 ~z$r_buff0_thd3~0 := #t~ite55; [L797] 0 havoc #t~ite55; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L798] 0 #t~ite56 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] 0 ~z$r_buff1_thd3~0 := #t~ite56; [L798] 0 havoc #t~ite56; [L801] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 havoc #t~nondet60; [L823] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L825] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L827] -1 #t~ite61 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 #t~ite62 := #t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L827] -1 ~z~0 := #t~ite62; [L827] -1 havoc #t~ite62; [L827] -1 havoc #t~ite61; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L828] -1 #t~ite63 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L828] -1 ~z$w_buff0_used~0 := #t~ite63; [L828] -1 havoc #t~ite63; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L829] -1 #t~ite64 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L829] -1 ~z$w_buff1_used~0 := #t~ite64; [L829] -1 havoc #t~ite64; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L830] -1 #t~ite65 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L830] -1 ~z$r_buff0_thd0~0 := #t~ite65; [L830] -1 havoc #t~ite65; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L831] -1 #t~ite66 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L831] -1 ~z$r_buff1_thd0~0 := #t~ite66; [L831] -1 havoc #t~ite66; [L834] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 0 == ~__unbuffered_p1_EAX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L672] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L674] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L676] -1 int __unbuffered_p0_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0] [L678] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0] [L680] -1 int __unbuffered_p2_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0] [L682] -1 int __unbuffered_p2_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0] [L684] -1 int a = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0] [L685] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0] [L686] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0] [L688] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L690] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L692] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L693] -1 _Bool z$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0] [L694] -1 int z$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0] [L695] -1 _Bool z$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0] [L696] -1 _Bool z$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0] [L697] -1 _Bool z$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0] [L698] -1 _Bool z$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0] [L699] -1 _Bool z$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0] [L700] -1 _Bool z$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0] [L701] -1 _Bool z$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0] [L702] -1 _Bool z$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0] [L703] -1 _Bool z$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0] [L704] -1 int *z$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}] [L705] -1 int z$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0] [L706] -1 _Bool z$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0] [L707] -1 int z$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0] [L708] -1 _Bool z$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L709] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L710] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L816] -1 pthread_t t408; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] FCALL, FORK -1 pthread_create(&t408, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] -1 pthread_t t409; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L819] FCALL, FORK -1 pthread_create(&t409, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L820] -1 pthread_t t410; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L821] FCALL, FORK -1 pthread_create(&t410, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L763] 0 z$w_buff1 = z$w_buff0 [L764] 0 z$w_buff0 = 1 [L765] 0 z$w_buff1_used = z$w_buff0_used [L766] 0 z$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] 0 z$r_buff1_thd0 = z$r_buff0_thd0 [L769] 0 z$r_buff1_thd1 = z$r_buff0_thd1 [L770] 0 z$r_buff1_thd2 = z$r_buff0_thd2 [L771] 0 z$r_buff1_thd3 = z$r_buff0_thd3 [L772] 0 z$r_buff0_thd3 = (_Bool)1 [L775] 0 weak$$choice0 = __VERIFIER_nondet_pointer() [L776] 0 weak$$choice2 = __VERIFIER_nondet_pointer() [L777] 0 z$flush_delayed = weak$$choice2 [L778] 0 z$mem_tmp = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L779] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L779] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L779] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L779] 0 z = !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) [L780] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L780] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0)) [L781] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L781] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff1 : z$w_buff1)) [L782] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L782] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used)) [L783] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L783] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L784] EXPR 0 weak$$choice2 ? z$r_buff0_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff0_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] 0 z$r_buff0_thd3 = weak$$choice2 ? z$r_buff0_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff0_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3)) [L785] EXPR 0 weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L785] 0 z$r_buff1_thd3 = weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L786] 0 __unbuffered_p2_EAX = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L787] EXPR 0 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L787] 0 z = z$flush_delayed ? z$mem_tmp : z [L788] 0 z$flush_delayed = (_Bool)0 [L791] 0 __unbuffered_p2_EBX = a VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L794] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L714] 1 a = 1 [L717] 1 x = 1 [L720] 1 __unbuffered_p0_EAX = x [L723] 1 __unbuffered_p0_EBX = y [L728] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L735] 2 y = 1 [L738] 2 weak$$choice0 = __VERIFIER_nondet_pointer() [L739] 2 weak$$choice2 = __VERIFIER_nondet_pointer() [L740] 2 z$flush_delayed = weak$$choice2 [L741] 2 z$mem_tmp = z VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] EXPR 2 !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] 2 z = !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) [L743] EXPR 2 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0))=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L743] 2 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) [L744] EXPR 2 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] 2 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) [L745] EXPR 2 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used))=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L745] 2 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) [L746] EXPR 2 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L746] 2 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L747] EXPR 2 weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L747] 2 z$r_buff0_thd2 = weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) [L748] EXPR 2 weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L748] 2 z$r_buff1_thd2 = weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L749] 2 __unbuffered_p1_EAX = z VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L750] EXPR 2 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L794] 0 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L795] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L750] 2 z = z$flush_delayed ? z$mem_tmp : z [L751] 2 z$flush_delayed = (_Bool)0 [L756] 2 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L795] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L796] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L796] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L797] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L797] 0 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L798] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L798] 0 z$r_buff1_thd3 = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 [L801] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L823] -1 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] EXPR -1 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] -1 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L828] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] -1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L829] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] -1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L830] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L830] -1 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L831] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L831] -1 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L834] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 1 && __unbuffered_p0_EBX == 0 && __unbuffered_p1_EAX == 0 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 0) VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] ----- [2018-11-23 13:19:24,093 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_d497b286-8028-4f68-b58d-1b6d5eed2d5b/bin-2019/uautomizer/witness.graphml [2018-11-23 13:19:24,093 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 13:19:24,093 INFO L168 Benchmark]: Toolchain (without parser) took 379878.40 ms. Allocated memory was 1.0 GB in the beginning and 9.4 GB in the end (delta: 8.4 GB). Free memory was 956.6 MB in the beginning and 3.8 GB in the end (delta: -2.8 GB). Peak memory consumption was 5.5 GB. Max. memory is 11.5 GB. [2018-11-23 13:19:24,095 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 13:19:24,095 INFO L168 Benchmark]: CACSL2BoogieTranslator took 448.36 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 153.1 MB). Free memory was 956.6 MB in the beginning and 1.1 GB in the end (delta: -173.8 MB). Peak memory consumption was 38.5 MB. Max. memory is 11.5 GB. [2018-11-23 13:19:24,095 INFO L168 Benchmark]: Boogie Procedure Inliner took 46.06 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.8 MB). Peak memory consumption was 3.8 MB. Max. memory is 11.5 GB. [2018-11-23 13:19:24,095 INFO L168 Benchmark]: Boogie Preprocessor took 31.84 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-23 13:19:24,095 INFO L168 Benchmark]: RCFGBuilder took 651.55 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 62.3 MB). Peak memory consumption was 62.3 MB. Max. memory is 11.5 GB. [2018-11-23 13:19:24,096 INFO L168 Benchmark]: TraceAbstraction took 369966.36 ms. Allocated memory was 1.2 GB in the beginning and 9.4 GB in the end (delta: 8.2 GB). Free memory was 1.1 GB in the beginning and 4.0 GB in the end (delta: -3.0 GB). Peak memory consumption was 5.3 GB. Max. memory is 11.5 GB. [2018-11-23 13:19:24,096 INFO L168 Benchmark]: Witness Printer took 8731.05 ms. Allocated memory is still 9.4 GB. Free memory was 4.0 GB in the beginning and 3.8 GB in the end (delta: 216.1 MB). Peak memory consumption was 216.1 MB. Max. memory is 11.5 GB. [2018-11-23 13:19:24,097 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 448.36 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 153.1 MB). Free memory was 956.6 MB in the beginning and 1.1 GB in the end (delta: -173.8 MB). Peak memory consumption was 38.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 46.06 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.8 MB). Peak memory consumption was 3.8 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 31.84 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 651.55 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 62.3 MB). Peak memory consumption was 62.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 369966.36 ms. Allocated memory was 1.2 GB in the beginning and 9.4 GB in the end (delta: 8.2 GB). Free memory was 1.1 GB in the beginning and 4.0 GB in the end (delta: -3.0 GB). Peak memory consumption was 5.3 GB. Max. memory is 11.5 GB. * Witness Printer took 8731.05 ms. Allocated memory is still 9.4 GB. Free memory was 4.0 GB in the beginning and 3.8 GB in the end (delta: 216.1 MB). Peak memory consumption was 216.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L672] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L674] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L676] -1 int __unbuffered_p0_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0] [L678] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0] [L680] -1 int __unbuffered_p2_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0] [L682] -1 int __unbuffered_p2_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0] [L684] -1 int a = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0] [L685] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0] [L686] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0] [L688] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L690] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L692] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L693] -1 _Bool z$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0] [L694] -1 int z$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0] [L695] -1 _Bool z$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0] [L696] -1 _Bool z$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0] [L697] -1 _Bool z$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0] [L698] -1 _Bool z$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0] [L699] -1 _Bool z$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0] [L700] -1 _Bool z$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0] [L701] -1 _Bool z$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0] [L702] -1 _Bool z$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0] [L703] -1 _Bool z$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0] [L704] -1 int *z$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}] [L705] -1 int z$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0] [L706] -1 _Bool z$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0] [L707] -1 int z$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0] [L708] -1 _Bool z$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L709] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L710] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L816] -1 pthread_t t408; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] FCALL, FORK -1 pthread_create(&t408, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] -1 pthread_t t409; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L819] FCALL, FORK -1 pthread_create(&t409, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L820] -1 pthread_t t410; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L821] FCALL, FORK -1 pthread_create(&t410, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L763] 0 z$w_buff1 = z$w_buff0 [L764] 0 z$w_buff0 = 1 [L765] 0 z$w_buff1_used = z$w_buff0_used [L766] 0 z$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] 0 z$r_buff1_thd0 = z$r_buff0_thd0 [L769] 0 z$r_buff1_thd1 = z$r_buff0_thd1 [L770] 0 z$r_buff1_thd2 = z$r_buff0_thd2 [L771] 0 z$r_buff1_thd3 = z$r_buff0_thd3 [L772] 0 z$r_buff0_thd3 = (_Bool)1 [L775] 0 weak$$choice0 = __VERIFIER_nondet_pointer() [L776] 0 weak$$choice2 = __VERIFIER_nondet_pointer() [L777] 0 z$flush_delayed = weak$$choice2 [L778] 0 z$mem_tmp = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L779] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L779] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L779] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L779] 0 z = !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) [L780] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L780] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0)) [L781] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L781] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff1 : z$w_buff1)) [L782] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L782] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used)) [L783] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L783] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L784] EXPR 0 weak$$choice2 ? z$r_buff0_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff0_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] 0 z$r_buff0_thd3 = weak$$choice2 ? z$r_buff0_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff0_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3)) [L785] EXPR 0 weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L785] 0 z$r_buff1_thd3 = weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L786] 0 __unbuffered_p2_EAX = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L787] EXPR 0 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L787] 0 z = z$flush_delayed ? z$mem_tmp : z [L788] 0 z$flush_delayed = (_Bool)0 [L791] 0 __unbuffered_p2_EBX = a VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L794] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L714] 1 a = 1 [L717] 1 x = 1 [L720] 1 __unbuffered_p0_EAX = x [L723] 1 __unbuffered_p0_EBX = y [L728] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L735] 2 y = 1 [L738] 2 weak$$choice0 = __VERIFIER_nondet_pointer() [L739] 2 weak$$choice2 = __VERIFIER_nondet_pointer() [L740] 2 z$flush_delayed = weak$$choice2 [L741] 2 z$mem_tmp = z VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] EXPR 2 !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] 2 z = !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) [L743] EXPR 2 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0))=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L743] 2 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) [L744] EXPR 2 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] 2 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) [L745] EXPR 2 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used))=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L745] 2 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) [L746] EXPR 2 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L746] 2 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L747] EXPR 2 weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L747] 2 z$r_buff0_thd2 = weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) [L748] EXPR 2 weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L748] 2 z$r_buff1_thd2 = weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L749] 2 __unbuffered_p1_EAX = z VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L750] EXPR 2 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L794] 0 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L795] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L750] 2 z = z$flush_delayed ? z$mem_tmp : z [L751] 2 z$flush_delayed = (_Bool)0 [L756] 2 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L795] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L796] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L796] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L797] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L797] 0 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L798] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L798] 0 z$r_buff1_thd3 = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 [L801] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L823] -1 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] EXPR -1 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] -1 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L828] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] -1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L829] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] -1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L830] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L830] -1 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L831] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L831] -1 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L834] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 1 && __unbuffered_p0_EBX == 0 && __unbuffered_p1_EAX == 0 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 0) VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 7 procedures, 305 locations, 3 error locations. UNSAFE Result, 369.8s OverallTime, 31 OverallIterations, 1 TraceHistogramMax, 50.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 12103 SDtfs, 15112 SDslu, 37284 SDs, 0 SdLazy, 11547 SolverSat, 524 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 8.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 352 GetRequests, 95 SyntacticMatches, 15 SemanticMatches, 242 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 468 ImplicationChecksByTransitivity, 2.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=445147occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 114.8s AutomataMinimizationTime, 30 MinimizatonAttempts, 676599 StatesRemovedByMinimization, 27 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.4s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 2.2s InterpolantComputationTime, 2943 NumberOfCodeBlocks, 2943 NumberOfCodeBlocksAsserted, 31 NumberOfCheckSat, 2800 ConstructedInterpolants, 0 QuantifiedInterpolants, 711410 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 30 InterpolantComputations, 30 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...