./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix031_pso.oepc_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix031_pso.oepc_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6024798e59ce0f0a3cb69b9d88eac58b24078872 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 03:15:56,801 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 03:15:56,802 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 03:15:56,808 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 03:15:56,808 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 03:15:56,809 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 03:15:56,810 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 03:15:56,811 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 03:15:56,812 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 03:15:56,813 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 03:15:56,813 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 03:15:56,813 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 03:15:56,814 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 03:15:56,815 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 03:15:56,815 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 03:15:56,816 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 03:15:56,816 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 03:15:56,818 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 03:15:56,819 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 03:15:56,820 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 03:15:56,820 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 03:15:56,821 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 03:15:56,823 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 03:15:56,823 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 03:15:56,823 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 03:15:56,824 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 03:15:56,824 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 03:15:56,824 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 03:15:56,825 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 03:15:56,825 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 03:15:56,826 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 03:15:56,826 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 03:15:56,826 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 03:15:56,826 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 03:15:56,827 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 03:15:56,827 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 03:15:56,827 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-23 03:15:56,834 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 03:15:56,834 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 03:15:56,835 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 03:15:56,835 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 03:15:56,836 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 03:15:56,836 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 03:15:56,836 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 03:15:56,836 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 03:15:56,836 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 03:15:56,836 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 03:15:56,837 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 03:15:56,837 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 03:15:56,837 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 03:15:56,837 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 03:15:56,837 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 03:15:56,837 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 03:15:56,837 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 03:15:56,837 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 03:15:56,838 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 03:15:56,838 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 03:15:56,838 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 03:15:56,838 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 03:15:56,838 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 03:15:56,838 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 03:15:56,838 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 03:15:56,839 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 03:15:56,839 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 03:15:56,839 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 03:15:56,839 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 03:15:56,839 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 03:15:56,839 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6024798e59ce0f0a3cb69b9d88eac58b24078872 [2018-11-23 03:15:56,865 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 03:15:56,875 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 03:15:56,878 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 03:15:56,879 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 03:15:56,879 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 03:15:56,880 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix031_pso.oepc_false-unreach-call.i [2018-11-23 03:15:56,926 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer/data/d112298c9/f6a0c5a59148442f8e981030c51f57b1/FLAG71a0aefbf [2018-11-23 03:15:57,303 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 03:15:57,303 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/sv-benchmarks/c/pthread-wmm/mix031_pso.oepc_false-unreach-call.i [2018-11-23 03:15:57,316 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer/data/d112298c9/f6a0c5a59148442f8e981030c51f57b1/FLAG71a0aefbf [2018-11-23 03:15:57,683 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer/data/d112298c9/f6a0c5a59148442f8e981030c51f57b1 [2018-11-23 03:15:57,685 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 03:15:57,687 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 03:15:57,687 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 03:15:57,687 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 03:15:57,690 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 03:15:57,691 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 03:15:57" (1/1) ... [2018-11-23 03:15:57,693 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@174bb65b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:57, skipping insertion in model container [2018-11-23 03:15:57,693 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 03:15:57" (1/1) ... [2018-11-23 03:15:57,700 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 03:15:57,732 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 03:15:57,971 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 03:15:57,981 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 03:15:58,078 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 03:15:58,124 INFO L195 MainTranslator]: Completed translation [2018-11-23 03:15:58,124 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:58 WrapperNode [2018-11-23 03:15:58,124 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 03:15:58,125 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 03:15:58,125 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 03:15:58,125 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 03:15:58,132 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:58" (1/1) ... [2018-11-23 03:15:58,146 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:58" (1/1) ... [2018-11-23 03:15:58,165 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 03:15:58,166 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 03:15:58,166 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 03:15:58,166 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 03:15:58,172 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:58" (1/1) ... [2018-11-23 03:15:58,172 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:58" (1/1) ... [2018-11-23 03:15:58,175 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:58" (1/1) ... [2018-11-23 03:15:58,175 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:58" (1/1) ... [2018-11-23 03:15:58,181 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:58" (1/1) ... [2018-11-23 03:15:58,183 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:58" (1/1) ... [2018-11-23 03:15:58,184 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:58" (1/1) ... [2018-11-23 03:15:58,186 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 03:15:58,187 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 03:15:58,187 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 03:15:58,187 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 03:15:58,187 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:58" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 03:15:58,220 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 03:15:58,220 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 03:15:58,220 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2018-11-23 03:15:58,220 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 03:15:58,220 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2018-11-23 03:15:58,220 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2018-11-23 03:15:58,220 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2018-11-23 03:15:58,221 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2018-11-23 03:15:58,221 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2018-11-23 03:15:58,221 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 03:15:58,221 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 03:15:58,222 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-23 03:15:58,637 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 03:15:58,637 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-23 03:15:58,638 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 03:15:58 BoogieIcfgContainer [2018-11-23 03:15:58,638 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 03:15:58,638 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 03:15:58,639 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 03:15:58,641 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 03:15:58,641 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 03:15:57" (1/3) ... [2018-11-23 03:15:58,642 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@98662bb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 03:15:58, skipping insertion in model container [2018-11-23 03:15:58,642 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:15:58" (2/3) ... [2018-11-23 03:15:58,642 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@98662bb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 03:15:58, skipping insertion in model container [2018-11-23 03:15:58,642 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 03:15:58" (3/3) ... [2018-11-23 03:15:58,644 INFO L112 eAbstractionObserver]: Analyzing ICFG mix031_pso.oepc_false-unreach-call.i [2018-11-23 03:15:58,670 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,670 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,670 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,670 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,670 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,671 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,671 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,671 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,671 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,671 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,672 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,672 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,672 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,672 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,672 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,672 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,672 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,673 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,673 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,673 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,673 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,673 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,673 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,673 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,673 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,674 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,674 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,674 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,674 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,674 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,674 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,674 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,675 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet9.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,675 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet9.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,675 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,675 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,675 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet9.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,675 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet9.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,676 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,676 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,676 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,676 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,676 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,676 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,676 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,676 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,677 WARN L317 ript$VariableManager]: TermVariabe Thread0_P1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,677 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,677 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,677 WARN L317 ript$VariableManager]: TermVariabe Thread0_P1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,677 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,677 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,677 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,678 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,678 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,678 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,678 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,678 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,678 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,678 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,679 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,679 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,679 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,679 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,679 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,679 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,679 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,679 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,680 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,680 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,680 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,680 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,680 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,680 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,680 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,681 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,681 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,681 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,681 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,681 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,681 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,681 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,682 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,682 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,682 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,682 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,682 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,682 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,682 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,683 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,683 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,683 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,683 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,683 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,683 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,683 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,683 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,684 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,684 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,684 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,684 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,684 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,684 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,684 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,685 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,685 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,685 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,685 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,685 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,685 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,685 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,685 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,686 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,686 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,686 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,686 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,686 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,686 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,686 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,687 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,687 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,687 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,687 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,687 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,687 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,687 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,688 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,688 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,688 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,688 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,688 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,688 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,688 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,688 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,689 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,689 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,689 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,689 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,689 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,689 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,689 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,689 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,690 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,690 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,690 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,690 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,690 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,690 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,690 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,690 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,691 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,691 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,691 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,691 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,691 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,691 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,691 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,691 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,692 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet39.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,692 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet39.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,692 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,692 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,692 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet39.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,692 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P1_#t~nondet39.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:15:58,699 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-23 03:15:58,699 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 03:15:58,704 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2018-11-23 03:15:58,718 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2018-11-23 03:15:58,733 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 03:15:58,733 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 03:15:58,733 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 03:15:58,734 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 03:15:58,734 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 03:15:58,734 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 03:15:58,734 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 03:15:58,734 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 03:15:58,734 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 03:15:58,741 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 146places, 184 transitions [2018-11-23 03:16:00,363 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 34810 states. [2018-11-23 03:16:00,365 INFO L276 IsEmpty]: Start isEmpty. Operand 34810 states. [2018-11-23 03:16:00,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-11-23 03:16:00,372 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:00,373 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:00,375 INFO L423 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:00,380 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:00,380 INFO L82 PathProgramCache]: Analyzing trace with hash 148401709, now seen corresponding path program 1 times [2018-11-23 03:16:00,382 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:00,382 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:00,421 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:00,421 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:00,421 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:00,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:00,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:00,567 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:00,567 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:16:00,570 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:16:00,578 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:16:00,579 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:16:00,581 INFO L87 Difference]: Start difference. First operand 34810 states. Second operand 4 states. [2018-11-23 03:16:01,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:01,404 INFO L93 Difference]: Finished difference Result 60794 states and 234497 transitions. [2018-11-23 03:16:01,404 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 03:16:01,405 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 37 [2018-11-23 03:16:01,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:01,625 INFO L225 Difference]: With dead ends: 60794 [2018-11-23 03:16:01,626 INFO L226 Difference]: Without dead ends: 44274 [2018-11-23 03:16:01,627 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:16:01,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44274 states. [2018-11-23 03:16:02,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44274 to 27342. [2018-11-23 03:16:02,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27342 states. [2018-11-23 03:16:02,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27342 states to 27342 states and 105503 transitions. [2018-11-23 03:16:02,700 INFO L78 Accepts]: Start accepts. Automaton has 27342 states and 105503 transitions. Word has length 37 [2018-11-23 03:16:02,700 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:02,701 INFO L480 AbstractCegarLoop]: Abstraction has 27342 states and 105503 transitions. [2018-11-23 03:16:02,701 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:16:02,701 INFO L276 IsEmpty]: Start isEmpty. Operand 27342 states and 105503 transitions. [2018-11-23 03:16:02,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-23 03:16:02,707 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:02,708 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:02,708 INFO L423 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:02,708 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:02,709 INFO L82 PathProgramCache]: Analyzing trace with hash -54930118, now seen corresponding path program 1 times [2018-11-23 03:16:02,709 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:02,709 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:02,712 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:02,713 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:02,713 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:02,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:02,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:02,776 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:02,776 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:16:02,778 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:16:02,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:16:02,778 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:16:02,778 INFO L87 Difference]: Start difference. First operand 27342 states and 105503 transitions. Second operand 4 states. [2018-11-23 03:16:02,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:02,937 INFO L93 Difference]: Finished difference Result 8532 states and 28348 transitions. [2018-11-23 03:16:02,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 03:16:02,938 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 49 [2018-11-23 03:16:02,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:02,971 INFO L225 Difference]: With dead ends: 8532 [2018-11-23 03:16:02,971 INFO L226 Difference]: Without dead ends: 7470 [2018-11-23 03:16:02,971 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:02,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7470 states. [2018-11-23 03:16:03,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7470 to 7470. [2018-11-23 03:16:03,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7470 states. [2018-11-23 03:16:03,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7470 states to 7470 states and 24640 transitions. [2018-11-23 03:16:03,097 INFO L78 Accepts]: Start accepts. Automaton has 7470 states and 24640 transitions. Word has length 49 [2018-11-23 03:16:03,097 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:03,097 INFO L480 AbstractCegarLoop]: Abstraction has 7470 states and 24640 transitions. [2018-11-23 03:16:03,098 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:16:03,098 INFO L276 IsEmpty]: Start isEmpty. Operand 7470 states and 24640 transitions. [2018-11-23 03:16:03,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-23 03:16:03,099 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:03,099 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:03,099 INFO L423 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:03,100 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:03,100 INFO L82 PathProgramCache]: Analyzing trace with hash -790300171, now seen corresponding path program 1 times [2018-11-23 03:16:03,100 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:03,100 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:03,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:03,104 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:03,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:03,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:03,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:03,163 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:03,163 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:16:03,164 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:16:03,164 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:16:03,164 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:03,164 INFO L87 Difference]: Start difference. First operand 7470 states and 24640 transitions. Second operand 5 states. [2018-11-23 03:16:03,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:03,439 INFO L93 Difference]: Finished difference Result 14002 states and 45809 transitions. [2018-11-23 03:16:03,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:16:03,440 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2018-11-23 03:16:03,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:03,484 INFO L225 Difference]: With dead ends: 14002 [2018-11-23 03:16:03,485 INFO L226 Difference]: Without dead ends: 13934 [2018-11-23 03:16:03,485 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:16:03,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13934 states. [2018-11-23 03:16:03,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13934 to 9445. [2018-11-23 03:16:03,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9445 states. [2018-11-23 03:16:03,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9445 states to 9445 states and 30546 transitions. [2018-11-23 03:16:03,844 INFO L78 Accepts]: Start accepts. Automaton has 9445 states and 30546 transitions. Word has length 50 [2018-11-23 03:16:03,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:03,845 INFO L480 AbstractCegarLoop]: Abstraction has 9445 states and 30546 transitions. [2018-11-23 03:16:03,846 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:16:03,846 INFO L276 IsEmpty]: Start isEmpty. Operand 9445 states and 30546 transitions. [2018-11-23 03:16:03,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-11-23 03:16:03,848 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:03,848 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:03,848 INFO L423 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:03,849 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:03,849 INFO L82 PathProgramCache]: Analyzing trace with hash 1702931131, now seen corresponding path program 1 times [2018-11-23 03:16:03,849 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:03,849 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:03,852 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:03,853 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:03,853 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:03,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:03,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:03,896 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:03,897 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 03:16:03,897 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 03:16:03,897 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 03:16:03,897 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:16:03,897 INFO L87 Difference]: Start difference. First operand 9445 states and 30546 transitions. Second operand 3 states. [2018-11-23 03:16:03,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:03,965 INFO L93 Difference]: Finished difference Result 13283 states and 42645 transitions. [2018-11-23 03:16:03,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 03:16:03,965 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 52 [2018-11-23 03:16:03,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:03,986 INFO L225 Difference]: With dead ends: 13283 [2018-11-23 03:16:03,986 INFO L226 Difference]: Without dead ends: 13283 [2018-11-23 03:16:03,987 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:16:04,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13283 states. [2018-11-23 03:16:04,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13283 to 9849. [2018-11-23 03:16:04,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9849 states. [2018-11-23 03:16:04,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9849 states to 9849 states and 31512 transitions. [2018-11-23 03:16:04,160 INFO L78 Accepts]: Start accepts. Automaton has 9849 states and 31512 transitions. Word has length 52 [2018-11-23 03:16:04,160 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:04,160 INFO L480 AbstractCegarLoop]: Abstraction has 9849 states and 31512 transitions. [2018-11-23 03:16:04,160 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 03:16:04,160 INFO L276 IsEmpty]: Start isEmpty. Operand 9849 states and 31512 transitions. [2018-11-23 03:16:04,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-23 03:16:04,161 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:04,161 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:04,162 INFO L423 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:04,162 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:04,162 INFO L82 PathProgramCache]: Analyzing trace with hash -1252831162, now seen corresponding path program 1 times [2018-11-23 03:16:04,162 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:04,162 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:04,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:04,164 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:04,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:04,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:04,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:04,245 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:04,246 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:16:04,246 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:16:04,246 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:16:04,246 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:16:04,246 INFO L87 Difference]: Start difference. First operand 9849 states and 31512 transitions. Second operand 6 states. [2018-11-23 03:16:04,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:04,551 INFO L93 Difference]: Finished difference Result 14207 states and 45068 transitions. [2018-11-23 03:16:04,552 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 03:16:04,552 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 56 [2018-11-23 03:16:04,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:04,569 INFO L225 Difference]: With dead ends: 14207 [2018-11-23 03:16:04,569 INFO L226 Difference]: Without dead ends: 14135 [2018-11-23 03:16:04,569 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2018-11-23 03:16:04,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14135 states. [2018-11-23 03:16:04,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14135 to 10853. [2018-11-23 03:16:04,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10853 states. [2018-11-23 03:16:04,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10853 states to 10853 states and 34567 transitions. [2018-11-23 03:16:04,695 INFO L78 Accepts]: Start accepts. Automaton has 10853 states and 34567 transitions. Word has length 56 [2018-11-23 03:16:04,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:04,696 INFO L480 AbstractCegarLoop]: Abstraction has 10853 states and 34567 transitions. [2018-11-23 03:16:04,696 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:16:04,696 INFO L276 IsEmpty]: Start isEmpty. Operand 10853 states and 34567 transitions. [2018-11-23 03:16:04,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-23 03:16:04,700 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:04,700 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:04,700 INFO L423 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:04,701 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:04,701 INFO L82 PathProgramCache]: Analyzing trace with hash -575191646, now seen corresponding path program 1 times [2018-11-23 03:16:04,701 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:04,701 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:04,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:04,703 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:04,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:04,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:04,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:04,750 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:04,750 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:16:04,751 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:16:04,751 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:16:04,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:16:04,751 INFO L87 Difference]: Start difference. First operand 10853 states and 34567 transitions. Second operand 4 states. [2018-11-23 03:16:04,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:04,841 INFO L93 Difference]: Finished difference Result 12400 states and 39576 transitions. [2018-11-23 03:16:04,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 03:16:04,841 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 64 [2018-11-23 03:16:04,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:04,856 INFO L225 Difference]: With dead ends: 12400 [2018-11-23 03:16:04,856 INFO L226 Difference]: Without dead ends: 12400 [2018-11-23 03:16:04,856 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:04,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12400 states. [2018-11-23 03:16:05,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12400 to 11373. [2018-11-23 03:16:05,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11373 states. [2018-11-23 03:16:05,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11373 states to 11373 states and 36240 transitions. [2018-11-23 03:16:05,046 INFO L78 Accepts]: Start accepts. Automaton has 11373 states and 36240 transitions. Word has length 64 [2018-11-23 03:16:05,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:05,046 INFO L480 AbstractCegarLoop]: Abstraction has 11373 states and 36240 transitions. [2018-11-23 03:16:05,046 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:16:05,046 INFO L276 IsEmpty]: Start isEmpty. Operand 11373 states and 36240 transitions. [2018-11-23 03:16:05,050 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-23 03:16:05,050 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:05,050 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:05,050 INFO L423 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:05,050 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:05,050 INFO L82 PathProgramCache]: Analyzing trace with hash 1167618689, now seen corresponding path program 1 times [2018-11-23 03:16:05,051 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:05,051 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:05,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:05,052 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:05,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:05,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:05,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:05,125 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:05,125 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:16:05,126 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:16:05,126 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:16:05,126 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:16:05,126 INFO L87 Difference]: Start difference. First operand 11373 states and 36240 transitions. Second operand 6 states. [2018-11-23 03:16:05,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:05,466 INFO L93 Difference]: Finished difference Result 20973 states and 66490 transitions. [2018-11-23 03:16:05,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 03:16:05,466 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 64 [2018-11-23 03:16:05,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:05,490 INFO L225 Difference]: With dead ends: 20973 [2018-11-23 03:16:05,490 INFO L226 Difference]: Without dead ends: 20902 [2018-11-23 03:16:05,490 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2018-11-23 03:16:05,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20902 states. [2018-11-23 03:16:05,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20902 to 13759. [2018-11-23 03:16:05,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13759 states. [2018-11-23 03:16:05,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13759 states to 13759 states and 43284 transitions. [2018-11-23 03:16:05,664 INFO L78 Accepts]: Start accepts. Automaton has 13759 states and 43284 transitions. Word has length 64 [2018-11-23 03:16:05,664 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:05,664 INFO L480 AbstractCegarLoop]: Abstraction has 13759 states and 43284 transitions. [2018-11-23 03:16:05,664 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:16:05,664 INFO L276 IsEmpty]: Start isEmpty. Operand 13759 states and 43284 transitions. [2018-11-23 03:16:05,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-23 03:16:05,668 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:05,668 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:05,668 INFO L423 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:05,669 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:05,669 INFO L82 PathProgramCache]: Analyzing trace with hash 1129581006, now seen corresponding path program 1 times [2018-11-23 03:16:05,669 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:05,669 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:05,670 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:05,670 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:05,670 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:05,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:05,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:05,739 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:05,739 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:16:05,739 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:16:05,739 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:16:05,739 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:16:05,740 INFO L87 Difference]: Start difference. First operand 13759 states and 43284 transitions. Second operand 4 states. [2018-11-23 03:16:05,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:05,926 INFO L93 Difference]: Finished difference Result 17639 states and 54589 transitions. [2018-11-23 03:16:05,926 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 03:16:05,926 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 68 [2018-11-23 03:16:05,927 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:05,946 INFO L225 Difference]: With dead ends: 17639 [2018-11-23 03:16:05,946 INFO L226 Difference]: Without dead ends: 17639 [2018-11-23 03:16:05,946 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:16:05,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17639 states. [2018-11-23 03:16:06,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17639 to 15797. [2018-11-23 03:16:06,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15797 states. [2018-11-23 03:16:06,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15797 states to 15797 states and 49135 transitions. [2018-11-23 03:16:06,115 INFO L78 Accepts]: Start accepts. Automaton has 15797 states and 49135 transitions. Word has length 68 [2018-11-23 03:16:06,116 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:06,116 INFO L480 AbstractCegarLoop]: Abstraction has 15797 states and 49135 transitions. [2018-11-23 03:16:06,116 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:16:06,116 INFO L276 IsEmpty]: Start isEmpty. Operand 15797 states and 49135 transitions. [2018-11-23 03:16:06,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-23 03:16:06,120 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:06,120 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:06,120 INFO L423 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:06,121 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:06,121 INFO L82 PathProgramCache]: Analyzing trace with hash -947628337, now seen corresponding path program 1 times [2018-11-23 03:16:06,121 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:06,121 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:06,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:06,122 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:06,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:06,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:06,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:06,156 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:06,156 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 03:16:06,156 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 03:16:06,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 03:16:06,156 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:16:06,156 INFO L87 Difference]: Start difference. First operand 15797 states and 49135 transitions. Second operand 3 states. [2018-11-23 03:16:06,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:06,325 INFO L93 Difference]: Finished difference Result 16389 states and 50742 transitions. [2018-11-23 03:16:06,325 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 03:16:06,325 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2018-11-23 03:16:06,326 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:06,344 INFO L225 Difference]: With dead ends: 16389 [2018-11-23 03:16:06,345 INFO L226 Difference]: Without dead ends: 16389 [2018-11-23 03:16:06,345 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:16:06,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16389 states. [2018-11-23 03:16:06,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16389 to 16113. [2018-11-23 03:16:06,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16113 states. [2018-11-23 03:16:06,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16113 states to 16113 states and 49985 transitions. [2018-11-23 03:16:06,524 INFO L78 Accepts]: Start accepts. Automaton has 16113 states and 49985 transitions. Word has length 68 [2018-11-23 03:16:06,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:06,524 INFO L480 AbstractCegarLoop]: Abstraction has 16113 states and 49985 transitions. [2018-11-23 03:16:06,524 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 03:16:06,524 INFO L276 IsEmpty]: Start isEmpty. Operand 16113 states and 49985 transitions. [2018-11-23 03:16:06,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 03:16:06,531 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:06,532 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:06,532 INFO L423 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:06,532 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:06,532 INFO L82 PathProgramCache]: Analyzing trace with hash -1412859306, now seen corresponding path program 1 times [2018-11-23 03:16:06,532 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:06,532 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:06,534 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:06,534 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:06,534 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:06,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:06,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:06,616 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:06,616 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:16:06,616 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:16:06,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:16:06,617 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:16:06,617 INFO L87 Difference]: Start difference. First operand 16113 states and 49985 transitions. Second operand 6 states. [2018-11-23 03:16:07,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:07,263 INFO L93 Difference]: Finished difference Result 19825 states and 60441 transitions. [2018-11-23 03:16:07,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:16:07,263 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 70 [2018-11-23 03:16:07,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:07,285 INFO L225 Difference]: With dead ends: 19825 [2018-11-23 03:16:07,285 INFO L226 Difference]: Without dead ends: 19825 [2018-11-23 03:16:07,285 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:16:07,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19825 states. [2018-11-23 03:16:07,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19825 to 18621. [2018-11-23 03:16:07,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18621 states. [2018-11-23 03:16:07,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18621 states to 18621 states and 57221 transitions. [2018-11-23 03:16:07,469 INFO L78 Accepts]: Start accepts. Automaton has 18621 states and 57221 transitions. Word has length 70 [2018-11-23 03:16:07,469 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:07,469 INFO L480 AbstractCegarLoop]: Abstraction has 18621 states and 57221 transitions. [2018-11-23 03:16:07,469 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:16:07,469 INFO L276 IsEmpty]: Start isEmpty. Operand 18621 states and 57221 transitions. [2018-11-23 03:16:07,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 03:16:07,477 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:07,477 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:07,477 INFO L423 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:07,477 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:07,477 INFO L82 PathProgramCache]: Analyzing trace with hash 804898647, now seen corresponding path program 1 times [2018-11-23 03:16:07,477 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:07,477 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:07,478 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:07,478 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:07,479 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:07,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:07,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:07,560 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:07,560 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:16:07,561 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:16:07,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:16:07,561 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:07,561 INFO L87 Difference]: Start difference. First operand 18621 states and 57221 transitions. Second operand 5 states. [2018-11-23 03:16:07,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:07,836 INFO L93 Difference]: Finished difference Result 24184 states and 73726 transitions. [2018-11-23 03:16:07,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:16:07,836 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 70 [2018-11-23 03:16:07,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:07,870 INFO L225 Difference]: With dead ends: 24184 [2018-11-23 03:16:07,870 INFO L226 Difference]: Without dead ends: 24184 [2018-11-23 03:16:07,871 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:16:07,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24184 states. [2018-11-23 03:16:08,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24184 to 22021. [2018-11-23 03:16:08,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22021 states. [2018-11-23 03:16:08,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22021 states to 22021 states and 67146 transitions. [2018-11-23 03:16:08,108 INFO L78 Accepts]: Start accepts. Automaton has 22021 states and 67146 transitions. Word has length 70 [2018-11-23 03:16:08,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:08,108 INFO L480 AbstractCegarLoop]: Abstraction has 22021 states and 67146 transitions. [2018-11-23 03:16:08,108 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:16:08,108 INFO L276 IsEmpty]: Start isEmpty. Operand 22021 states and 67146 transitions. [2018-11-23 03:16:08,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 03:16:08,116 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:08,116 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:08,116 INFO L423 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:08,116 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:08,117 INFO L82 PathProgramCache]: Analyzing trace with hash 294364470, now seen corresponding path program 1 times [2018-11-23 03:16:08,117 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:08,117 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:08,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:08,118 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:08,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:08,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:08,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:08,207 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:08,207 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:16:08,207 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:16:08,207 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:16:08,207 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:08,208 INFO L87 Difference]: Start difference. First operand 22021 states and 67146 transitions. Second operand 5 states. [2018-11-23 03:16:08,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:08,588 INFO L93 Difference]: Finished difference Result 30767 states and 92772 transitions. [2018-11-23 03:16:08,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:16:08,588 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 70 [2018-11-23 03:16:08,589 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:08,625 INFO L225 Difference]: With dead ends: 30767 [2018-11-23 03:16:08,625 INFO L226 Difference]: Without dead ends: 30767 [2018-11-23 03:16:08,625 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:16:08,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30767 states. [2018-11-23 03:16:08,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30767 to 27531. [2018-11-23 03:16:08,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27531 states. [2018-11-23 03:16:08,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27531 states to 27531 states and 83463 transitions. [2018-11-23 03:16:08,986 INFO L78 Accepts]: Start accepts. Automaton has 27531 states and 83463 transitions. Word has length 70 [2018-11-23 03:16:08,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:08,986 INFO L480 AbstractCegarLoop]: Abstraction has 27531 states and 83463 transitions. [2018-11-23 03:16:08,986 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:16:08,986 INFO L276 IsEmpty]: Start isEmpty. Operand 27531 states and 83463 transitions. [2018-11-23 03:16:08,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 03:16:08,994 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:08,994 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:08,994 INFO L423 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:08,994 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:08,995 INFO L82 PathProgramCache]: Analyzing trace with hash -1513089993, now seen corresponding path program 1 times [2018-11-23 03:16:08,995 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:08,995 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:08,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:08,996 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:08,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:09,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:09,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:09,038 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:09,038 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:16:09,038 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:16:09,038 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:16:09,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:16:09,038 INFO L87 Difference]: Start difference. First operand 27531 states and 83463 transitions. Second operand 4 states. [2018-11-23 03:16:09,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:09,398 INFO L93 Difference]: Finished difference Result 37927 states and 115324 transitions. [2018-11-23 03:16:09,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 03:16:09,398 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 70 [2018-11-23 03:16:09,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:09,442 INFO L225 Difference]: With dead ends: 37927 [2018-11-23 03:16:09,442 INFO L226 Difference]: Without dead ends: 37711 [2018-11-23 03:16:09,443 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:09,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37711 states. [2018-11-23 03:16:09,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37711 to 34931. [2018-11-23 03:16:09,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34931 states. [2018-11-23 03:16:09,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34931 states to 34931 states and 106353 transitions. [2018-11-23 03:16:09,826 INFO L78 Accepts]: Start accepts. Automaton has 34931 states and 106353 transitions. Word has length 70 [2018-11-23 03:16:09,826 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:09,826 INFO L480 AbstractCegarLoop]: Abstraction has 34931 states and 106353 transitions. [2018-11-23 03:16:09,826 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:16:09,826 INFO L276 IsEmpty]: Start isEmpty. Operand 34931 states and 106353 transitions. [2018-11-23 03:16:09,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 03:16:09,835 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:09,835 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:09,836 INFO L423 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:09,836 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:09,836 INFO L82 PathProgramCache]: Analyzing trace with hash 984925944, now seen corresponding path program 1 times [2018-11-23 03:16:09,836 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:09,836 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:09,837 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:09,838 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:09,838 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:09,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:09,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:09,951 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:09,951 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:16:09,952 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:16:09,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:16:09,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:16:09,952 INFO L87 Difference]: Start difference. First operand 34931 states and 106353 transitions. Second operand 7 states. [2018-11-23 03:16:10,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:10,262 INFO L93 Difference]: Finished difference Result 30943 states and 89976 transitions. [2018-11-23 03:16:10,262 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 03:16:10,262 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 70 [2018-11-23 03:16:10,262 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:10,295 INFO L225 Difference]: With dead ends: 30943 [2018-11-23 03:16:10,295 INFO L226 Difference]: Without dead ends: 30943 [2018-11-23 03:16:10,295 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=87, Unknown=0, NotChecked=0, Total=132 [2018-11-23 03:16:10,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30943 states. [2018-11-23 03:16:10,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30943 to 25023. [2018-11-23 03:16:10,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25023 states. [2018-11-23 03:16:10,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25023 states to 25023 states and 72808 transitions. [2018-11-23 03:16:10,621 INFO L78 Accepts]: Start accepts. Automaton has 25023 states and 72808 transitions. Word has length 70 [2018-11-23 03:16:10,621 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:10,621 INFO L480 AbstractCegarLoop]: Abstraction has 25023 states and 72808 transitions. [2018-11-23 03:16:10,621 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:16:10,621 INFO L276 IsEmpty]: Start isEmpty. Operand 25023 states and 72808 transitions. [2018-11-23 03:16:10,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 03:16:10,630 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:10,630 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:10,631 INFO L423 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:10,631 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:10,631 INFO L82 PathProgramCache]: Analyzing trace with hash 1872429625, now seen corresponding path program 1 times [2018-11-23 03:16:10,631 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:10,631 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:10,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:10,632 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:10,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:10,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:10,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:10,696 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:10,696 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:16:10,697 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:16:10,697 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:16:10,697 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:10,697 INFO L87 Difference]: Start difference. First operand 25023 states and 72808 transitions. Second operand 5 states. [2018-11-23 03:16:10,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:10,739 INFO L93 Difference]: Finished difference Result 7111 states and 17702 transitions. [2018-11-23 03:16:10,740 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 03:16:10,740 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 70 [2018-11-23 03:16:10,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:10,746 INFO L225 Difference]: With dead ends: 7111 [2018-11-23 03:16:10,746 INFO L226 Difference]: Without dead ends: 5778 [2018-11-23 03:16:10,746 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:16:10,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5778 states. [2018-11-23 03:16:10,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5778 to 5211. [2018-11-23 03:16:10,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5211 states. [2018-11-23 03:16:10,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5211 states to 5211 states and 12576 transitions. [2018-11-23 03:16:10,853 INFO L78 Accepts]: Start accepts. Automaton has 5211 states and 12576 transitions. Word has length 70 [2018-11-23 03:16:10,854 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:10,854 INFO L480 AbstractCegarLoop]: Abstraction has 5211 states and 12576 transitions. [2018-11-23 03:16:10,854 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:16:10,854 INFO L276 IsEmpty]: Start isEmpty. Operand 5211 states and 12576 transitions. [2018-11-23 03:16:10,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 03:16:10,858 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:10,858 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:10,859 INFO L423 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:10,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:10,859 INFO L82 PathProgramCache]: Analyzing trace with hash -173742318, now seen corresponding path program 1 times [2018-11-23 03:16:10,859 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:10,859 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:10,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:10,860 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:10,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:10,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:10,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:10,876 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:10,876 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 03:16:10,876 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 03:16:10,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 03:16:10,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:16:10,877 INFO L87 Difference]: Start difference. First operand 5211 states and 12576 transitions. Second operand 3 states. [2018-11-23 03:16:10,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:10,905 INFO L93 Difference]: Finished difference Result 6743 states and 16083 transitions. [2018-11-23 03:16:10,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 03:16:10,906 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2018-11-23 03:16:10,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:10,911 INFO L225 Difference]: With dead ends: 6743 [2018-11-23 03:16:10,911 INFO L226 Difference]: Without dead ends: 6743 [2018-11-23 03:16:10,911 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 03:16:10,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6743 states. [2018-11-23 03:16:10,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6743 to 5112. [2018-11-23 03:16:10,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5112 states. [2018-11-23 03:16:10,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5112 states to 5112 states and 12061 transitions. [2018-11-23 03:16:10,953 INFO L78 Accepts]: Start accepts. Automaton has 5112 states and 12061 transitions. Word has length 70 [2018-11-23 03:16:10,953 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:10,953 INFO L480 AbstractCegarLoop]: Abstraction has 5112 states and 12061 transitions. [2018-11-23 03:16:10,953 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 03:16:10,953 INFO L276 IsEmpty]: Start isEmpty. Operand 5112 states and 12061 transitions. [2018-11-23 03:16:10,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-23 03:16:10,957 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:10,957 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:10,958 INFO L423 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:10,958 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:10,958 INFO L82 PathProgramCache]: Analyzing trace with hash 536084869, now seen corresponding path program 1 times [2018-11-23 03:16:10,958 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:10,958 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:10,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:10,959 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:10,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:10,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:11,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:11,014 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:11,014 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:16:11,014 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:16:11,014 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:16:11,014 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:11,015 INFO L87 Difference]: Start difference. First operand 5112 states and 12061 transitions. Second operand 5 states. [2018-11-23 03:16:11,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:11,124 INFO L93 Difference]: Finished difference Result 6146 states and 14511 transitions. [2018-11-23 03:16:11,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 03:16:11,125 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 76 [2018-11-23 03:16:11,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:11,130 INFO L225 Difference]: With dead ends: 6146 [2018-11-23 03:16:11,130 INFO L226 Difference]: Without dead ends: 6146 [2018-11-23 03:16:11,130 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-23 03:16:11,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6146 states. [2018-11-23 03:16:11,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6146 to 5590. [2018-11-23 03:16:11,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5590 states. [2018-11-23 03:16:11,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5590 states to 5590 states and 13219 transitions. [2018-11-23 03:16:11,175 INFO L78 Accepts]: Start accepts. Automaton has 5590 states and 13219 transitions. Word has length 76 [2018-11-23 03:16:11,176 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:11,176 INFO L480 AbstractCegarLoop]: Abstraction has 5590 states and 13219 transitions. [2018-11-23 03:16:11,176 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:16:11,176 INFO L276 IsEmpty]: Start isEmpty. Operand 5590 states and 13219 transitions. [2018-11-23 03:16:11,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-23 03:16:11,180 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:11,180 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:11,180 INFO L423 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:11,180 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:11,180 INFO L82 PathProgramCache]: Analyzing trace with hash -2016072092, now seen corresponding path program 1 times [2018-11-23 03:16:11,181 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:11,181 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:11,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:11,182 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:11,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:11,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:11,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:11,241 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:11,241 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:16:11,241 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:16:11,242 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:16:11,242 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:16:11,242 INFO L87 Difference]: Start difference. First operand 5590 states and 13219 transitions. Second operand 7 states. [2018-11-23 03:16:11,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:11,483 INFO L93 Difference]: Finished difference Result 6317 states and 14770 transitions. [2018-11-23 03:16:11,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 03:16:11,483 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 76 [2018-11-23 03:16:11,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:11,488 INFO L225 Difference]: With dead ends: 6317 [2018-11-23 03:16:11,488 INFO L226 Difference]: Without dead ends: 6215 [2018-11-23 03:16:11,488 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=211, Unknown=0, NotChecked=0, Total=272 [2018-11-23 03:16:11,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6215 states. [2018-11-23 03:16:11,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6215 to 5600. [2018-11-23 03:16:11,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5600 states. [2018-11-23 03:16:11,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5600 states to 5600 states and 13149 transitions. [2018-11-23 03:16:11,533 INFO L78 Accepts]: Start accepts. Automaton has 5600 states and 13149 transitions. Word has length 76 [2018-11-23 03:16:11,533 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:11,533 INFO L480 AbstractCegarLoop]: Abstraction has 5600 states and 13149 transitions. [2018-11-23 03:16:11,533 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:16:11,533 INFO L276 IsEmpty]: Start isEmpty. Operand 5600 states and 13149 transitions. [2018-11-23 03:16:11,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-23 03:16:11,538 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:11,538 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:11,538 INFO L423 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:11,538 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:11,538 INFO L82 PathProgramCache]: Analyzing trace with hash -321575746, now seen corresponding path program 1 times [2018-11-23 03:16:11,538 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:11,538 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:11,539 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:11,540 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:11,540 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:11,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:11,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:11,611 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:11,611 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:16:11,611 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:16:11,611 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:16:11,611 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:16:11,611 INFO L87 Difference]: Start difference. First operand 5600 states and 13149 transitions. Second operand 7 states. [2018-11-23 03:16:11,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:11,952 INFO L93 Difference]: Finished difference Result 6817 states and 16126 transitions. [2018-11-23 03:16:11,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:16:11,952 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 97 [2018-11-23 03:16:11,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:11,957 INFO L225 Difference]: With dead ends: 6817 [2018-11-23 03:16:11,957 INFO L226 Difference]: Without dead ends: 6817 [2018-11-23 03:16:11,957 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:16:11,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6817 states. [2018-11-23 03:16:11,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6817 to 5783. [2018-11-23 03:16:11,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5783 states. [2018-11-23 03:16:12,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5783 states to 5783 states and 13733 transitions. [2018-11-23 03:16:12,002 INFO L78 Accepts]: Start accepts. Automaton has 5783 states and 13733 transitions. Word has length 97 [2018-11-23 03:16:12,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:12,003 INFO L480 AbstractCegarLoop]: Abstraction has 5783 states and 13733 transitions. [2018-11-23 03:16:12,003 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:16:12,003 INFO L276 IsEmpty]: Start isEmpty. Operand 5783 states and 13733 transitions. [2018-11-23 03:16:12,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-23 03:16:12,007 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:12,007 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:12,007 INFO L423 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:12,007 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:12,007 INFO L82 PathProgramCache]: Analyzing trace with hash 1424496976, now seen corresponding path program 1 times [2018-11-23 03:16:12,007 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:12,007 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:12,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:12,008 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:12,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:12,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:12,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:12,069 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:12,069 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:16:12,069 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:16:12,070 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:16:12,070 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:16:12,070 INFO L87 Difference]: Start difference. First operand 5783 states and 13733 transitions. Second operand 4 states. [2018-11-23 03:16:12,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:12,131 INFO L93 Difference]: Finished difference Result 6884 states and 16093 transitions. [2018-11-23 03:16:12,132 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 03:16:12,132 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 97 [2018-11-23 03:16:12,132 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:12,138 INFO L225 Difference]: With dead ends: 6884 [2018-11-23 03:16:12,138 INFO L226 Difference]: Without dead ends: 6884 [2018-11-23 03:16:12,139 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:12,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6884 states. [2018-11-23 03:16:12,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6884 to 6235. [2018-11-23 03:16:12,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6235 states. [2018-11-23 03:16:12,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6235 states to 6235 states and 14671 transitions. [2018-11-23 03:16:12,189 INFO L78 Accepts]: Start accepts. Automaton has 6235 states and 14671 transitions. Word has length 97 [2018-11-23 03:16:12,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:12,189 INFO L480 AbstractCegarLoop]: Abstraction has 6235 states and 14671 transitions. [2018-11-23 03:16:12,190 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:16:12,190 INFO L276 IsEmpty]: Start isEmpty. Operand 6235 states and 14671 transitions. [2018-11-23 03:16:12,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-11-23 03:16:12,194 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:12,194 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:12,194 INFO L423 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:12,194 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:12,194 INFO L82 PathProgramCache]: Analyzing trace with hash 1324645014, now seen corresponding path program 1 times [2018-11-23 03:16:12,194 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:12,194 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:12,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:12,196 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:12,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:12,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:12,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:12,264 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:12,265 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:16:12,265 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:16:12,265 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:16:12,265 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:12,265 INFO L87 Difference]: Start difference. First operand 6235 states and 14671 transitions. Second operand 5 states. [2018-11-23 03:16:12,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:12,371 INFO L93 Difference]: Finished difference Result 6821 states and 15986 transitions. [2018-11-23 03:16:12,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:16:12,371 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 99 [2018-11-23 03:16:12,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:12,375 INFO L225 Difference]: With dead ends: 6821 [2018-11-23 03:16:12,375 INFO L226 Difference]: Without dead ends: 6821 [2018-11-23 03:16:12,376 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:16:12,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6821 states. [2018-11-23 03:16:12,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6821 to 5265. [2018-11-23 03:16:12,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5265 states. [2018-11-23 03:16:12,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5265 states to 5265 states and 12335 transitions. [2018-11-23 03:16:12,416 INFO L78 Accepts]: Start accepts. Automaton has 5265 states and 12335 transitions. Word has length 99 [2018-11-23 03:16:12,416 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:12,416 INFO L480 AbstractCegarLoop]: Abstraction has 5265 states and 12335 transitions. [2018-11-23 03:16:12,416 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:16:12,416 INFO L276 IsEmpty]: Start isEmpty. Operand 5265 states and 12335 transitions. [2018-11-23 03:16:12,422 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-11-23 03:16:12,422 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:12,422 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:12,422 INFO L423 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:12,422 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:12,422 INFO L82 PathProgramCache]: Analyzing trace with hash 1335961141, now seen corresponding path program 1 times [2018-11-23 03:16:12,422 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:12,423 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:12,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:12,424 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:12,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:12,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:12,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:12,476 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:12,476 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 03:16:12,476 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 03:16:12,476 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 03:16:12,476 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 03:16:12,477 INFO L87 Difference]: Start difference. First operand 5265 states and 12335 transitions. Second operand 4 states. [2018-11-23 03:16:12,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:12,602 INFO L93 Difference]: Finished difference Result 6800 states and 15876 transitions. [2018-11-23 03:16:12,602 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 03:16:12,602 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 99 [2018-11-23 03:16:12,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:12,607 INFO L225 Difference]: With dead ends: 6800 [2018-11-23 03:16:12,607 INFO L226 Difference]: Without dead ends: 6739 [2018-11-23 03:16:12,607 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:12,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6739 states. [2018-11-23 03:16:12,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6739 to 6337. [2018-11-23 03:16:12,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6337 states. [2018-11-23 03:16:12,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6337 states to 6337 states and 14856 transitions. [2018-11-23 03:16:12,654 INFO L78 Accepts]: Start accepts. Automaton has 6337 states and 14856 transitions. Word has length 99 [2018-11-23 03:16:12,654 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:12,654 INFO L480 AbstractCegarLoop]: Abstraction has 6337 states and 14856 transitions. [2018-11-23 03:16:12,654 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 03:16:12,654 INFO L276 IsEmpty]: Start isEmpty. Operand 6337 states and 14856 transitions. [2018-11-23 03:16:12,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-11-23 03:16:12,658 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:12,658 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:12,658 INFO L423 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:12,659 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:12,659 INFO L82 PathProgramCache]: Analyzing trace with hash -741248202, now seen corresponding path program 1 times [2018-11-23 03:16:12,659 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:12,659 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:12,659 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:12,660 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:12,660 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:12,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:12,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:12,751 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:12,751 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 03:16:12,752 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 03:16:12,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 03:16:12,752 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:16:12,752 INFO L87 Difference]: Start difference. First operand 6337 states and 14856 transitions. Second operand 7 states. [2018-11-23 03:16:12,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:12,843 INFO L93 Difference]: Finished difference Result 8083 states and 18867 transitions. [2018-11-23 03:16:12,844 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:16:12,844 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 99 [2018-11-23 03:16:12,844 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:12,849 INFO L225 Difference]: With dead ends: 8083 [2018-11-23 03:16:12,849 INFO L226 Difference]: Without dead ends: 8083 [2018-11-23 03:16:12,849 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-11-23 03:16:12,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8083 states. [2018-11-23 03:16:12,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8083 to 6105. [2018-11-23 03:16:12,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6105 states. [2018-11-23 03:16:12,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6105 states to 6105 states and 14166 transitions. [2018-11-23 03:16:12,897 INFO L78 Accepts]: Start accepts. Automaton has 6105 states and 14166 transitions. Word has length 99 [2018-11-23 03:16:12,897 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:12,897 INFO L480 AbstractCegarLoop]: Abstraction has 6105 states and 14166 transitions. [2018-11-23 03:16:12,897 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 03:16:12,897 INFO L276 IsEmpty]: Start isEmpty. Operand 6105 states and 14166 transitions. [2018-11-23 03:16:12,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-11-23 03:16:12,901 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:12,901 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:12,902 INFO L423 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:12,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:12,902 INFO L82 PathProgramCache]: Analyzing trace with hash -529897289, now seen corresponding path program 1 times [2018-11-23 03:16:12,902 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:12,902 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:12,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:12,903 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:12,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:12,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:12,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:12,969 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:12,969 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:16:12,969 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:16:12,969 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:16:12,969 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:12,969 INFO L87 Difference]: Start difference. First operand 6105 states and 14166 transitions. Second operand 5 states. [2018-11-23 03:16:12,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:12,996 INFO L93 Difference]: Finished difference Result 6105 states and 14150 transitions. [2018-11-23 03:16:12,997 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 03:16:12,997 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 99 [2018-11-23 03:16:12,997 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:13,001 INFO L225 Difference]: With dead ends: 6105 [2018-11-23 03:16:13,001 INFO L226 Difference]: Without dead ends: 6105 [2018-11-23 03:16:13,001 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:16:13,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6105 states. [2018-11-23 03:16:13,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6105 to 5757. [2018-11-23 03:16:13,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5757 states. [2018-11-23 03:16:13,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5757 states to 5757 states and 13316 transitions. [2018-11-23 03:16:13,046 INFO L78 Accepts]: Start accepts. Automaton has 5757 states and 13316 transitions. Word has length 99 [2018-11-23 03:16:13,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:13,046 INFO L480 AbstractCegarLoop]: Abstraction has 5757 states and 13316 transitions. [2018-11-23 03:16:13,046 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:16:13,046 INFO L276 IsEmpty]: Start isEmpty. Operand 5757 states and 13316 transitions. [2018-11-23 03:16:13,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-11-23 03:16:13,052 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:13,052 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:13,052 INFO L423 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:13,052 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:13,052 INFO L82 PathProgramCache]: Analyzing trace with hash 357606392, now seen corresponding path program 1 times [2018-11-23 03:16:13,052 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:13,052 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:13,053 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:13,054 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:13,054 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:13,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:13,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:13,219 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:13,219 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-23 03:16:13,219 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 03:16:13,219 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 03:16:13,219 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-11-23 03:16:13,220 INFO L87 Difference]: Start difference. First operand 5757 states and 13316 transitions. Second operand 10 states. [2018-11-23 03:16:13,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:13,882 INFO L93 Difference]: Finished difference Result 8664 states and 19989 transitions. [2018-11-23 03:16:13,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 03:16:13,882 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 99 [2018-11-23 03:16:13,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:13,886 INFO L225 Difference]: With dead ends: 8664 [2018-11-23 03:16:13,886 INFO L226 Difference]: Without dead ends: 6420 [2018-11-23 03:16:13,886 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=61, Invalid=179, Unknown=0, NotChecked=0, Total=240 [2018-11-23 03:16:13,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6420 states. [2018-11-23 03:16:13,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6420 to 5890. [2018-11-23 03:16:13,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5890 states. [2018-11-23 03:16:13,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5890 states to 5890 states and 13589 transitions. [2018-11-23 03:16:13,926 INFO L78 Accepts]: Start accepts. Automaton has 5890 states and 13589 transitions. Word has length 99 [2018-11-23 03:16:13,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:13,926 INFO L480 AbstractCegarLoop]: Abstraction has 5890 states and 13589 transitions. [2018-11-23 03:16:13,926 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 03:16:13,927 INFO L276 IsEmpty]: Start isEmpty. Operand 5890 states and 13589 transitions. [2018-11-23 03:16:13,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-11-23 03:16:13,931 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:13,931 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:13,931 INFO L423 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:13,931 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:13,931 INFO L82 PathProgramCache]: Analyzing trace with hash 571332279, now seen corresponding path program 1 times [2018-11-23 03:16:13,931 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:13,932 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:13,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:13,933 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:13,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:13,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:14,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:14,008 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:14,008 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:16:14,009 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:16:14,009 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:16:14,009 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:16:14,009 INFO L87 Difference]: Start difference. First operand 5890 states and 13589 transitions. Second operand 6 states. [2018-11-23 03:16:14,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:14,106 INFO L93 Difference]: Finished difference Result 7234 states and 16172 transitions. [2018-11-23 03:16:14,107 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 03:16:14,107 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 99 [2018-11-23 03:16:14,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:14,112 INFO L225 Difference]: With dead ends: 7234 [2018-11-23 03:16:14,112 INFO L226 Difference]: Without dead ends: 7203 [2018-11-23 03:16:14,112 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-23 03:16:14,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7203 states. [2018-11-23 03:16:14,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7203 to 5897. [2018-11-23 03:16:14,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5897 states. [2018-11-23 03:16:14,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5897 states to 5897 states and 13285 transitions. [2018-11-23 03:16:14,160 INFO L78 Accepts]: Start accepts. Automaton has 5897 states and 13285 transitions. Word has length 99 [2018-11-23 03:16:14,160 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:14,160 INFO L480 AbstractCegarLoop]: Abstraction has 5897 states and 13285 transitions. [2018-11-23 03:16:14,160 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:16:14,160 INFO L276 IsEmpty]: Start isEmpty. Operand 5897 states and 13285 transitions. [2018-11-23 03:16:14,164 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-11-23 03:16:14,165 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:14,165 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:14,165 INFO L423 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:14,165 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:14,165 INFO L82 PathProgramCache]: Analyzing trace with hash 1679511564, now seen corresponding path program 1 times [2018-11-23 03:16:14,165 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:14,165 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:14,166 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:14,166 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:14,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:14,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:14,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:14,213 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:14,213 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:16:14,213 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:16:14,213 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:16:14,213 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:16:14,213 INFO L87 Difference]: Start difference. First operand 5897 states and 13285 transitions. Second operand 5 states. [2018-11-23 03:16:14,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:14,351 INFO L93 Difference]: Finished difference Result 6847 states and 15318 transitions. [2018-11-23 03:16:14,352 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:16:14,352 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 99 [2018-11-23 03:16:14,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:14,357 INFO L225 Difference]: With dead ends: 6847 [2018-11-23 03:16:14,357 INFO L226 Difference]: Without dead ends: 6781 [2018-11-23 03:16:14,358 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:16:14,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6781 states. [2018-11-23 03:16:14,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6781 to 5524. [2018-11-23 03:16:14,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5524 states. [2018-11-23 03:16:14,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5524 states to 5524 states and 12519 transitions. [2018-11-23 03:16:14,405 INFO L78 Accepts]: Start accepts. Automaton has 5524 states and 12519 transitions. Word has length 99 [2018-11-23 03:16:14,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:14,405 INFO L480 AbstractCegarLoop]: Abstraction has 5524 states and 12519 transitions. [2018-11-23 03:16:14,405 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:16:14,405 INFO L276 IsEmpty]: Start isEmpty. Operand 5524 states and 12519 transitions. [2018-11-23 03:16:14,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-11-23 03:16:14,409 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:14,409 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:14,410 INFO L423 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:14,410 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:14,410 INFO L82 PathProgramCache]: Analyzing trace with hash -1922354035, now seen corresponding path program 2 times [2018-11-23 03:16:14,410 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:14,410 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:14,411 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:14,411 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:16:14,411 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:14,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:14,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:14,471 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:14,472 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:16:14,472 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:16:14,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:16:14,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:16:14,472 INFO L87 Difference]: Start difference. First operand 5524 states and 12519 transitions. Second operand 6 states. [2018-11-23 03:16:14,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:14,579 INFO L93 Difference]: Finished difference Result 5976 states and 13438 transitions. [2018-11-23 03:16:14,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:16:14,580 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 99 [2018-11-23 03:16:14,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:14,584 INFO L225 Difference]: With dead ends: 5976 [2018-11-23 03:16:14,584 INFO L226 Difference]: Without dead ends: 5976 [2018-11-23 03:16:14,585 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:16:14,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5976 states. [2018-11-23 03:16:14,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5976 to 5689. [2018-11-23 03:16:14,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5689 states. [2018-11-23 03:16:14,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5689 states to 5689 states and 12814 transitions. [2018-11-23 03:16:14,625 INFO L78 Accepts]: Start accepts. Automaton has 5689 states and 12814 transitions. Word has length 99 [2018-11-23 03:16:14,625 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:14,625 INFO L480 AbstractCegarLoop]: Abstraction has 5689 states and 12814 transitions. [2018-11-23 03:16:14,625 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:16:14,625 INFO L276 IsEmpty]: Start isEmpty. Operand 5689 states and 12814 transitions. [2018-11-23 03:16:14,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-11-23 03:16:14,629 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:14,629 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:14,630 INFO L423 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:14,630 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:14,630 INFO L82 PathProgramCache]: Analyzing trace with hash 122635640, now seen corresponding path program 2 times [2018-11-23 03:16:14,630 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:14,630 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:14,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:14,631 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 03:16:14,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:14,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:14,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:14,739 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:14,739 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-23 03:16:14,739 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 03:16:14,739 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 03:16:14,739 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-11-23 03:16:14,740 INFO L87 Difference]: Start difference. First operand 5689 states and 12814 transitions. Second operand 9 states. [2018-11-23 03:16:14,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:14,842 INFO L93 Difference]: Finished difference Result 7272 states and 16362 transitions. [2018-11-23 03:16:14,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 03:16:14,842 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 99 [2018-11-23 03:16:14,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:14,846 INFO L225 Difference]: With dead ends: 7272 [2018-11-23 03:16:14,847 INFO L226 Difference]: Without dead ends: 5792 [2018-11-23 03:16:14,847 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=53, Invalid=103, Unknown=0, NotChecked=0, Total=156 [2018-11-23 03:16:14,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5792 states. [2018-11-23 03:16:14,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5792 to 5343. [2018-11-23 03:16:14,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5343 states. [2018-11-23 03:16:14,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5343 states to 5343 states and 12092 transitions. [2018-11-23 03:16:14,888 INFO L78 Accepts]: Start accepts. Automaton has 5343 states and 12092 transitions. Word has length 99 [2018-11-23 03:16:14,888 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:14,888 INFO L480 AbstractCegarLoop]: Abstraction has 5343 states and 12092 transitions. [2018-11-23 03:16:14,888 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 03:16:14,888 INFO L276 IsEmpty]: Start isEmpty. Operand 5343 states and 12092 transitions. [2018-11-23 03:16:14,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-11-23 03:16:14,893 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:14,893 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:14,893 INFO L423 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:14,893 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:14,893 INFO L82 PathProgramCache]: Analyzing trace with hash -1836332608, now seen corresponding path program 3 times [2018-11-23 03:16:14,893 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:14,893 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:14,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:14,894 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 03:16:14,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:14,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:15,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:15,016 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:15,016 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-23 03:16:15,016 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 03:16:15,016 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 03:16:15,016 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-11-23 03:16:15,017 INFO L87 Difference]: Start difference. First operand 5343 states and 12092 transitions. Second operand 10 states. [2018-11-23 03:16:15,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:15,453 INFO L93 Difference]: Finished difference Result 14141 states and 32221 transitions. [2018-11-23 03:16:15,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-23 03:16:15,454 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 99 [2018-11-23 03:16:15,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:15,457 INFO L225 Difference]: With dead ends: 14141 [2018-11-23 03:16:15,457 INFO L226 Difference]: Without dead ends: 4580 [2018-11-23 03:16:15,457 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 77 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=129, Invalid=377, Unknown=0, NotChecked=0, Total=506 [2018-11-23 03:16:15,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4580 states. [2018-11-23 03:16:15,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4580 to 3276. [2018-11-23 03:16:15,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3276 states. [2018-11-23 03:16:15,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3276 states to 3276 states and 7363 transitions. [2018-11-23 03:16:15,484 INFO L78 Accepts]: Start accepts. Automaton has 3276 states and 7363 transitions. Word has length 99 [2018-11-23 03:16:15,484 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:15,484 INFO L480 AbstractCegarLoop]: Abstraction has 3276 states and 7363 transitions. [2018-11-23 03:16:15,484 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 03:16:15,484 INFO L276 IsEmpty]: Start isEmpty. Operand 3276 states and 7363 transitions. [2018-11-23 03:16:15,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-11-23 03:16:15,486 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:15,486 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:15,487 INFO L423 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:15,487 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:15,487 INFO L82 PathProgramCache]: Analyzing trace with hash -2012018334, now seen corresponding path program 4 times [2018-11-23 03:16:15,487 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:15,487 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:15,488 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:15,488 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 03:16:15,488 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:15,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:16:15,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:16:15,690 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:16:15,690 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-11-23 03:16:15,691 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 03:16:15,691 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 03:16:15,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-11-23 03:16:15,691 INFO L87 Difference]: Start difference. First operand 3276 states and 7363 transitions. Second operand 11 states. [2018-11-23 03:16:16,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:16:16,179 INFO L93 Difference]: Finished difference Result 6829 states and 15388 transitions. [2018-11-23 03:16:16,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 03:16:16,180 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 99 [2018-11-23 03:16:16,180 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:16:16,183 INFO L225 Difference]: With dead ends: 6829 [2018-11-23 03:16:16,183 INFO L226 Difference]: Without dead ends: 4448 [2018-11-23 03:16:16,184 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=70, Invalid=310, Unknown=0, NotChecked=0, Total=380 [2018-11-23 03:16:16,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4448 states. [2018-11-23 03:16:16,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4448 to 3307. [2018-11-23 03:16:16,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3307 states. [2018-11-23 03:16:16,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3307 states to 3307 states and 7379 transitions. [2018-11-23 03:16:16,211 INFO L78 Accepts]: Start accepts. Automaton has 3307 states and 7379 transitions. Word has length 99 [2018-11-23 03:16:16,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:16:16,211 INFO L480 AbstractCegarLoop]: Abstraction has 3307 states and 7379 transitions. [2018-11-23 03:16:16,211 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 03:16:16,211 INFO L276 IsEmpty]: Start isEmpty. Operand 3307 states and 7379 transitions. [2018-11-23 03:16:16,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-11-23 03:16:16,214 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:16:16,214 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:16:16,214 INFO L423 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:16:16,214 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:16:16,214 INFO L82 PathProgramCache]: Analyzing trace with hash 460693250, now seen corresponding path program 5 times [2018-11-23 03:16:16,214 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:16:16,214 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:16:16,215 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:16,215 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 03:16:16,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:16:16,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 03:16:16,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 03:16:16,258 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [485] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [363] L-1-->L671: Formula: (= |v_#valid_9| (store |v_#valid_10| 0 0)) InVars {#valid=|v_#valid_10|} OutVars{#valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [530] L671-->L673: Formula: (= v_~__unbuffered_cnt~0_6 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [389] L673-->L675: Formula: (= v_~__unbuffered_p0_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 [429] L675-->L677: Formula: (= v_~__unbuffered_p0_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p0_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [?] -1 [494] L677-->L679: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [536] L679-->L681: Formula: (= v_~__unbuffered_p1_EBX~0_2 0) InVars {} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 [393] L681-->L682: Formula: (= v_~a~0_11 0) InVars {} OutVars{~a~0=v_~a~0_11} AuxVars[] AssignedVars[~a~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [?] -1 [529] L682-->L683: Formula: (= v_~a$flush_delayed~0_5 0) InVars {} OutVars{~a$flush_delayed~0=v_~a$flush_delayed~0_5} AuxVars[] AssignedVars[~a$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [?] -1 [458] L683-->L684: Formula: (= v_~a$mem_tmp~0_3 0) InVars {} OutVars{~a$mem_tmp~0=v_~a$mem_tmp~0_3} AuxVars[] AssignedVars[~a$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [?] -1 [386] L684-->L685: Formula: (= v_~a$r_buff0_thd0~0_2 0) InVars {} OutVars{~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_2} AuxVars[] AssignedVars[~a$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [?] -1 [504] L685-->L686: Formula: (= v_~a$r_buff0_thd1~0_14 0) InVars {} OutVars{~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_14} AuxVars[] AssignedVars[~a$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [?] -1 [428] L686-->L687: Formula: (= v_~a$r_buff0_thd2~0_43 0) InVars {} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_43} AuxVars[] AssignedVars[~a$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [?] -1 [380] L687-->L688: Formula: (= v_~a$r_buff1_thd0~0_2 0) InVars {} OutVars{~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_2} AuxVars[] AssignedVars[~a$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [?] -1 [493] L688-->L689: Formula: (= v_~a$r_buff1_thd1~0_9 0) InVars {} OutVars{~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~a$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [?] -1 [421] L689-->L690: Formula: (= v_~a$r_buff1_thd2~0_25 0) InVars {} OutVars{~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_25} AuxVars[] AssignedVars[~a$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [?] -1 [535] L690-->L691: Formula: (= v_~a$read_delayed~0_1 0) InVars {} OutVars{~a$read_delayed~0=v_~a$read_delayed~0_1} AuxVars[] AssignedVars[~a$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [?] -1 [466] L691-->L692: Formula: (and (= v_~a$read_delayed_var~0.base_1 0) (= v_~a$read_delayed_var~0.offset_1 0)) InVars {} OutVars{~a$read_delayed_var~0.base=v_~a$read_delayed_var~0.base_1, ~a$read_delayed_var~0.offset=v_~a$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~a$read_delayed_var~0.offset, ~a$read_delayed_var~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a~0=0] [?] -1 [392] L692-->L693: Formula: (= v_~a$w_buff0~0_11 0) InVars {} OutVars{~a$w_buff0~0=v_~a$w_buff0~0_11} AuxVars[] AssignedVars[~a$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [?] -1 [526] L693-->L694: Formula: (= v_~a$w_buff0_used~0_55 0) InVars {} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_55} AuxVars[] AssignedVars[~a$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [?] -1 [457] L694-->L695: Formula: (= v_~a$w_buff1~0_10 0) InVars {} OutVars{~a$w_buff1~0=v_~a$w_buff1~0_10} AuxVars[] AssignedVars[~a$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [?] -1 [385] L695-->L696: Formula: (= v_~a$w_buff1_used~0_32 0) InVars {} OutVars{~a$w_buff1_used~0=v_~a$w_buff1_used~0_32} AuxVars[] AssignedVars[~a$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [?] -1 [502] L696-->L697: Formula: (= v_~main$tmp_guard0~0_1 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [?] -1 [425] L697-->L699: Formula: (= v_~main$tmp_guard1~0_1 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_1} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [491] L699-->L701: Formula: (= v_~x~0_2 0) InVars {} OutVars{~x~0=v_~x~0_2} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [534] L701-->L703: Formula: (= v_~y~0_3 0) InVars {} OutVars{~y~0=v_~y~0_3} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 [415] L703-->L704: Formula: (= v_~z~0_2 0) InVars {} OutVars{~z~0=v_~z~0_2} AuxVars[] AssignedVars[~z~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [523] L704-->L705: Formula: (= v_~weak$$choice0~0_2 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [456] L705-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [527] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [520] L-1-2-->L790: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_1|, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_1|, ULTIMATE.start_main_~#t840~0.offset=|v_ULTIMATE.start_main_~#t840~0.offset_1|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_1|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_1|, ULTIMATE.start_main_~#t839~0.base=|v_ULTIMATE.start_main_~#t839~0.base_1|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_1|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_1|, ULTIMATE.start_main_~#t840~0.base=|v_ULTIMATE.start_main_~#t840~0.base_1|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_1|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_1|, ULTIMATE.start_main_~#t839~0.offset=|v_ULTIMATE.start_main_~#t839~0.offset_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet40, ULTIMATE.start_main_#t~nondet41, ULTIMATE.start_main_~#t840~0.offset, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_~#t839~0.offset, ULTIMATE.start_main_~#t839~0.base, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_~#t840~0.base, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [477] L790-->L790-1: Formula: (and (not (= |v_ULTIMATE.start_main_~#t839~0.base_2| 0)) (= 0 |v_ULTIMATE.start_main_~#t839~0.offset_2|) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t839~0.base_2|) 0) (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t839~0.base_2| 4) |v_#length_1|) (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t839~0.base_2| 1) |v_#valid_1|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{ULTIMATE.start_main_~#t839~0.offset=|v_ULTIMATE.start_main_~#t839~0.offset_2|, #length=|v_#length_1|, ULTIMATE.start_main_~#t839~0.base=|v_ULTIMATE.start_main_~#t839~0.base_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid, ULTIMATE.start_main_~#t839~0.offset, #length, ULTIMATE.start_main_~#t839~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [478] L790-1-->L791: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t839~0.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t839~0.base_3|) |v_ULTIMATE.start_main_~#t839~0.offset_3| 0))) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t839~0.offset=|v_ULTIMATE.start_main_~#t839~0.offset_3|, ULTIMATE.start_main_~#t839~0.base=|v_ULTIMATE.start_main_~#t839~0.base_3|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t839~0.offset=|v_ULTIMATE.start_main_~#t839~0.offset_3|, ULTIMATE.start_main_~#t839~0.base=|v_ULTIMATE.start_main_~#t839~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 [651] L791-->P0ENTRY: Formula: (and (= 0 |v_Thread1_P0_#in~arg.base_3|) (= 0 v_Thread1_P0_thidvar0_2) (= 0 |v_Thread1_P0_#in~arg.offset_3|)) InVars {} OutVars{Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_3|, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_3|, Thread1_P0_thidvar0=v_Thread1_P0_thidvar0_2} AuxVars[] AssignedVars[Thread1_P0_#in~arg.base, Thread1_P0_#in~arg.offset, Thread1_P0_thidvar0] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 [538] P0ENTRY-->L4: Formula: (and (= v_Thread1_P0_~arg.base_1 |v_Thread1_P0_#in~arg.base_1|) (= v_Thread1_P0_~arg.offset_1 |v_Thread1_P0_#in~arg.offset_1|) (= v_~a$w_buff1_used~0_1 v_~a$w_buff0_used~0_2) (= v_~a$w_buff0_used~0_1 1) (= v_~a$w_buff0~0_1 1) (= v_Thread1_P0___VERIFIER_assert_~expression_1 |v_Thread1_P0___VERIFIER_assert_#in~expression_1|) (= v_~a$w_buff1~0_1 v_~a$w_buff0~0_2) (= |v_Thread1_P0___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~a$w_buff1_used~0_1 256))) (not (= (mod v_~a$w_buff0_used~0_1 256) 0)))) 1 0))) InVars {Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_2, Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, ~a$w_buff0~0=v_~a$w_buff0~0_2} OutVars{Thread1_P0___VERIFIER_assert_~expression=v_Thread1_P0___VERIFIER_assert_~expression_1, Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, ~a$w_buff1~0=v_~a$w_buff1~0_1, Thread1_P0_~arg.offset=v_Thread1_P0_~arg.offset_1, ~a$w_buff0~0=v_~a$w_buff0~0_1, Thread1_P0___VERIFIER_assert_#in~expression=|v_Thread1_P0___VERIFIER_assert_#in~expression_1|, Thread1_P0_~arg.base=v_Thread1_P0_~arg.base_1, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_1, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_1} AuxVars[] AssignedVars[Thread1_P0___VERIFIER_assert_~expression, ~a$w_buff1~0, Thread1_P0_~arg.offset, ~a$w_buff0~0, Thread1_P0___VERIFIER_assert_#in~expression, Thread1_P0_~arg.base, ~a$w_buff0_used~0, ~a$w_buff1_used~0] VAL [Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [411] L791-1-->L792: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet40] VAL [Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [517] L792-->L792-1: Formula: (and (= |v_ULTIMATE.start_main_~#t840~0.offset_2| 0) (= |v_#valid_3| (store |v_#valid_4| |v_ULTIMATE.start_main_~#t840~0.base_2| 1)) (= 0 (select |v_#valid_4| |v_ULTIMATE.start_main_~#t840~0.base_2|)) (not (= |v_ULTIMATE.start_main_~#t840~0.base_2| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t840~0.base_2| 4))) InVars {#length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{#length=|v_#length_3|, ULTIMATE.start_main_~#t840~0.offset=|v_ULTIMATE.start_main_~#t840~0.offset_2|, ULTIMATE.start_main_~#t840~0.base=|v_ULTIMATE.start_main_~#t840~0.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t840~0.offset, #valid, #length, ULTIMATE.start_main_~#t840~0.base] VAL [Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [518] L792-1-->L793: Formula: (= |v_#memory_int_3| (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t840~0.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t840~0.base_3|) |v_ULTIMATE.start_main_~#t840~0.offset_3| 1))) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t840~0.offset=|v_ULTIMATE.start_main_~#t840~0.offset_3|, ULTIMATE.start_main_~#t840~0.base=|v_ULTIMATE.start_main_~#t840~0.base_3|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t840~0.offset=|v_ULTIMATE.start_main_~#t840~0.offset_3|, ULTIMATE.start_main_~#t840~0.base=|v_ULTIMATE.start_main_~#t840~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 [650] L793-->P1ENTRY: Formula: (and (= 0 |v_Thread0_P1_#in~arg.offset_3|) (= 1 v_Thread0_P1_thidvar0_2) (= 0 |v_Thread0_P1_#in~arg.base_3|)) InVars {} OutVars{Thread0_P1_thidvar0=v_Thread0_P1_thidvar0_2, Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_3|, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P1_thidvar0, Thread0_P1_#in~arg.base, Thread0_P1_#in~arg.offset] VAL [Thread0_P1_thidvar0=1, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 [540] L4-->L4-3: Formula: (not (= 0 v_Thread1_P0___VERIFIER_assert_~expression_3)) InVars {Thread1_P0___VERIFIER_assert_~expression=v_Thread1_P0___VERIFIER_assert_~expression_3} OutVars{Thread1_P0___VERIFIER_assert_~expression=v_Thread1_P0___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 [543] L4-3-->L729: Formula: (and (= v_~__unbuffered_p0_EAX~0_1 v_~x~0_1) (= v_~a$r_buff1_thd1~0_1 v_~a$r_buff0_thd1~0_2) (= v_~a$r_buff1_thd0~0_1 v_~a$r_buff0_thd0~0_1) (= v_~a$r_buff1_thd2~0_1 v_~a$r_buff0_thd2~0_1) (= v_~a$r_buff0_thd1~0_1 1) (= v_~x~0_1 1) (= v_~__unbuffered_p0_EBX~0_1 v_~y~0_1)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_1, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_2, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_1, ~y~0=v_~y~0_1} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_1, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_1, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_1, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_1, ~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_1, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_1, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_1, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_1, ~y~0=v_~y~0_1, ~x~0=v_~x~0_1} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, ~__unbuffered_p0_EBX~0, ~a$r_buff1_thd1~0, ~a$r_buff1_thd2~0, ~a$r_buff1_thd0~0, ~a$r_buff0_thd1~0, ~x~0] VAL [Thread0_P1_thidvar0=1, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [?] 0 [544] L729-->L729-5: Formula: (and (not (= (mod v_~a$r_buff0_thd1~0_3 256) 0)) (= |v_Thread1_P0_#t~ite4_1| v_~a$w_buff0~0_3) (not (= 0 (mod v_~a$w_buff0_used~0_3 256)))) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_3, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_3, ~a$w_buff0~0=v_~a$w_buff0~0_3} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_3, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_3, ~a$w_buff0~0=v_~a$w_buff0~0_3, Thread1_P0_#t~ite4=|v_Thread1_P0_#t~ite4_1|} AuxVars[] AssignedVars[Thread1_P0_#t~ite4] VAL [Thread0_P1_thidvar0=1, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite4|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [?] 1 [565] P1ENTRY-->L756: Formula: (and (= v_Thread0_P1_~arg.offset_1 |v_Thread0_P1_#in~arg.offset_1|) (= v_~z~0_1 1) (= v_~a$flush_delayed~0_1 v_~weak$$choice2~0_7) (= v_Thread0_P1_~arg.base_1 |v_Thread0_P1_#in~arg.base_1|) (= v_~a$mem_tmp~0_1 v_~a~0_3) (= v_~weak$$choice0~0_1 (ite (= 0 (+ |v_Thread0_P1_#t~nondet10.base_1| |v_Thread0_P1_#t~nondet10.offset_1|)) 0 1)) (= v_~__unbuffered_p1_EAX~0_1 v_~z~0_1) (= v_~y~0_2 1) (= v_~weak$$choice2~0_7 (ite (= (+ |v_Thread0_P1_#t~nondet11.offset_1| |v_Thread0_P1_#t~nondet11.base_1|) 0) 0 1))) InVars {~a~0=v_~a~0_3, Thread0_P1_#t~nondet10.offset=|v_Thread0_P1_#t~nondet10.offset_1|, Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_1|, Thread0_P1_#t~nondet10.base=|v_Thread0_P1_#t~nondet10.base_1|, Thread0_P1_#t~nondet11.base=|v_Thread0_P1_#t~nondet11.base_1|, Thread0_P1_#t~nondet11.offset=|v_Thread0_P1_#t~nondet11.offset_1|, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_1|} OutVars{Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_1|, Thread0_P1_#t~nondet10.base=|v_Thread0_P1_#t~nondet10.base_2|, Thread0_P1_~arg.offset=v_Thread0_P1_~arg.offset_1, Thread0_P1_#t~nondet11.base=|v_Thread0_P1_#t~nondet11.base_2|, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_1|, ~a$mem_tmp~0=v_~a$mem_tmp~0_1, ~a~0=v_~a~0_3, ~weak$$choice0~0=v_~weak$$choice0~0_1, Thread0_P1_#t~nondet10.offset=|v_Thread0_P1_#t~nondet10.offset_2|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, ~a$flush_delayed~0=v_~a$flush_delayed~0_1, Thread0_P1_~arg.base=v_Thread0_P1_~arg.base_1, Thread0_P1_#t~nondet11.offset=|v_Thread0_P1_#t~nondet11.offset_2|, ~z~0=v_~z~0_1, ~weak$$choice2~0=v_~weak$$choice2~0_7, ~y~0=v_~y~0_2} AuxVars[] AssignedVars[Thread0_P1_#t~nondet10.base, Thread0_P1_~arg.offset, Thread0_P1_#t~nondet11.base, ~a$mem_tmp~0, ~weak$$choice0~0, Thread0_P1_#t~nondet10.offset, ~__unbuffered_p1_EAX~0, ~a$flush_delayed~0, Thread0_P1_~arg.base, Thread0_P1_#t~nondet11.offset, ~z~0, ~weak$$choice2~0, ~y~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite4|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [566] L756-->L756-5: Formula: (and (let ((.cse0 (= 0 (mod v_~a$r_buff0_thd2~0_15 256)))) (or (and .cse0 (= 0 (mod v_~a$w_buff1_used~0_17 256))) (and .cse0 (= (mod v_~a$r_buff1_thd2~0_9 256) 0)) (= 0 (mod v_~a$w_buff0_used~0_26 256)))) (= |v_Thread0_P1_#t~ite13_1| v_~a~0_4)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_15, ~a~0=v_~a~0_4, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_26, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_17, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_9} OutVars{~a~0=v_~a~0_4, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_9, ~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_15, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_26, Thread0_P1_#t~ite13=|v_Thread0_P1_#t~ite13_1|, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_17} AuxVars[] AssignedVars[Thread0_P1_#t~ite13] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite13|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite4|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [546] L729-5-->L730: Formula: (= v_~a~0_2 |v_Thread1_P0_#t~ite4_2|) InVars {Thread1_P0_#t~ite4=|v_Thread1_P0_#t~ite4_2|} OutVars{~a~0=v_~a~0_2, Thread1_P0_#t~ite3=|v_Thread1_P0_#t~ite3_1|, Thread1_P0_#t~ite4=|v_Thread1_P0_#t~ite4_3|} AuxVars[] AssignedVars[~a~0, Thread1_P0_#t~ite3, Thread1_P0_#t~ite4] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite13|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [549] L730-->L730-2: Formula: (and (= |v_Thread1_P0_#t~ite5_1| 0) (not (= (mod v_~a$r_buff0_thd1~0_5 256) 0)) (not (= (mod v_~a$w_buff0_used~0_5 256) 0))) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_5, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_5} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_5, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_5, Thread1_P0_#t~ite5=|v_Thread1_P0_#t~ite5_1|} AuxVars[] AssignedVars[Thread1_P0_#t~ite5] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite13|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite5|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [552] L730-2-->L731: Formula: (= v_~a$w_buff0_used~0_7 |v_Thread1_P0_#t~ite5_3|) InVars {Thread1_P0_#t~ite5=|v_Thread1_P0_#t~ite5_3|} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_7, Thread1_P0_#t~ite5=|v_Thread1_P0_#t~ite5_4|} AuxVars[] AssignedVars[~a$w_buff0_used~0, Thread1_P0_#t~ite5] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite13|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [568] L756-5-->L757: Formula: (= v_~a~0_6 |v_Thread0_P1_#t~ite13_2|) InVars {Thread0_P1_#t~ite13=|v_Thread0_P1_#t~ite13_2|} OutVars{~a~0=v_~a~0_6, Thread0_P1_#t~ite12=|v_Thread0_P1_#t~ite12_1|, Thread0_P1_#t~ite13=|v_Thread0_P1_#t~ite13_3|} AuxVars[] AssignedVars[~a~0, Thread0_P1_#t~ite12, Thread0_P1_#t~ite13] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [554] L731-->L731-2: Formula: (and (= |v_Thread1_P0_#t~ite6_2| v_~a$w_buff1_used~0_5) (or (= (mod v_~a$w_buff1_used~0_5 256) 0) (= (mod v_~a$r_buff1_thd1~0_5 256) 0)) (or (= 0 (mod v_~a$r_buff0_thd1~0_8 256)) (= 0 (mod v_~a$w_buff0_used~0_9 256)))) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_9, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_8, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_5, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_5} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_9, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_8, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_5, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_5, Thread1_P0_#t~ite6=|v_Thread1_P0_#t~ite6_2|} AuxVars[] AssignedVars[Thread1_P0_#t~ite6] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite6|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [571] L757-->L757-8: Formula: (and (not (= (mod v_~weak$$choice2~0_8 256) 0)) (= |v_Thread0_P1_#t~ite16_1| v_~a$w_buff0~0_5)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_8, ~a$w_buff0~0=v_~a$w_buff0~0_5} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_8, ~a$w_buff0~0=v_~a$w_buff0~0_5, Thread0_P1_#t~ite16=|v_Thread0_P1_#t~ite16_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite16] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite6|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [555] L731-2-->L732: Formula: (= v_~a$w_buff1_used~0_6 |v_Thread1_P0_#t~ite6_3|) InVars {Thread1_P0_#t~ite6=|v_Thread1_P0_#t~ite6_3|} OutVars{~a$w_buff1_used~0=v_~a$w_buff1_used~0_6, Thread1_P0_#t~ite6=|v_Thread1_P0_#t~ite6_4|} AuxVars[] AssignedVars[~a$w_buff1_used~0, Thread1_P0_#t~ite6] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [557] L732-->L732-2: Formula: (and (or (= 0 (mod v_~a$r_buff0_thd1~0_10 256)) (= 0 (mod v_~a$w_buff0_used~0_11 256))) (= |v_Thread1_P0_#t~ite7_2| v_~a$r_buff0_thd1~0_10)) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_11, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_10} OutVars{Thread1_P0_#t~ite7=|v_Thread1_P0_#t~ite7_2|, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_11, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_10} AuxVars[] AssignedVars[Thread1_P0_#t~ite7] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite7|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [558] L732-2-->L733: Formula: (= v_~a$r_buff0_thd1~0_11 |v_Thread1_P0_#t~ite7_3|) InVars {Thread1_P0_#t~ite7=|v_Thread1_P0_#t~ite7_3|} OutVars{Thread1_P0_#t~ite7=|v_Thread1_P0_#t~ite7_4|, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_11} AuxVars[] AssignedVars[Thread1_P0_#t~ite7, ~a$r_buff0_thd1~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [560] L733-->L733-2: Formula: (and (or (= 0 (mod v_~a$w_buff0_used~0_13 256)) (= (mod v_~a$r_buff0_thd1~0_13 256) 0)) (= |v_Thread1_P0_#t~ite8_2| v_~a$r_buff1_thd1~0_7) (or (= 0 (mod v_~a$r_buff1_thd1~0_7 256)) (= (mod v_~a$w_buff1_used~0_8 256) 0))) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_13, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_13, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_8, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_7} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_13, Thread1_P0_#t~ite8=|v_Thread1_P0_#t~ite8_2|, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_13, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_8, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_7} AuxVars[] AssignedVars[Thread1_P0_#t~ite8] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite8|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [561] L733-2-->L738: Formula: (and (= v_~a$r_buff1_thd1~0_8 |v_Thread1_P0_#t~ite8_3|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1))) InVars {Thread1_P0_#t~ite8=|v_Thread1_P0_#t~ite8_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{Thread1_P0_#t~ite8=|v_Thread1_P0_#t~ite8_4|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_8} AuxVars[] AssignedVars[~a$r_buff1_thd1~0, Thread1_P0_#t~ite8, ~__unbuffered_cnt~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [574] L757-8-->L758: Formula: (= v_~a$w_buff0~0_10 |v_Thread0_P1_#t~ite16_2|) InVars {Thread0_P1_#t~ite16=|v_Thread0_P1_#t~ite16_2|} OutVars{Thread0_P1_#t~ite14=|v_Thread0_P1_#t~ite14_1|, ~a$w_buff0~0=v_~a$w_buff0~0_10, Thread0_P1_#t~ite15=|v_Thread0_P1_#t~ite15_1|, Thread0_P1_#t~ite16=|v_Thread0_P1_#t~ite16_3|} AuxVars[] AssignedVars[~a$w_buff0~0, Thread0_P1_#t~ite14, Thread0_P1_#t~ite15, Thread0_P1_#t~ite16] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [577] L758-->L758-8: Formula: (and (= |v_Thread0_P1_#t~ite19_1| v_~a$w_buff1~0_5) (not (= (mod v_~weak$$choice2~0_10 256) 0))) InVars {~a$w_buff1~0=v_~a$w_buff1~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_10} OutVars{Thread0_P1_#t~ite19=|v_Thread0_P1_#t~ite19_1|, ~a$w_buff1~0=v_~a$w_buff1~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_10} AuxVars[] AssignedVars[Thread0_P1_#t~ite19] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite19|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [582] L758-8-->L759: Formula: (= v_~a$w_buff1~0_9 |v_Thread0_P1_#t~ite19_2|) InVars {Thread0_P1_#t~ite19=|v_Thread0_P1_#t~ite19_2|} OutVars{Thread0_P1_#t~ite18=|v_Thread0_P1_#t~ite18_1|, Thread0_P1_#t~ite19=|v_Thread0_P1_#t~ite19_3|, ~a$w_buff1~0=v_~a$w_buff1~0_9, Thread0_P1_#t~ite17=|v_Thread0_P1_#t~ite17_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite18, Thread0_P1_#t~ite19, ~a$w_buff1~0, Thread0_P1_#t~ite17] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [586] L759-->L759-8: Formula: (and (not (= (mod v_~weak$$choice2~0_12 256) 0)) (= |v_Thread0_P1_#t~ite22_1| v_~a$w_buff0_used~0_50)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_12, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_50} OutVars{Thread0_P1_#t~ite22=|v_Thread0_P1_#t~ite22_1|, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_50, ~weak$$choice2~0=v_~weak$$choice2~0_12} AuxVars[] AssignedVars[Thread0_P1_#t~ite22] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite22|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [591] L759-8-->L760: Formula: (= v_~a$w_buff0_used~0_15 |v_Thread0_P1_#t~ite22_2|) InVars {Thread0_P1_#t~ite22=|v_Thread0_P1_#t~ite22_2|} OutVars{Thread0_P1_#t~ite22=|v_Thread0_P1_#t~ite22_3|, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_15, Thread0_P1_#t~ite21=|v_Thread0_P1_#t~ite21_1|, Thread0_P1_#t~ite20=|v_Thread0_P1_#t~ite20_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite20, Thread0_P1_#t~ite22, ~a$w_buff0_used~0, Thread0_P1_#t~ite21] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [595] L760-->L760-8: Formula: (and (= |v_Thread0_P1_#t~ite25_1| v_~a$w_buff1_used~0_9) (not (= (mod v_~weak$$choice2~0_1 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_1, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_9} OutVars{~a$w_buff1_used~0=v_~a$w_buff1_used~0_9, ~weak$$choice2~0=v_~weak$$choice2~0_1, Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite25] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite25|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [600] L760-8-->L761: Formula: (= v_~a$w_buff1_used~0_12 |v_Thread0_P1_#t~ite25_2|) InVars {Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_2|} OutVars{Thread0_P1_#t~ite24=|v_Thread0_P1_#t~ite24_1|, Thread0_P1_#t~ite23=|v_Thread0_P1_#t~ite23_1|, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_12, Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_3|} AuxVars[] AssignedVars[Thread0_P1_#t~ite24, Thread0_P1_#t~ite23, ~a$w_buff1_used~0, Thread0_P1_#t~ite25] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [604] L761-->L761-8: Formula: (and (= |v_Thread0_P1_#t~ite28_1| v_~a$r_buff0_thd2~0_7) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_3} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_3, Thread0_P1_#t~ite28=|v_Thread0_P1_#t~ite28_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite28] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite28|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [609] L761-8-->L762: Formula: (= v_~a$r_buff0_thd2~0_12 |v_Thread0_P1_#t~ite28_2|) InVars {Thread0_P1_#t~ite28=|v_Thread0_P1_#t~ite28_2|} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_12, Thread0_P1_#t~ite26=|v_Thread0_P1_#t~ite26_1|, Thread0_P1_#t~ite28=|v_Thread0_P1_#t~ite28_3|, Thread0_P1_#t~ite27=|v_Thread0_P1_#t~ite27_1|} AuxVars[] AssignedVars[~a$r_buff0_thd2~0, Thread0_P1_#t~ite26, Thread0_P1_#t~ite28, Thread0_P1_#t~ite27] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [613] L762-->L762-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_5 256))) (= |v_Thread0_P1_#t~ite31_1| v_~a$r_buff1_thd2~0_6)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_6} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_5, Thread0_P1_#t~ite31=|v_Thread0_P1_#t~ite31_1|, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_6} AuxVars[] AssignedVars[Thread0_P1_#t~ite31] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite31|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [618] L762-8-->L764: Formula: (and (= v_~a$r_buff1_thd2~0_11 |v_Thread0_P1_#t~ite31_2|) (= v_~__unbuffered_p1_EBX~0_1 v_~a~0_5)) InVars {~a~0=v_~a~0_5, Thread0_P1_#t~ite31=|v_Thread0_P1_#t~ite31_2|} OutVars{~a~0=v_~a~0_5, Thread0_P1_#t~ite29=|v_Thread0_P1_#t~ite29_1|, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_1, Thread0_P1_#t~ite31=|v_Thread0_P1_#t~ite31_3|, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_11, Thread0_P1_#t~ite30=|v_Thread0_P1_#t~ite30_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite29, ~__unbuffered_p1_EBX~0, Thread0_P1_#t~ite31, ~a$r_buff1_thd2~0, Thread0_P1_#t~ite30] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [622] L764-->L764-2: Formula: (and (not (= 0 (mod v_~a$flush_delayed~0_2 256))) (= |v_Thread0_P1_#t~ite32_1| v_~a$mem_tmp~0_2)) InVars {~a$mem_tmp~0=v_~a$mem_tmp~0_2, ~a$flush_delayed~0=v_~a$flush_delayed~0_2} OutVars{~a$mem_tmp~0=v_~a$mem_tmp~0_2, Thread0_P1_#t~ite32=|v_Thread0_P1_#t~ite32_1|, ~a$flush_delayed~0=v_~a$flush_delayed~0_2} AuxVars[] AssignedVars[Thread0_P1_#t~ite32] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite32|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [627] L764-2-->L768: Formula: (and (= v_~a~0_8 |v_Thread0_P1_#t~ite32_3|) (= v_~a$flush_delayed~0_4 0)) InVars {Thread0_P1_#t~ite32=|v_Thread0_P1_#t~ite32_3|} OutVars{~a~0=v_~a~0_8, Thread0_P1_#t~ite32=|v_Thread0_P1_#t~ite32_4|, ~a$flush_delayed~0=v_~a$flush_delayed~0_4} AuxVars[] AssignedVars[~a~0, ~a$flush_delayed~0, Thread0_P1_#t~ite32] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [630] L768-->L768-2: Formula: (or (= 0 (mod v_~a$r_buff0_thd2~0_24 256)) (= (mod v_~a$w_buff0_used~0_35 256) 0)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_24, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_35} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_24, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_35} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [633] L768-2-->L768-4: Formula: (and (or (= 0 (mod v_~a$w_buff1_used~0_22 256)) (= (mod v_~a$r_buff1_thd2~0_15 256) 0)) (= |v_Thread0_P1_#t~ite33_3| v_~a~0_9)) InVars {~a~0=v_~a~0_9, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_22, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_15} OutVars{Thread0_P1_#t~ite33=|v_Thread0_P1_#t~ite33_3|, ~a~0=v_~a~0_9, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_22, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_15} AuxVars[] AssignedVars[Thread0_P1_#t~ite33] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite33|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [636] L768-4-->L768-5: Formula: (= |v_Thread0_P1_#t~ite34_4| |v_Thread0_P1_#t~ite33_4|) InVars {Thread0_P1_#t~ite33=|v_Thread0_P1_#t~ite33_4|} OutVars{Thread0_P1_#t~ite33=|v_Thread0_P1_#t~ite33_4|, Thread0_P1_#t~ite34=|v_Thread0_P1_#t~ite34_4|} AuxVars[] AssignedVars[Thread0_P1_#t~ite34] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite33|=0, |Thread0_P1_#t~ite34|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [631] L768-5-->L769: Formula: (= v_~a~0_10 |v_Thread0_P1_#t~ite34_2|) InVars {Thread0_P1_#t~ite34=|v_Thread0_P1_#t~ite34_2|} OutVars{Thread0_P1_#t~ite33=|v_Thread0_P1_#t~ite33_1|, ~a~0=v_~a~0_10, Thread0_P1_#t~ite34=|v_Thread0_P1_#t~ite34_3|} AuxVars[] AssignedVars[~a~0, Thread0_P1_#t~ite33, Thread0_P1_#t~ite34] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [635] L769-->L769-2: Formula: (and (or (= 0 (mod v_~a$r_buff0_thd2~0_28 256)) (= (mod v_~a$w_buff0_used~0_39 256) 0)) (= |v_Thread0_P1_#t~ite35_2| v_~a$w_buff0_used~0_39)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_28, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_39} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_28, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_39, Thread0_P1_#t~ite35=|v_Thread0_P1_#t~ite35_2|} AuxVars[] AssignedVars[Thread0_P1_#t~ite35] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite35|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [637] L769-2-->L770: Formula: (= v_~a$w_buff0_used~0_40 |v_Thread0_P1_#t~ite35_3|) InVars {Thread0_P1_#t~ite35=|v_Thread0_P1_#t~ite35_3|} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_40, Thread0_P1_#t~ite35=|v_Thread0_P1_#t~ite35_4|} AuxVars[] AssignedVars[~a$w_buff0_used~0, Thread0_P1_#t~ite35] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [639] L770-->L770-2: Formula: (and (or (= (mod v_~a$r_buff1_thd2~0_19 256) 0) (= (mod v_~a$w_buff1_used~0_26 256) 0)) (or (= 0 (mod v_~a$r_buff0_thd2~0_32 256)) (= 0 (mod v_~a$w_buff0_used~0_44 256))) (= |v_Thread0_P1_#t~ite36_2| v_~a$w_buff1_used~0_26)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_32, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_44, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_26, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_19} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_32, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_44, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_26, Thread0_P1_#t~ite36=|v_Thread0_P1_#t~ite36_2|, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_19} AuxVars[] AssignedVars[Thread0_P1_#t~ite36] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite36|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [640] L770-2-->L771: Formula: (= v_~a$w_buff1_used~0_27 |v_Thread0_P1_#t~ite36_3|) InVars {Thread0_P1_#t~ite36=|v_Thread0_P1_#t~ite36_3|} OutVars{Thread0_P1_#t~ite36=|v_Thread0_P1_#t~ite36_4|, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_27} AuxVars[] AssignedVars[~a$w_buff1_used~0, Thread0_P1_#t~ite36] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [642] L771-->L771-2: Formula: (and (or (= 0 (mod v_~a$w_buff0_used~0_48 256)) (= 0 (mod v_~a$r_buff0_thd2~0_36 256))) (= |v_Thread0_P1_#t~ite37_2| v_~a$r_buff0_thd2~0_36)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_36, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_48} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_36, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_48, Thread0_P1_#t~ite37=|v_Thread0_P1_#t~ite37_2|} AuxVars[] AssignedVars[Thread0_P1_#t~ite37] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite37|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [643] L771-2-->L772: Formula: (= v_~a$r_buff0_thd2~0_37 |v_Thread0_P1_#t~ite37_3|) InVars {Thread0_P1_#t~ite37=|v_Thread0_P1_#t~ite37_3|} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_37, Thread0_P1_#t~ite37=|v_Thread0_P1_#t~ite37_4|} AuxVars[] AssignedVars[~a$r_buff0_thd2~0, Thread0_P1_#t~ite37] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [645] L772-->L772-2: Formula: (and (or (= (mod v_~a$w_buff0_used~0_51 256) 0) (= (mod v_~a$r_buff0_thd2~0_39 256) 0)) (or (= 0 (mod v_~a$w_buff1_used~0_29 256)) (= 0 (mod v_~a$r_buff1_thd2~0_21 256))) (= |v_Thread0_P1_#t~ite38_2| v_~a$r_buff1_thd2~0_21)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_39, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_51, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_29, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_21} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_39, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_51, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_29, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_21, Thread0_P1_#t~ite38=|v_Thread0_P1_#t~ite38_2|} AuxVars[] AssignedVars[Thread0_P1_#t~ite38] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite38|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [646] L772-2-->L777: Formula: (and (= v_~a$r_buff1_thd2~0_22 |v_Thread0_P1_#t~ite38_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4, Thread0_P1_#t~ite38=|v_Thread0_P1_#t~ite38_3|} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_22, Thread0_P1_#t~ite38=|v_Thread0_P1_#t~ite38_4|} AuxVars[] AssignedVars[~a$r_buff1_thd2~0, ~__unbuffered_cnt~0, Thread0_P1_#t~ite38] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [451] L793-1-->L797: Formula: (= v_~main$tmp_guard0~0_2 (ite (= (ite (= v_~__unbuffered_cnt~0_5 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_2|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet41, ~main$tmp_guard0~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [367] L797-->L799: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_3 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [438] L799-->L799-2: Formula: (or (= 0 (mod v_~a$r_buff0_thd0~0_4 256)) (= 0 (mod v_~a$w_buff0_used~0_57 256))) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_57, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_4} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_57, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_4} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [419] L799-2-->L799-4: Formula: (and (= |v_ULTIMATE.start_main_#t~ite42_3| v_~a~0_12) (or (= (mod v_~a$w_buff1_used~0_34 256) 0) (= (mod v_~a$r_buff1_thd0~0_4 256) 0))) InVars {~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_4, ~a~0=v_~a~0_12, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_34} OutVars{~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_4, ~a~0=v_~a~0_12, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_34, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [423] L799-4-->L799-5: Formula: (= |v_ULTIMATE.start_main_#t~ite43_3| |v_ULTIMATE.start_main_#t~ite42_4|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [424] L799-5-->L800: Formula: (= v_~a~0_13 |v_ULTIMATE.start_main_#t~ite43_5|) InVars {ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|} OutVars{~a~0=v_~a~0_13, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|} AuxVars[] AssignedVars[~a~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [360] L800-->L800-2: Formula: (and (or (= (mod v_~a$w_buff0_used~0_59 256) 0) (= 0 (mod v_~a$r_buff0_thd0~0_6 256))) (= |v_ULTIMATE.start_main_#t~ite44_3| v_~a$w_buff0_used~0_59)) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_59, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_6} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_59, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_6, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [532] L800-2-->L801: Formula: (= v_~a$w_buff0_used~0_60 |v_ULTIMATE.start_main_#t~ite44_5|) InVars {ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_5|} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_60, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_4|} AuxVars[] AssignedVars[~a$w_buff0_used~0, ULTIMATE.start_main_#t~ite44] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [476] L801-->L801-2: Formula: (and (or (= (mod v_~a$w_buff0_used~0_62 256) 0) (= (mod v_~a$r_buff0_thd0~0_8 256) 0)) (= |v_ULTIMATE.start_main_#t~ite45_3| v_~a$w_buff1_used~0_36) (or (= (mod v_~a$r_buff1_thd0~0_6 256) 0) (= (mod v_~a$w_buff1_used~0_36 256) 0))) InVars {~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_6, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_62, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_36, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_8} OutVars{~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_6, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_62, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_36, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_8, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite45] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [483] L801-2-->L802: Formula: (= v_~a$w_buff1_used~0_37 |v_ULTIMATE.start_main_#t~ite45_5|) InVars {ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_5|} OutVars{ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_4|, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_37} AuxVars[] AssignedVars[~a$w_buff1_used~0, ULTIMATE.start_main_#t~ite45] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [409] L802-->L802-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite46_3| v_~a$r_buff0_thd0~0_10) (or (= (mod v_~a$r_buff0_thd0~0_10 256) 0) (= 0 (mod v_~a$w_buff0_used~0_64 256)))) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_64, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_10} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_3|, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_64, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_10} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [412] L802-2-->L803: Formula: (= v_~a$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite46_5|) InVars {ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_5|} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_4|, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_11} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ~a$r_buff0_thd0~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [516] L803-->L803-2: Formula: (and (or (= 0 (mod v_~a$w_buff1_used~0_39 256)) (= 0 (mod v_~a$r_buff1_thd0~0_8 256))) (or (= 0 (mod v_~a$r_buff0_thd0~0_13 256)) (= 0 (mod v_~a$w_buff0_used~0_66 256))) (= |v_ULTIMATE.start_main_#t~ite47_3| v_~a$r_buff1_thd0~0_8)) InVars {~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_8, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_66, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_13, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_39} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_3|, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_8, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_66, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_13, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_39} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [519] L803-2-->L808: Formula: (and (= v_~a$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite47_5|) (= v_~main$tmp_guard1~0_2 (ite (= (ite (not (and (= 0 v_~__unbuffered_p1_EBX~0_3) (= v_~__unbuffered_p0_EBX~0_2 0) (= 1 v_~__unbuffered_p1_EAX~0_2) (= v_~__unbuffered_p0_EAX~0_2 1))) 1 0) 0) 0 1))) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_5|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_2, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_2, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_4|, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ~a$r_buff1_thd0~0, ~main$tmp_guard1~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [366] L808-->L808-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_3 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [370] L808-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [407] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [405] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [402] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [?] -1 ~a$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [?] -1 ~a$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [?] -1 ~a$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [?] -1 ~a$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [?] -1 ~a$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [?] -1 ~a$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [?] -1 ~a$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [?] -1 ~a$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [?] -1 ~a$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [?] -1 ~a$read_delayed_var~0.base, ~a$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a~0=0] [?] -1 ~a$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [?] -1 ~a$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [?] -1 ~a$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [?] -1 ~a$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t839~0.base, main_~#t839~0.offset, main_~#t840~0.base, main_~#t840~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t839~0.base, main_~#t839~0.offset := #Ultimate.alloc(4); srcloc: L790 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t839~0.base, main_~#t839~0.offset, 4); srcloc: L790-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~a$w_buff1~0 := ~a$w_buff0~0;~a$w_buff0~0 := 1;~a$w_buff1_used~0 := ~a$w_buff0_used~0;~a$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t840~0.base, main_~#t840~0.offset := #Ultimate.alloc(4); srcloc: L792 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t840~0.base, main_~#t840~0.offset, 4); srcloc: L792-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0;~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0;~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0;~a$r_buff0_thd1~0 := 1;~x~0 := 1;~__unbuffered_p0_EAX~0 := ~x~0;~__unbuffered_p0_EBX~0 := ~y~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [?] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256;#t~ite4 := ~a$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 1;~z~0 := 1;~__unbuffered_p1_EAX~0 := ~z~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~a$flush_delayed~0 := ~weak$$choice2~0;~a$mem_tmp~0 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256);#t~ite13 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a~0 := #t~ite4;havoc #t~ite4;havoc #t~ite3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256));#t~ite6 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~a$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256);#t~ite7 := ~a$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256));#t~ite8 := ~a$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff0~0 := #t~ite16;havoc #t~ite15;havoc #t~ite16;havoc #t~ite14; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~a$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff1~0 := #t~ite19;havoc #t~ite19;havoc #t~ite17;havoc #t~ite18; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~a$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff0_used~0 := #t~ite22;havoc #t~ite21;havoc #t~ite20;havoc #t~ite22; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff1_used~0 := #t~ite25;havoc #t~ite23;havoc #t~ite25;havoc #t~ite24; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~a$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff0_thd2~0 := #t~ite28;havoc #t~ite26;havoc #t~ite27;havoc #t~ite28; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~a$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff1_thd2~0 := #t~ite31;havoc #t~ite31;havoc #t~ite29;havoc #t~ite30;~__unbuffered_p1_EBX~0 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~a$flush_delayed~0 % 256;#t~ite32 := ~a$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a~0 := #t~ite32;havoc #t~ite32;~a$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256);#t~ite33 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a~0 := #t~ite34;havoc #t~ite34;havoc #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256);#t~ite35 := ~a$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256));#t~ite36 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256);#t~ite37 := ~a$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256));#t~ite38 := ~a$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256);main_#t~ite42 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256);main_#t~ite44 := ~a$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256));main_#t~ite45 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256);main_#t~ite46 := ~a$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256));main_#t~ite47 := ~a$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [?] -1 ~a$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [?] -1 ~a$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [?] -1 ~a$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [?] -1 ~a$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [?] -1 ~a$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [?] -1 ~a$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [?] -1 ~a$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [?] -1 ~a$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [?] -1 ~a$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [?] -1 ~a$read_delayed_var~0.base, ~a$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a~0=0] [?] -1 ~a$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [?] -1 ~a$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [?] -1 ~a$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [?] -1 ~a$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t839~0.base, main_~#t839~0.offset, main_~#t840~0.base, main_~#t840~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t839~0.base, main_~#t839~0.offset := #Ultimate.alloc(4); srcloc: L790 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t839~0.base, main_~#t839~0.offset, 4); srcloc: L790-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~a$w_buff1~0 := ~a$w_buff0~0;~a$w_buff0~0 := 1;~a$w_buff1_used~0 := ~a$w_buff0_used~0;~a$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t840~0.base, main_~#t840~0.offset := #Ultimate.alloc(4); srcloc: L792 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t840~0.base, main_~#t840~0.offset, 4); srcloc: L792-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0;~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0;~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0;~a$r_buff0_thd1~0 := 1;~x~0 := 1;~__unbuffered_p0_EAX~0 := ~x~0;~__unbuffered_p0_EBX~0 := ~y~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [?] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256;#t~ite4 := ~a$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 1;~z~0 := 1;~__unbuffered_p1_EAX~0 := ~z~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~a$flush_delayed~0 := ~weak$$choice2~0;~a$mem_tmp~0 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256);#t~ite13 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a~0 := #t~ite4;havoc #t~ite4;havoc #t~ite3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256));#t~ite6 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~a$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256);#t~ite7 := ~a$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256));#t~ite8 := ~a$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff0~0 := #t~ite16;havoc #t~ite15;havoc #t~ite16;havoc #t~ite14; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~a$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff1~0 := #t~ite19;havoc #t~ite19;havoc #t~ite17;havoc #t~ite18; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~a$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff0_used~0 := #t~ite22;havoc #t~ite21;havoc #t~ite20;havoc #t~ite22; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff1_used~0 := #t~ite25;havoc #t~ite23;havoc #t~ite25;havoc #t~ite24; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~a$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff0_thd2~0 := #t~ite28;havoc #t~ite26;havoc #t~ite27;havoc #t~ite28; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~a$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff1_thd2~0 := #t~ite31;havoc #t~ite31;havoc #t~ite29;havoc #t~ite30;~__unbuffered_p1_EBX~0 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~a$flush_delayed~0 % 256;#t~ite32 := ~a$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a~0 := #t~ite32;havoc #t~ite32;~a$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256);#t~ite33 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a~0 := #t~ite34;havoc #t~ite34;havoc #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256);#t~ite35 := ~a$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256));#t~ite36 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256);#t~ite37 := ~a$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256));#t~ite38 := ~a$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256);main_#t~ite42 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256);main_#t~ite44 := ~a$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256));main_#t~ite45 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256);main_#t~ite46 := ~a$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256));main_#t~ite47 := ~a$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L677] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L681] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [L682] -1 ~a$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [L683] -1 ~a$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [L684] -1 ~a$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [L685] -1 ~a$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [L686] -1 ~a$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [L687] -1 ~a$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [L688] -1 ~a$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [L689] -1 ~a$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [L690] -1 ~a$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [L691] -1 ~a$read_delayed_var~0.base, ~a$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a~0=0] [L692] -1 ~a$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [L693] -1 ~a$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [L694] -1 ~a$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [L695] -1 ~a$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [L696] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L697] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L699] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L701] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L703] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L704] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L705] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t839~0.base, main_~#t839~0.offset, main_~#t840~0.base, main_~#t840~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L790] -1 call main_~#t839~0.base, main_~#t839~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 call write~int(0, main_~#t839~0.base, main_~#t839~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L706-L739] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L709] 0 ~a$w_buff1~0 := ~a$w_buff0~0; [L710] 0 ~a$w_buff0~0 := 1; [L711] 0 ~a$w_buff1_used~0 := ~a$w_buff0_used~0; [L712] 0 ~a$w_buff0_used~0 := 1; [L713] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$w_buff0_used~0 % 256) then 1 else 0); [L713] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L792] -1 call main_~#t840~0.base, main_~#t840~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] -1 call write~int(1, main_~#t840~0.base, main_~#t840~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L714] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0; [L715] 0 ~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0; [L716] 0 ~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0; [L717] 0 ~a$r_buff0_thd1~0 := 1; [L720] 0 ~x~0 := 1; [L723] 0 ~__unbuffered_p0_EAX~0 := ~x~0; [L726] 0 ~__unbuffered_p0_EBX~0 := ~y~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L729] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256; [L729] 0 #t~ite4 := ~a$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L740-L778] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L743] 1 ~y~0 := 1; [L746] 1 ~z~0 := 1; [L749] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L752] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L752] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L753] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L753] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L754] 1 ~a$flush_delayed~0 := ~weak$$choice2~0; [L755] 1 ~a$mem_tmp~0 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 assume (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256); [L756] 1 #t~ite13 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L729] 0 ~a~0 := #t~ite4; [L729] 0 havoc #t~ite4; [L729] 0 havoc #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256; [L730] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 ~a$w_buff0_used~0 := #t~ite5; [L730] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 ~a~0 := #t~ite13; [L756] 1 havoc #t~ite13; [L756] 1 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)); [L731] 0 #t~ite6 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 assume 0 != ~weak$$choice2~0 % 256; [L757] 1 #t~ite16 := ~a$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 ~a$w_buff1_used~0 := #t~ite6; [L731] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256); [L732] 0 #t~ite7 := ~a$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 ~a$r_buff0_thd1~0 := #t~ite7; [L732] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)); [L733] 0 #t~ite8 := ~a$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 ~a$r_buff1_thd1~0 := #t~ite8; [L733] 0 havoc #t~ite8; [L736] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 ~a$w_buff0~0 := #t~ite16; [L757] 1 havoc #t~ite15; [L757] 1 havoc #t~ite16; [L757] 1 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 assume 0 != ~weak$$choice2~0 % 256; [L758] 1 #t~ite19 := ~a$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 ~a$w_buff1~0 := #t~ite19; [L758] 1 havoc #t~ite19; [L758] 1 havoc #t~ite17; [L758] 1 havoc #t~ite18; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 assume 0 != ~weak$$choice2~0 % 256; [L759] 1 #t~ite22 := ~a$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 ~a$w_buff0_used~0 := #t~ite22; [L759] 1 havoc #t~ite21; [L759] 1 havoc #t~ite20; [L759] 1 havoc #t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 assume 0 != ~weak$$choice2~0 % 256; [L760] 1 #t~ite25 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 ~a$w_buff1_used~0 := #t~ite25; [L760] 1 havoc #t~ite23; [L760] 1 havoc #t~ite25; [L760] 1 havoc #t~ite24; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 assume 0 != ~weak$$choice2~0 % 256; [L761] 1 #t~ite28 := ~a$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 ~a$r_buff0_thd2~0 := #t~ite28; [L761] 1 havoc #t~ite26; [L761] 1 havoc #t~ite27; [L761] 1 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 assume 0 != ~weak$$choice2~0 % 256; [L762] 1 #t~ite31 := ~a$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 ~a$r_buff1_thd2~0 := #t~ite31; [L762] 1 havoc #t~ite31; [L762] 1 havoc #t~ite29; [L762] 1 havoc #t~ite30; [L763] 1 ~__unbuffered_p1_EBX~0 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 assume 0 != ~a$flush_delayed~0 % 256; [L764] 1 #t~ite32 := ~a$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 ~a~0 := #t~ite32; [L764] 1 havoc #t~ite32; [L765] 1 ~a$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256); [L768] 1 #t~ite33 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 ~a~0 := #t~ite34; [L768] 1 havoc #t~ite34; [L768] 1 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); [L769] 1 #t~ite35 := ~a$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 ~a$w_buff0_used~0 := #t~ite35; [L769] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)); [L770] 1 #t~ite36 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 ~a$w_buff1_used~0 := #t~ite36; [L770] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); [L771] 1 #t~ite37 := ~a$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 ~a$r_buff0_thd2~0 := #t~ite37; [L771] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)); [L772] 1 #t~ite38 := ~a$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 ~a$r_buff1_thd2~0 := #t~ite38; [L772] 1 havoc #t~ite38; [L775] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L793] -1 havoc main_#t~nondet41; [L795] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L797] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256); [L799] -1 main_#t~ite42 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 ~a~0 := main_#t~ite43; [L799] -1 havoc main_#t~ite42; [L799] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); [L800] -1 main_#t~ite44 := ~a$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 ~a$w_buff0_used~0 := main_#t~ite44; [L800] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)); [L801] -1 main_#t~ite45 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 ~a$w_buff1_used~0 := main_#t~ite45; [L801] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); [L802] -1 main_#t~ite46 := ~a$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 ~a$r_buff0_thd0~0 := main_#t~ite46; [L802] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)); [L803] -1 main_#t~ite47 := ~a$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 ~a$r_buff1_thd0~0 := main_#t~ite47; [L803] -1 havoc main_#t~ite47; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L677] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L681] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [L682] -1 ~a$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [L683] -1 ~a$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [L684] -1 ~a$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [L685] -1 ~a$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [L686] -1 ~a$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [L687] -1 ~a$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [L688] -1 ~a$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [L689] -1 ~a$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [L690] -1 ~a$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [L691] -1 ~a$read_delayed_var~0.base, ~a$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a~0=0] [L692] -1 ~a$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [L693] -1 ~a$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [L694] -1 ~a$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [L695] -1 ~a$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [L696] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L697] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L699] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L701] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L703] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L704] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L705] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t839~0.base, main_~#t839~0.offset, main_~#t840~0.base, main_~#t840~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L790] -1 call main_~#t839~0.base, main_~#t839~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 call write~int(0, main_~#t839~0.base, main_~#t839~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L706-L739] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L709] 0 ~a$w_buff1~0 := ~a$w_buff0~0; [L710] 0 ~a$w_buff0~0 := 1; [L711] 0 ~a$w_buff1_used~0 := ~a$w_buff0_used~0; [L712] 0 ~a$w_buff0_used~0 := 1; [L713] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$w_buff0_used~0 % 256) then 1 else 0); [L713] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L792] -1 call main_~#t840~0.base, main_~#t840~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] -1 call write~int(1, main_~#t840~0.base, main_~#t840~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L714] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0; [L715] 0 ~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0; [L716] 0 ~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0; [L717] 0 ~a$r_buff0_thd1~0 := 1; [L720] 0 ~x~0 := 1; [L723] 0 ~__unbuffered_p0_EAX~0 := ~x~0; [L726] 0 ~__unbuffered_p0_EBX~0 := ~y~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L729] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256; [L729] 0 #t~ite4 := ~a$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L740-L778] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L743] 1 ~y~0 := 1; [L746] 1 ~z~0 := 1; [L749] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L752] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L752] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L753] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L753] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L754] 1 ~a$flush_delayed~0 := ~weak$$choice2~0; [L755] 1 ~a$mem_tmp~0 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 assume (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256); [L756] 1 #t~ite13 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L729] 0 ~a~0 := #t~ite4; [L729] 0 havoc #t~ite4; [L729] 0 havoc #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256; [L730] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 ~a$w_buff0_used~0 := #t~ite5; [L730] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 ~a~0 := #t~ite13; [L756] 1 havoc #t~ite13; [L756] 1 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)); [L731] 0 #t~ite6 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 assume 0 != ~weak$$choice2~0 % 256; [L757] 1 #t~ite16 := ~a$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 ~a$w_buff1_used~0 := #t~ite6; [L731] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256); [L732] 0 #t~ite7 := ~a$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 ~a$r_buff0_thd1~0 := #t~ite7; [L732] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)); [L733] 0 #t~ite8 := ~a$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 ~a$r_buff1_thd1~0 := #t~ite8; [L733] 0 havoc #t~ite8; [L736] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 ~a$w_buff0~0 := #t~ite16; [L757] 1 havoc #t~ite15; [L757] 1 havoc #t~ite16; [L757] 1 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 assume 0 != ~weak$$choice2~0 % 256; [L758] 1 #t~ite19 := ~a$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 ~a$w_buff1~0 := #t~ite19; [L758] 1 havoc #t~ite19; [L758] 1 havoc #t~ite17; [L758] 1 havoc #t~ite18; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 assume 0 != ~weak$$choice2~0 % 256; [L759] 1 #t~ite22 := ~a$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 ~a$w_buff0_used~0 := #t~ite22; [L759] 1 havoc #t~ite21; [L759] 1 havoc #t~ite20; [L759] 1 havoc #t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 assume 0 != ~weak$$choice2~0 % 256; [L760] 1 #t~ite25 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 ~a$w_buff1_used~0 := #t~ite25; [L760] 1 havoc #t~ite23; [L760] 1 havoc #t~ite25; [L760] 1 havoc #t~ite24; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 assume 0 != ~weak$$choice2~0 % 256; [L761] 1 #t~ite28 := ~a$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 ~a$r_buff0_thd2~0 := #t~ite28; [L761] 1 havoc #t~ite26; [L761] 1 havoc #t~ite27; [L761] 1 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 assume 0 != ~weak$$choice2~0 % 256; [L762] 1 #t~ite31 := ~a$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 ~a$r_buff1_thd2~0 := #t~ite31; [L762] 1 havoc #t~ite31; [L762] 1 havoc #t~ite29; [L762] 1 havoc #t~ite30; [L763] 1 ~__unbuffered_p1_EBX~0 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 assume 0 != ~a$flush_delayed~0 % 256; [L764] 1 #t~ite32 := ~a$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 ~a~0 := #t~ite32; [L764] 1 havoc #t~ite32; [L765] 1 ~a$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256); [L768] 1 #t~ite33 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 ~a~0 := #t~ite34; [L768] 1 havoc #t~ite34; [L768] 1 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); [L769] 1 #t~ite35 := ~a$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 ~a$w_buff0_used~0 := #t~ite35; [L769] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)); [L770] 1 #t~ite36 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 ~a$w_buff1_used~0 := #t~ite36; [L770] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); [L771] 1 #t~ite37 := ~a$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 ~a$r_buff0_thd2~0 := #t~ite37; [L771] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)); [L772] 1 #t~ite38 := ~a$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 ~a$r_buff1_thd2~0 := #t~ite38; [L772] 1 havoc #t~ite38; [L775] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L793] -1 havoc main_#t~nondet41; [L795] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L797] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256); [L799] -1 main_#t~ite42 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 ~a~0 := main_#t~ite43; [L799] -1 havoc main_#t~ite42; [L799] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); [L800] -1 main_#t~ite44 := ~a$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 ~a$w_buff0_used~0 := main_#t~ite44; [L800] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)); [L801] -1 main_#t~ite45 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 ~a$w_buff1_used~0 := main_#t~ite45; [L801] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); [L802] -1 main_#t~ite46 := ~a$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 ~a$r_buff0_thd0~0 := main_#t~ite46; [L802] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)); [L803] -1 main_#t~ite47 := ~a$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 ~a$r_buff1_thd0~0 := main_#t~ite47; [L803] -1 havoc main_#t~ite47; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L677] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L681] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [L682] -1 ~a$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [L683] -1 ~a$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [L684] -1 ~a$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [L685] -1 ~a$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [L686] -1 ~a$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [L687] -1 ~a$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [L688] -1 ~a$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [L689] -1 ~a$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [L690] -1 ~a$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [L691] -1 ~a$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a~0=0] [L692] -1 ~a$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [L693] -1 ~a$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [L694] -1 ~a$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [L695] -1 ~a$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [L696] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L697] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L699] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L701] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L703] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L704] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L705] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t839~0, main_~#t840~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L790] FCALL -1 call main_~#t839~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FCALL -1 call write~int(0, main_~#t839~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L706-L739] 0 ~arg := #in~arg; [L709] 0 ~a$w_buff1~0 := ~a$w_buff0~0; [L710] 0 ~a$w_buff0~0 := 1; [L711] 0 ~a$w_buff1_used~0 := ~a$w_buff0_used~0; [L712] 0 ~a$w_buff0_used~0 := 1; [L713] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$w_buff0_used~0 % 256) then 1 else 0); [L713] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L792] FCALL -1 call main_~#t840~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FCALL -1 call write~int(1, main_~#t840~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L714] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0; [L715] 0 ~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0; [L716] 0 ~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0; [L717] 0 ~a$r_buff0_thd1~0 := 1; [L720] 0 ~x~0 := 1; [L723] 0 ~__unbuffered_p0_EAX~0 := ~x~0; [L726] 0 ~__unbuffered_p0_EBX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L729] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L729] 0 #t~ite4 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L740-L778] 1 ~arg := #in~arg; [L743] 1 ~y~0 := 1; [L746] 1 ~z~0 := 1; [L749] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L752] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L752] 1 havoc #t~nondet10; [L753] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L753] 1 havoc #t~nondet11; [L754] 1 ~a$flush_delayed~0 := ~weak$$choice2~0; [L755] 1 ~a$mem_tmp~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] COND TRUE 1 (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256) [L756] 1 #t~ite13 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L729] 0 ~a~0 := #t~ite4; [L729] 0 havoc #t~ite4; [L729] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L730] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 ~a$w_buff0_used~0 := #t~ite5; [L730] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 ~a~0 := #t~ite13; [L756] 1 havoc #t~ite13; [L756] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L731] 0 #t~ite6 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L757] 1 #t~ite16 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 ~a$w_buff1_used~0 := #t~ite6; [L731] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] COND FALSE 0 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) [L732] 0 #t~ite7 := ~a$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 ~a$r_buff0_thd1~0 := #t~ite7; [L732] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L733] 0 #t~ite8 := ~a$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 ~a$r_buff1_thd1~0 := #t~ite8; [L733] 0 havoc #t~ite8; [L736] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 ~a$w_buff0~0 := #t~ite16; [L757] 1 havoc #t~ite15; [L757] 1 havoc #t~ite16; [L757] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L758] 1 #t~ite19 := ~a$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 ~a$w_buff1~0 := #t~ite19; [L758] 1 havoc #t~ite19; [L758] 1 havoc #t~ite17; [L758] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L759] 1 #t~ite22 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 ~a$w_buff0_used~0 := #t~ite22; [L759] 1 havoc #t~ite21; [L759] 1 havoc #t~ite20; [L759] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L760] 1 #t~ite25 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 ~a$w_buff1_used~0 := #t~ite25; [L760] 1 havoc #t~ite23; [L760] 1 havoc #t~ite25; [L760] 1 havoc #t~ite24; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L761] 1 #t~ite28 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 ~a$r_buff0_thd2~0 := #t~ite28; [L761] 1 havoc #t~ite26; [L761] 1 havoc #t~ite27; [L761] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L762] 1 #t~ite31 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 ~a$r_buff1_thd2~0 := #t~ite31; [L762] 1 havoc #t~ite31; [L762] 1 havoc #t~ite29; [L762] 1 havoc #t~ite30; [L763] 1 ~__unbuffered_p1_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] COND TRUE 1 0 != ~a$flush_delayed~0 % 256 [L764] 1 #t~ite32 := ~a$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 ~a~0 := #t~ite32; [L764] 1 havoc #t~ite32; [L765] 1 ~a$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256) [L768] 1 #t~ite33 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 ~a~0 := #t~ite34; [L768] 1 havoc #t~ite34; [L768] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L769] 1 #t~ite35 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 ~a$w_buff0_used~0 := #t~ite35; [L769] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L770] 1 #t~ite36 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 ~a$w_buff1_used~0 := #t~ite36; [L770] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L771] 1 #t~ite37 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 ~a$r_buff0_thd2~0 := #t~ite37; [L771] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L772] 1 #t~ite38 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 ~a$r_buff1_thd2~0 := #t~ite38; [L772] 1 havoc #t~ite38; [L775] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L793] -1 havoc main_#t~nondet41; [L795] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L797] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256) [L799] -1 main_#t~ite42 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 ~a~0 := main_#t~ite43; [L799] -1 havoc main_#t~ite42; [L799] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L800] -1 main_#t~ite44 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 ~a$w_buff0_used~0 := main_#t~ite44; [L800] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L801] -1 main_#t~ite45 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 ~a$w_buff1_used~0 := main_#t~ite45; [L801] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L802] -1 main_#t~ite46 := ~a$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 ~a$r_buff0_thd0~0 := main_#t~ite46; [L802] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L803] -1 main_#t~ite47 := ~a$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 ~a$r_buff1_thd0~0 := main_#t~ite47; [L803] -1 havoc main_#t~ite47; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L677] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L681] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [L682] -1 ~a$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [L683] -1 ~a$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [L684] -1 ~a$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [L685] -1 ~a$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [L686] -1 ~a$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [L687] -1 ~a$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [L688] -1 ~a$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [L689] -1 ~a$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [L690] -1 ~a$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [L691] -1 ~a$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a~0=0] [L692] -1 ~a$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [L693] -1 ~a$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [L694] -1 ~a$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [L695] -1 ~a$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [L696] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L697] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L699] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L701] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L703] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L704] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L705] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t839~0, main_~#t840~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L790] FCALL -1 call main_~#t839~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FCALL -1 call write~int(0, main_~#t839~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L706-L739] 0 ~arg := #in~arg; [L709] 0 ~a$w_buff1~0 := ~a$w_buff0~0; [L710] 0 ~a$w_buff0~0 := 1; [L711] 0 ~a$w_buff1_used~0 := ~a$w_buff0_used~0; [L712] 0 ~a$w_buff0_used~0 := 1; [L713] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$w_buff0_used~0 % 256) then 1 else 0); [L713] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L792] FCALL -1 call main_~#t840~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FCALL -1 call write~int(1, main_~#t840~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L714] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0; [L715] 0 ~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0; [L716] 0 ~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0; [L717] 0 ~a$r_buff0_thd1~0 := 1; [L720] 0 ~x~0 := 1; [L723] 0 ~__unbuffered_p0_EAX~0 := ~x~0; [L726] 0 ~__unbuffered_p0_EBX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L729] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L729] 0 #t~ite4 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L740-L778] 1 ~arg := #in~arg; [L743] 1 ~y~0 := 1; [L746] 1 ~z~0 := 1; [L749] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L752] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L752] 1 havoc #t~nondet10; [L753] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L753] 1 havoc #t~nondet11; [L754] 1 ~a$flush_delayed~0 := ~weak$$choice2~0; [L755] 1 ~a$mem_tmp~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] COND TRUE 1 (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256) [L756] 1 #t~ite13 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L729] 0 ~a~0 := #t~ite4; [L729] 0 havoc #t~ite4; [L729] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L730] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 ~a$w_buff0_used~0 := #t~ite5; [L730] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 ~a~0 := #t~ite13; [L756] 1 havoc #t~ite13; [L756] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L731] 0 #t~ite6 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L757] 1 #t~ite16 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 ~a$w_buff1_used~0 := #t~ite6; [L731] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] COND FALSE 0 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) [L732] 0 #t~ite7 := ~a$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 ~a$r_buff0_thd1~0 := #t~ite7; [L732] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L733] 0 #t~ite8 := ~a$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 ~a$r_buff1_thd1~0 := #t~ite8; [L733] 0 havoc #t~ite8; [L736] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 ~a$w_buff0~0 := #t~ite16; [L757] 1 havoc #t~ite15; [L757] 1 havoc #t~ite16; [L757] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L758] 1 #t~ite19 := ~a$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 ~a$w_buff1~0 := #t~ite19; [L758] 1 havoc #t~ite19; [L758] 1 havoc #t~ite17; [L758] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L759] 1 #t~ite22 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 ~a$w_buff0_used~0 := #t~ite22; [L759] 1 havoc #t~ite21; [L759] 1 havoc #t~ite20; [L759] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L760] 1 #t~ite25 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 ~a$w_buff1_used~0 := #t~ite25; [L760] 1 havoc #t~ite23; [L760] 1 havoc #t~ite25; [L760] 1 havoc #t~ite24; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L761] 1 #t~ite28 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 ~a$r_buff0_thd2~0 := #t~ite28; [L761] 1 havoc #t~ite26; [L761] 1 havoc #t~ite27; [L761] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L762] 1 #t~ite31 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 ~a$r_buff1_thd2~0 := #t~ite31; [L762] 1 havoc #t~ite31; [L762] 1 havoc #t~ite29; [L762] 1 havoc #t~ite30; [L763] 1 ~__unbuffered_p1_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] COND TRUE 1 0 != ~a$flush_delayed~0 % 256 [L764] 1 #t~ite32 := ~a$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 ~a~0 := #t~ite32; [L764] 1 havoc #t~ite32; [L765] 1 ~a$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256) [L768] 1 #t~ite33 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 ~a~0 := #t~ite34; [L768] 1 havoc #t~ite34; [L768] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L769] 1 #t~ite35 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 ~a$w_buff0_used~0 := #t~ite35; [L769] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L770] 1 #t~ite36 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 ~a$w_buff1_used~0 := #t~ite36; [L770] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L771] 1 #t~ite37 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 ~a$r_buff0_thd2~0 := #t~ite37; [L771] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L772] 1 #t~ite38 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 ~a$r_buff1_thd2~0 := #t~ite38; [L772] 1 havoc #t~ite38; [L775] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L793] -1 havoc main_#t~nondet41; [L795] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L797] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256) [L799] -1 main_#t~ite42 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 ~a~0 := main_#t~ite43; [L799] -1 havoc main_#t~ite42; [L799] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L800] -1 main_#t~ite44 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 ~a$w_buff0_used~0 := main_#t~ite44; [L800] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L801] -1 main_#t~ite45 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 ~a$w_buff1_used~0 := main_#t~ite45; [L801] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L802] -1 main_#t~ite46 := ~a$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 ~a$r_buff0_thd0~0 := main_#t~ite46; [L802] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L803] -1 main_#t~ite47 := ~a$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 ~a$r_buff1_thd0~0 := main_#t~ite47; [L803] -1 havoc main_#t~ite47; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L677] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L681] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [L682] -1 ~a$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [L683] -1 ~a$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [L684] -1 ~a$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [L685] -1 ~a$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [L686] -1 ~a$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [L687] -1 ~a$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [L688] -1 ~a$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [L689] -1 ~a$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [L690] -1 ~a$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [L691] -1 ~a$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a~0=0] [L692] -1 ~a$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [L693] -1 ~a$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [L694] -1 ~a$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [L695] -1 ~a$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [L696] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L697] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L699] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L701] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L703] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L704] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L705] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L790] FCALL -1 call ~#t839~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FCALL -1 call write~int(0, ~#t839~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L706-L739] 0 ~arg := #in~arg; [L709] 0 ~a$w_buff1~0 := ~a$w_buff0~0; [L710] 0 ~a$w_buff0~0 := 1; [L711] 0 ~a$w_buff1_used~0 := ~a$w_buff0_used~0; [L712] 0 ~a$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L792] FCALL -1 call ~#t840~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FCALL -1 call write~int(1, ~#t840~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L714] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0; [L715] 0 ~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0; [L716] 0 ~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0; [L717] 0 ~a$r_buff0_thd1~0 := 1; [L720] 0 ~x~0 := 1; [L723] 0 ~__unbuffered_p0_EAX~0 := ~x~0; [L726] 0 ~__unbuffered_p0_EBX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L729] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L729] 0 #t~ite4 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L740-L778] 1 ~arg := #in~arg; [L743] 1 ~y~0 := 1; [L746] 1 ~z~0 := 1; [L749] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L752] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L752] 1 havoc #t~nondet10; [L753] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L753] 1 havoc #t~nondet11; [L754] 1 ~a$flush_delayed~0 := ~weak$$choice2~0; [L755] 1 ~a$mem_tmp~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] COND TRUE 1 (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256) [L756] 1 #t~ite13 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L729] 0 ~a~0 := #t~ite4; [L729] 0 havoc #t~ite4; [L729] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L730] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 ~a$w_buff0_used~0 := #t~ite5; [L730] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 ~a~0 := #t~ite13; [L756] 1 havoc #t~ite13; [L756] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L731] 0 #t~ite6 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L757] 1 #t~ite16 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 ~a$w_buff1_used~0 := #t~ite6; [L731] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] COND FALSE 0 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) [L732] 0 #t~ite7 := ~a$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 ~a$r_buff0_thd1~0 := #t~ite7; [L732] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L733] 0 #t~ite8 := ~a$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 ~a$r_buff1_thd1~0 := #t~ite8; [L733] 0 havoc #t~ite8; [L736] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 ~a$w_buff0~0 := #t~ite16; [L757] 1 havoc #t~ite15; [L757] 1 havoc #t~ite16; [L757] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L758] 1 #t~ite19 := ~a$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 ~a$w_buff1~0 := #t~ite19; [L758] 1 havoc #t~ite19; [L758] 1 havoc #t~ite17; [L758] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L759] 1 #t~ite22 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 ~a$w_buff0_used~0 := #t~ite22; [L759] 1 havoc #t~ite21; [L759] 1 havoc #t~ite20; [L759] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L760] 1 #t~ite25 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 ~a$w_buff1_used~0 := #t~ite25; [L760] 1 havoc #t~ite23; [L760] 1 havoc #t~ite25; [L760] 1 havoc #t~ite24; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L761] 1 #t~ite28 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 ~a$r_buff0_thd2~0 := #t~ite28; [L761] 1 havoc #t~ite26; [L761] 1 havoc #t~ite27; [L761] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L762] 1 #t~ite31 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 ~a$r_buff1_thd2~0 := #t~ite31; [L762] 1 havoc #t~ite31; [L762] 1 havoc #t~ite29; [L762] 1 havoc #t~ite30; [L763] 1 ~__unbuffered_p1_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] COND TRUE 1 0 != ~a$flush_delayed~0 % 256 [L764] 1 #t~ite32 := ~a$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 ~a~0 := #t~ite32; [L764] 1 havoc #t~ite32; [L765] 1 ~a$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256) [L768] 1 #t~ite33 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 ~a~0 := #t~ite34; [L768] 1 havoc #t~ite34; [L768] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L769] 1 #t~ite35 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 ~a$w_buff0_used~0 := #t~ite35; [L769] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L770] 1 #t~ite36 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 ~a$w_buff1_used~0 := #t~ite36; [L770] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L771] 1 #t~ite37 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 ~a$r_buff0_thd2~0 := #t~ite37; [L771] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L772] 1 #t~ite38 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 ~a$r_buff1_thd2~0 := #t~ite38; [L772] 1 havoc #t~ite38; [L775] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L793] -1 havoc #t~nondet41; [L795] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L797] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256) [L799] -1 #t~ite42 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 ~a~0 := #t~ite43; [L799] -1 havoc #t~ite42; [L799] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L800] -1 #t~ite44 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 ~a$w_buff0_used~0 := #t~ite44; [L800] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L801] -1 #t~ite45 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 ~a$w_buff1_used~0 := #t~ite45; [L801] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L802] -1 #t~ite46 := ~a$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 ~a$r_buff0_thd0~0 := #t~ite46; [L802] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L803] -1 #t~ite47 := ~a$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 ~a$r_buff1_thd0~0 := #t~ite47; [L803] -1 havoc #t~ite47; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L677] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L681] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [L682] -1 ~a$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [L683] -1 ~a$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [L684] -1 ~a$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [L685] -1 ~a$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [L686] -1 ~a$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [L687] -1 ~a$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [L688] -1 ~a$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [L689] -1 ~a$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [L690] -1 ~a$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [L691] -1 ~a$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a~0=0] [L692] -1 ~a$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [L693] -1 ~a$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [L694] -1 ~a$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [L695] -1 ~a$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [L696] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L697] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L699] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L701] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L703] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L704] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L705] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L790] FCALL -1 call ~#t839~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FCALL -1 call write~int(0, ~#t839~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L706-L739] 0 ~arg := #in~arg; [L709] 0 ~a$w_buff1~0 := ~a$w_buff0~0; [L710] 0 ~a$w_buff0~0 := 1; [L711] 0 ~a$w_buff1_used~0 := ~a$w_buff0_used~0; [L712] 0 ~a$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L792] FCALL -1 call ~#t840~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FCALL -1 call write~int(1, ~#t840~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L714] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0; [L715] 0 ~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0; [L716] 0 ~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0; [L717] 0 ~a$r_buff0_thd1~0 := 1; [L720] 0 ~x~0 := 1; [L723] 0 ~__unbuffered_p0_EAX~0 := ~x~0; [L726] 0 ~__unbuffered_p0_EBX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L729] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L729] 0 #t~ite4 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L740-L778] 1 ~arg := #in~arg; [L743] 1 ~y~0 := 1; [L746] 1 ~z~0 := 1; [L749] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L752] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L752] 1 havoc #t~nondet10; [L753] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L753] 1 havoc #t~nondet11; [L754] 1 ~a$flush_delayed~0 := ~weak$$choice2~0; [L755] 1 ~a$mem_tmp~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] COND TRUE 1 (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256) [L756] 1 #t~ite13 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L729] 0 ~a~0 := #t~ite4; [L729] 0 havoc #t~ite4; [L729] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L730] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 ~a$w_buff0_used~0 := #t~ite5; [L730] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 ~a~0 := #t~ite13; [L756] 1 havoc #t~ite13; [L756] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L731] 0 #t~ite6 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L757] 1 #t~ite16 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 ~a$w_buff1_used~0 := #t~ite6; [L731] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] COND FALSE 0 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) [L732] 0 #t~ite7 := ~a$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 ~a$r_buff0_thd1~0 := #t~ite7; [L732] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L733] 0 #t~ite8 := ~a$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 ~a$r_buff1_thd1~0 := #t~ite8; [L733] 0 havoc #t~ite8; [L736] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 ~a$w_buff0~0 := #t~ite16; [L757] 1 havoc #t~ite15; [L757] 1 havoc #t~ite16; [L757] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L758] 1 #t~ite19 := ~a$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 ~a$w_buff1~0 := #t~ite19; [L758] 1 havoc #t~ite19; [L758] 1 havoc #t~ite17; [L758] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L759] 1 #t~ite22 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 ~a$w_buff0_used~0 := #t~ite22; [L759] 1 havoc #t~ite21; [L759] 1 havoc #t~ite20; [L759] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L760] 1 #t~ite25 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 ~a$w_buff1_used~0 := #t~ite25; [L760] 1 havoc #t~ite23; [L760] 1 havoc #t~ite25; [L760] 1 havoc #t~ite24; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L761] 1 #t~ite28 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 ~a$r_buff0_thd2~0 := #t~ite28; [L761] 1 havoc #t~ite26; [L761] 1 havoc #t~ite27; [L761] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L762] 1 #t~ite31 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 ~a$r_buff1_thd2~0 := #t~ite31; [L762] 1 havoc #t~ite31; [L762] 1 havoc #t~ite29; [L762] 1 havoc #t~ite30; [L763] 1 ~__unbuffered_p1_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] COND TRUE 1 0 != ~a$flush_delayed~0 % 256 [L764] 1 #t~ite32 := ~a$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 ~a~0 := #t~ite32; [L764] 1 havoc #t~ite32; [L765] 1 ~a$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256) [L768] 1 #t~ite33 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 ~a~0 := #t~ite34; [L768] 1 havoc #t~ite34; [L768] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L769] 1 #t~ite35 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 ~a$w_buff0_used~0 := #t~ite35; [L769] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L770] 1 #t~ite36 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 ~a$w_buff1_used~0 := #t~ite36; [L770] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L771] 1 #t~ite37 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 ~a$r_buff0_thd2~0 := #t~ite37; [L771] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L772] 1 #t~ite38 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 ~a$r_buff1_thd2~0 := #t~ite38; [L772] 1 havoc #t~ite38; [L775] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L793] -1 havoc #t~nondet41; [L795] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L797] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256) [L799] -1 #t~ite42 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 ~a~0 := #t~ite43; [L799] -1 havoc #t~ite42; [L799] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L800] -1 #t~ite44 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 ~a$w_buff0_used~0 := #t~ite44; [L800] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L801] -1 #t~ite45 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 ~a$w_buff1_used~0 := #t~ite45; [L801] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L802] -1 #t~ite46 := ~a$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 ~a$r_buff0_thd0~0 := #t~ite46; [L802] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L803] -1 #t~ite47 := ~a$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 ~a$r_buff1_thd0~0 := #t~ite47; [L803] -1 havoc #t~ite47; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L675] -1 int __unbuffered_p0_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0] [L677] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0] [L679] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L681] -1 int a = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0] [L682] -1 _Bool a$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0] [L683] -1 int a$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0] [L684] -1 _Bool a$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0] [L685] -1 _Bool a$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0] [L686] -1 _Bool a$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0] [L687] -1 _Bool a$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0] [L688] -1 _Bool a$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0] [L689] -1 _Bool a$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0] [L690] -1 _Bool a$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0] [L691] -1 int *a$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}] [L692] -1 int a$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0] [L693] -1 _Bool a$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0] [L694] -1 int a$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0] [L695] -1 _Bool a$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0] [L696] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0] [L697] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0] [L699] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L701] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L703] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L704] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0] [L705] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L790] -1 pthread_t t839; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L791] FCALL, FORK -1 pthread_create(&t839, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L709] 0 a$w_buff1 = a$w_buff0 [L710] 0 a$w_buff0 = 1 [L711] 0 a$w_buff1_used = a$w_buff0_used [L712] 0 a$w_buff0_used = (_Bool)1 [L792] -1 pthread_t t840; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L793] FCALL, FORK -1 pthread_create(&t840, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L714] 0 a$r_buff1_thd0 = a$r_buff0_thd0 [L715] 0 a$r_buff1_thd1 = a$r_buff0_thd1 [L716] 0 a$r_buff1_thd2 = a$r_buff0_thd2 [L717] 0 a$r_buff0_thd1 = (_Bool)1 [L720] 0 x = 1 [L723] 0 __unbuffered_p0_EAX = x [L726] 0 __unbuffered_p0_EBX = y VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0] [L729] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd1 ? a$w_buff1 : a) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0] [L743] 1 y = 1 [L746] 1 z = 1 [L749] 1 __unbuffered_p1_EAX = z [L752] 1 weak$$choice0 = __VERIFIER_nondet_pointer() [L753] 1 weak$$choice2 = __VERIFIER_nondet_pointer() [L754] 1 a$flush_delayed = weak$$choice2 [L755] 1 a$mem_tmp = a VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L756] EXPR 1 !a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff1) VAL [!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L729] 0 a = a$w_buff0_used && a$r_buff0_thd1 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd1 ? a$w_buff1 : a) [L730] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$w_buff0_used VAL [!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=1, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L730] 0 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$w_buff0_used [L756] 1 a = !a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff1) [L731] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L757] EXPR 1 weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0))=1, x=1, y=1, z=1] [L731] 0 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$w_buff1_used [L732] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$r_buff0_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0))=1, x=1, y=1, z=1] [L732] 0 a$r_buff0_thd1 = a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$r_buff0_thd1 [L733] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$r_buff1_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0))=1, x=1, y=1, z=1] [L733] 0 a$r_buff1_thd1 = a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$r_buff1_thd1 [L736] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0))=1, x=1, y=1, z=1] [L757] 1 a$w_buff0 = weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0)) [L758] EXPR 1 weak$$choice2 ? a$w_buff1 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff1 : a$w_buff1)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff1 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff1 : a$w_buff1))=0, x=1, y=1, z=1] [L758] 1 a$w_buff1 = weak$$choice2 ? a$w_buff1 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff1 : a$w_buff1)) [L759] EXPR 1 weak$$choice2 ? a$w_buff0_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used))=0, x=1, y=1, z=1] [L759] 1 a$w_buff0_used = weak$$choice2 ? a$w_buff0_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used)) [L760] EXPR 1 weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=1] [L760] 1 a$w_buff1_used = weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L761] EXPR 1 weak$$choice2 ? a$r_buff0_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff0_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$r_buff0_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff0_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2))=0, x=1, y=1, z=1] [L761] 1 a$r_buff0_thd2 = weak$$choice2 ? a$r_buff0_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff0_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2)) [L762] EXPR 1 weak$$choice2 ? a$r_buff1_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff1_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$r_buff1_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff1_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=1] [L762] 1 a$r_buff1_thd2 = weak$$choice2 ? a$r_buff1_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff1_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L763] 1 __unbuffered_p1_EBX = a VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L764] EXPR 1 a$flush_delayed ? a$mem_tmp : a VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$flush_delayed ? a$mem_tmp : a=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L764] 1 a = a$flush_delayed ? a$mem_tmp : a [L765] 1 a$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L768] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L768] EXPR 1 a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L768] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a)=0, a$w_buff1=0, a$w_buff1_used=0, a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L768] 1 a = a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a) [L769] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L769] 1 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used [L770] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$w_buff1_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L770] 1 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$w_buff1_used [L771] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L771] 1 a$r_buff0_thd2 = a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2 [L772] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$r_buff1_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$r_buff1_thd2=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L772] 1 a$r_buff1_thd2 = a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$r_buff1_thd2 [L775] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L795] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L799] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L799] EXPR -1 a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L799] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L799] -1 a = a$w_buff0_used && a$r_buff0_thd0 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a) [L800] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L800] -1 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$w_buff0_used [L801] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L801] -1 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$w_buff1_used [L802] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L802] -1 a$r_buff0_thd0 = a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$r_buff0_thd0 [L803] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L803] -1 a$r_buff1_thd0 = a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$r_buff1_thd0 [L806] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 1 && __unbuffered_p0_EBX == 0 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] ----- [2018-11-23 03:16:18,429 INFO L305 ceAbstractionStarter]: Did not count any witness invariants because Icfg is not BoogieIcfg [2018-11-23 03:16:18,431 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 03:16:18 BasicIcfg [2018-11-23 03:16:18,431 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 03:16:18,431 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 03:16:18,431 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 03:16:18,431 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 03:16:18,432 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 03:15:58" (3/4) ... [2018-11-23 03:16:18,434 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [485] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [363] L-1-->L671: Formula: (= |v_#valid_9| (store |v_#valid_10| 0 0)) InVars {#valid=|v_#valid_10|} OutVars{#valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [530] L671-->L673: Formula: (= v_~__unbuffered_cnt~0_6 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [389] L673-->L675: Formula: (= v_~__unbuffered_p0_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 [429] L675-->L677: Formula: (= v_~__unbuffered_p0_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p0_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [?] -1 [494] L677-->L679: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [536] L679-->L681: Formula: (= v_~__unbuffered_p1_EBX~0_2 0) InVars {} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 [393] L681-->L682: Formula: (= v_~a~0_11 0) InVars {} OutVars{~a~0=v_~a~0_11} AuxVars[] AssignedVars[~a~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [?] -1 [529] L682-->L683: Formula: (= v_~a$flush_delayed~0_5 0) InVars {} OutVars{~a$flush_delayed~0=v_~a$flush_delayed~0_5} AuxVars[] AssignedVars[~a$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [?] -1 [458] L683-->L684: Formula: (= v_~a$mem_tmp~0_3 0) InVars {} OutVars{~a$mem_tmp~0=v_~a$mem_tmp~0_3} AuxVars[] AssignedVars[~a$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [?] -1 [386] L684-->L685: Formula: (= v_~a$r_buff0_thd0~0_2 0) InVars {} OutVars{~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_2} AuxVars[] AssignedVars[~a$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [?] -1 [504] L685-->L686: Formula: (= v_~a$r_buff0_thd1~0_14 0) InVars {} OutVars{~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_14} AuxVars[] AssignedVars[~a$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [?] -1 [428] L686-->L687: Formula: (= v_~a$r_buff0_thd2~0_43 0) InVars {} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_43} AuxVars[] AssignedVars[~a$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [?] -1 [380] L687-->L688: Formula: (= v_~a$r_buff1_thd0~0_2 0) InVars {} OutVars{~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_2} AuxVars[] AssignedVars[~a$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [?] -1 [493] L688-->L689: Formula: (= v_~a$r_buff1_thd1~0_9 0) InVars {} OutVars{~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~a$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [?] -1 [421] L689-->L690: Formula: (= v_~a$r_buff1_thd2~0_25 0) InVars {} OutVars{~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_25} AuxVars[] AssignedVars[~a$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [?] -1 [535] L690-->L691: Formula: (= v_~a$read_delayed~0_1 0) InVars {} OutVars{~a$read_delayed~0=v_~a$read_delayed~0_1} AuxVars[] AssignedVars[~a$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [?] -1 [466] L691-->L692: Formula: (and (= v_~a$read_delayed_var~0.base_1 0) (= v_~a$read_delayed_var~0.offset_1 0)) InVars {} OutVars{~a$read_delayed_var~0.base=v_~a$read_delayed_var~0.base_1, ~a$read_delayed_var~0.offset=v_~a$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~a$read_delayed_var~0.offset, ~a$read_delayed_var~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a~0=0] [?] -1 [392] L692-->L693: Formula: (= v_~a$w_buff0~0_11 0) InVars {} OutVars{~a$w_buff0~0=v_~a$w_buff0~0_11} AuxVars[] AssignedVars[~a$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [?] -1 [526] L693-->L694: Formula: (= v_~a$w_buff0_used~0_55 0) InVars {} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_55} AuxVars[] AssignedVars[~a$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [?] -1 [457] L694-->L695: Formula: (= v_~a$w_buff1~0_10 0) InVars {} OutVars{~a$w_buff1~0=v_~a$w_buff1~0_10} AuxVars[] AssignedVars[~a$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [?] -1 [385] L695-->L696: Formula: (= v_~a$w_buff1_used~0_32 0) InVars {} OutVars{~a$w_buff1_used~0=v_~a$w_buff1_used~0_32} AuxVars[] AssignedVars[~a$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [?] -1 [502] L696-->L697: Formula: (= v_~main$tmp_guard0~0_1 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [?] -1 [425] L697-->L699: Formula: (= v_~main$tmp_guard1~0_1 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_1} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [491] L699-->L701: Formula: (= v_~x~0_2 0) InVars {} OutVars{~x~0=v_~x~0_2} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [534] L701-->L703: Formula: (= v_~y~0_3 0) InVars {} OutVars{~y~0=v_~y~0_3} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 [415] L703-->L704: Formula: (= v_~z~0_2 0) InVars {} OutVars{~z~0=v_~z~0_2} AuxVars[] AssignedVars[~z~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [523] L704-->L705: Formula: (= v_~weak$$choice0~0_2 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [456] L705-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [527] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [520] L-1-2-->L790: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_1|, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_1|, ULTIMATE.start_main_~#t840~0.offset=|v_ULTIMATE.start_main_~#t840~0.offset_1|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_1|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_1|, ULTIMATE.start_main_~#t839~0.base=|v_ULTIMATE.start_main_~#t839~0.base_1|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_1|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_1|, ULTIMATE.start_main_~#t840~0.base=|v_ULTIMATE.start_main_~#t840~0.base_1|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_1|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_1|, ULTIMATE.start_main_~#t839~0.offset=|v_ULTIMATE.start_main_~#t839~0.offset_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet40, ULTIMATE.start_main_#t~nondet41, ULTIMATE.start_main_~#t840~0.offset, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_~#t839~0.offset, ULTIMATE.start_main_~#t839~0.base, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_~#t840~0.base, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [477] L790-->L790-1: Formula: (and (not (= |v_ULTIMATE.start_main_~#t839~0.base_2| 0)) (= 0 |v_ULTIMATE.start_main_~#t839~0.offset_2|) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t839~0.base_2|) 0) (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t839~0.base_2| 4) |v_#length_1|) (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t839~0.base_2| 1) |v_#valid_1|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{ULTIMATE.start_main_~#t839~0.offset=|v_ULTIMATE.start_main_~#t839~0.offset_2|, #length=|v_#length_1|, ULTIMATE.start_main_~#t839~0.base=|v_ULTIMATE.start_main_~#t839~0.base_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid, ULTIMATE.start_main_~#t839~0.offset, #length, ULTIMATE.start_main_~#t839~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [478] L790-1-->L791: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t839~0.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t839~0.base_3|) |v_ULTIMATE.start_main_~#t839~0.offset_3| 0))) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t839~0.offset=|v_ULTIMATE.start_main_~#t839~0.offset_3|, ULTIMATE.start_main_~#t839~0.base=|v_ULTIMATE.start_main_~#t839~0.base_3|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t839~0.offset=|v_ULTIMATE.start_main_~#t839~0.offset_3|, ULTIMATE.start_main_~#t839~0.base=|v_ULTIMATE.start_main_~#t839~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 [651] L791-->P0ENTRY: Formula: (and (= 0 |v_Thread1_P0_#in~arg.base_3|) (= 0 v_Thread1_P0_thidvar0_2) (= 0 |v_Thread1_P0_#in~arg.offset_3|)) InVars {} OutVars{Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_3|, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_3|, Thread1_P0_thidvar0=v_Thread1_P0_thidvar0_2} AuxVars[] AssignedVars[Thread1_P0_#in~arg.base, Thread1_P0_#in~arg.offset, Thread1_P0_thidvar0] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 [538] P0ENTRY-->L4: Formula: (and (= v_Thread1_P0_~arg.base_1 |v_Thread1_P0_#in~arg.base_1|) (= v_Thread1_P0_~arg.offset_1 |v_Thread1_P0_#in~arg.offset_1|) (= v_~a$w_buff1_used~0_1 v_~a$w_buff0_used~0_2) (= v_~a$w_buff0_used~0_1 1) (= v_~a$w_buff0~0_1 1) (= v_Thread1_P0___VERIFIER_assert_~expression_1 |v_Thread1_P0___VERIFIER_assert_#in~expression_1|) (= v_~a$w_buff1~0_1 v_~a$w_buff0~0_2) (= |v_Thread1_P0___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~a$w_buff1_used~0_1 256))) (not (= (mod v_~a$w_buff0_used~0_1 256) 0)))) 1 0))) InVars {Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_2, Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, ~a$w_buff0~0=v_~a$w_buff0~0_2} OutVars{Thread1_P0___VERIFIER_assert_~expression=v_Thread1_P0___VERIFIER_assert_~expression_1, Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, ~a$w_buff1~0=v_~a$w_buff1~0_1, Thread1_P0_~arg.offset=v_Thread1_P0_~arg.offset_1, ~a$w_buff0~0=v_~a$w_buff0~0_1, Thread1_P0___VERIFIER_assert_#in~expression=|v_Thread1_P0___VERIFIER_assert_#in~expression_1|, Thread1_P0_~arg.base=v_Thread1_P0_~arg.base_1, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_1, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_1} AuxVars[] AssignedVars[Thread1_P0___VERIFIER_assert_~expression, ~a$w_buff1~0, Thread1_P0_~arg.offset, ~a$w_buff0~0, Thread1_P0___VERIFIER_assert_#in~expression, Thread1_P0_~arg.base, ~a$w_buff0_used~0, ~a$w_buff1_used~0] VAL [Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [411] L791-1-->L792: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet40] VAL [Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [517] L792-->L792-1: Formula: (and (= |v_ULTIMATE.start_main_~#t840~0.offset_2| 0) (= |v_#valid_3| (store |v_#valid_4| |v_ULTIMATE.start_main_~#t840~0.base_2| 1)) (= 0 (select |v_#valid_4| |v_ULTIMATE.start_main_~#t840~0.base_2|)) (not (= |v_ULTIMATE.start_main_~#t840~0.base_2| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t840~0.base_2| 4))) InVars {#length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{#length=|v_#length_3|, ULTIMATE.start_main_~#t840~0.offset=|v_ULTIMATE.start_main_~#t840~0.offset_2|, ULTIMATE.start_main_~#t840~0.base=|v_ULTIMATE.start_main_~#t840~0.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t840~0.offset, #valid, #length, ULTIMATE.start_main_~#t840~0.base] VAL [Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [518] L792-1-->L793: Formula: (= |v_#memory_int_3| (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t840~0.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t840~0.base_3|) |v_ULTIMATE.start_main_~#t840~0.offset_3| 1))) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t840~0.offset=|v_ULTIMATE.start_main_~#t840~0.offset_3|, ULTIMATE.start_main_~#t840~0.base=|v_ULTIMATE.start_main_~#t840~0.base_3|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t840~0.offset=|v_ULTIMATE.start_main_~#t840~0.offset_3|, ULTIMATE.start_main_~#t840~0.base=|v_ULTIMATE.start_main_~#t840~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 [650] L793-->P1ENTRY: Formula: (and (= 0 |v_Thread0_P1_#in~arg.offset_3|) (= 1 v_Thread0_P1_thidvar0_2) (= 0 |v_Thread0_P1_#in~arg.base_3|)) InVars {} OutVars{Thread0_P1_thidvar0=v_Thread0_P1_thidvar0_2, Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_3|, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P1_thidvar0, Thread0_P1_#in~arg.base, Thread0_P1_#in~arg.offset] VAL [Thread0_P1_thidvar0=1, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 [540] L4-->L4-3: Formula: (not (= 0 v_Thread1_P0___VERIFIER_assert_~expression_3)) InVars {Thread1_P0___VERIFIER_assert_~expression=v_Thread1_P0___VERIFIER_assert_~expression_3} OutVars{Thread1_P0___VERIFIER_assert_~expression=v_Thread1_P0___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 [543] L4-3-->L729: Formula: (and (= v_~__unbuffered_p0_EAX~0_1 v_~x~0_1) (= v_~a$r_buff1_thd1~0_1 v_~a$r_buff0_thd1~0_2) (= v_~a$r_buff1_thd0~0_1 v_~a$r_buff0_thd0~0_1) (= v_~a$r_buff1_thd2~0_1 v_~a$r_buff0_thd2~0_1) (= v_~a$r_buff0_thd1~0_1 1) (= v_~x~0_1 1) (= v_~__unbuffered_p0_EBX~0_1 v_~y~0_1)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_1, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_2, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_1, ~y~0=v_~y~0_1} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_1, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_1, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_1, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_1, ~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_1, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_1, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_1, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_1, ~y~0=v_~y~0_1, ~x~0=v_~x~0_1} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, ~__unbuffered_p0_EBX~0, ~a$r_buff1_thd1~0, ~a$r_buff1_thd2~0, ~a$r_buff1_thd0~0, ~a$r_buff0_thd1~0, ~x~0] VAL [Thread0_P1_thidvar0=1, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [?] 0 [544] L729-->L729-5: Formula: (and (not (= (mod v_~a$r_buff0_thd1~0_3 256) 0)) (= |v_Thread1_P0_#t~ite4_1| v_~a$w_buff0~0_3) (not (= 0 (mod v_~a$w_buff0_used~0_3 256)))) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_3, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_3, ~a$w_buff0~0=v_~a$w_buff0~0_3} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_3, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_3, ~a$w_buff0~0=v_~a$w_buff0~0_3, Thread1_P0_#t~ite4=|v_Thread1_P0_#t~ite4_1|} AuxVars[] AssignedVars[Thread1_P0_#t~ite4] VAL [Thread0_P1_thidvar0=1, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite4|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [?] 1 [565] P1ENTRY-->L756: Formula: (and (= v_Thread0_P1_~arg.offset_1 |v_Thread0_P1_#in~arg.offset_1|) (= v_~z~0_1 1) (= v_~a$flush_delayed~0_1 v_~weak$$choice2~0_7) (= v_Thread0_P1_~arg.base_1 |v_Thread0_P1_#in~arg.base_1|) (= v_~a$mem_tmp~0_1 v_~a~0_3) (= v_~weak$$choice0~0_1 (ite (= 0 (+ |v_Thread0_P1_#t~nondet10.base_1| |v_Thread0_P1_#t~nondet10.offset_1|)) 0 1)) (= v_~__unbuffered_p1_EAX~0_1 v_~z~0_1) (= v_~y~0_2 1) (= v_~weak$$choice2~0_7 (ite (= (+ |v_Thread0_P1_#t~nondet11.offset_1| |v_Thread0_P1_#t~nondet11.base_1|) 0) 0 1))) InVars {~a~0=v_~a~0_3, Thread0_P1_#t~nondet10.offset=|v_Thread0_P1_#t~nondet10.offset_1|, Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_1|, Thread0_P1_#t~nondet10.base=|v_Thread0_P1_#t~nondet10.base_1|, Thread0_P1_#t~nondet11.base=|v_Thread0_P1_#t~nondet11.base_1|, Thread0_P1_#t~nondet11.offset=|v_Thread0_P1_#t~nondet11.offset_1|, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_1|} OutVars{Thread0_P1_#in~arg.base=|v_Thread0_P1_#in~arg.base_1|, Thread0_P1_#t~nondet10.base=|v_Thread0_P1_#t~nondet10.base_2|, Thread0_P1_~arg.offset=v_Thread0_P1_~arg.offset_1, Thread0_P1_#t~nondet11.base=|v_Thread0_P1_#t~nondet11.base_2|, Thread0_P1_#in~arg.offset=|v_Thread0_P1_#in~arg.offset_1|, ~a$mem_tmp~0=v_~a$mem_tmp~0_1, ~a~0=v_~a~0_3, ~weak$$choice0~0=v_~weak$$choice0~0_1, Thread0_P1_#t~nondet10.offset=|v_Thread0_P1_#t~nondet10.offset_2|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, ~a$flush_delayed~0=v_~a$flush_delayed~0_1, Thread0_P1_~arg.base=v_Thread0_P1_~arg.base_1, Thread0_P1_#t~nondet11.offset=|v_Thread0_P1_#t~nondet11.offset_2|, ~z~0=v_~z~0_1, ~weak$$choice2~0=v_~weak$$choice2~0_7, ~y~0=v_~y~0_2} AuxVars[] AssignedVars[Thread0_P1_#t~nondet10.base, Thread0_P1_~arg.offset, Thread0_P1_#t~nondet11.base, ~a$mem_tmp~0, ~weak$$choice0~0, Thread0_P1_#t~nondet10.offset, ~__unbuffered_p1_EAX~0, ~a$flush_delayed~0, Thread0_P1_~arg.base, Thread0_P1_#t~nondet11.offset, ~z~0, ~weak$$choice2~0, ~y~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite4|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [566] L756-->L756-5: Formula: (and (let ((.cse0 (= 0 (mod v_~a$r_buff0_thd2~0_15 256)))) (or (and .cse0 (= 0 (mod v_~a$w_buff1_used~0_17 256))) (and .cse0 (= (mod v_~a$r_buff1_thd2~0_9 256) 0)) (= 0 (mod v_~a$w_buff0_used~0_26 256)))) (= |v_Thread0_P1_#t~ite13_1| v_~a~0_4)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_15, ~a~0=v_~a~0_4, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_26, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_17, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_9} OutVars{~a~0=v_~a~0_4, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_9, ~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_15, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_26, Thread0_P1_#t~ite13=|v_Thread0_P1_#t~ite13_1|, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_17} AuxVars[] AssignedVars[Thread0_P1_#t~ite13] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite13|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite4|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [546] L729-5-->L730: Formula: (= v_~a~0_2 |v_Thread1_P0_#t~ite4_2|) InVars {Thread1_P0_#t~ite4=|v_Thread1_P0_#t~ite4_2|} OutVars{~a~0=v_~a~0_2, Thread1_P0_#t~ite3=|v_Thread1_P0_#t~ite3_1|, Thread1_P0_#t~ite4=|v_Thread1_P0_#t~ite4_3|} AuxVars[] AssignedVars[~a~0, Thread1_P0_#t~ite3, Thread1_P0_#t~ite4] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite13|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [549] L730-->L730-2: Formula: (and (= |v_Thread1_P0_#t~ite5_1| 0) (not (= (mod v_~a$r_buff0_thd1~0_5 256) 0)) (not (= (mod v_~a$w_buff0_used~0_5 256) 0))) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_5, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_5} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_5, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_5, Thread1_P0_#t~ite5=|v_Thread1_P0_#t~ite5_1|} AuxVars[] AssignedVars[Thread1_P0_#t~ite5] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite13|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite5|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [552] L730-2-->L731: Formula: (= v_~a$w_buff0_used~0_7 |v_Thread1_P0_#t~ite5_3|) InVars {Thread1_P0_#t~ite5=|v_Thread1_P0_#t~ite5_3|} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_7, Thread1_P0_#t~ite5=|v_Thread1_P0_#t~ite5_4|} AuxVars[] AssignedVars[~a$w_buff0_used~0, Thread1_P0_#t~ite5] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite13|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [568] L756-5-->L757: Formula: (= v_~a~0_6 |v_Thread0_P1_#t~ite13_2|) InVars {Thread0_P1_#t~ite13=|v_Thread0_P1_#t~ite13_2|} OutVars{~a~0=v_~a~0_6, Thread0_P1_#t~ite12=|v_Thread0_P1_#t~ite12_1|, Thread0_P1_#t~ite13=|v_Thread0_P1_#t~ite13_3|} AuxVars[] AssignedVars[~a~0, Thread0_P1_#t~ite12, Thread0_P1_#t~ite13] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [554] L731-->L731-2: Formula: (and (= |v_Thread1_P0_#t~ite6_2| v_~a$w_buff1_used~0_5) (or (= (mod v_~a$w_buff1_used~0_5 256) 0) (= (mod v_~a$r_buff1_thd1~0_5 256) 0)) (or (= 0 (mod v_~a$r_buff0_thd1~0_8 256)) (= 0 (mod v_~a$w_buff0_used~0_9 256)))) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_9, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_8, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_5, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_5} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_9, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_8, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_5, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_5, Thread1_P0_#t~ite6=|v_Thread1_P0_#t~ite6_2|} AuxVars[] AssignedVars[Thread1_P0_#t~ite6] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite6|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [571] L757-->L757-8: Formula: (and (not (= (mod v_~weak$$choice2~0_8 256) 0)) (= |v_Thread0_P1_#t~ite16_1| v_~a$w_buff0~0_5)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_8, ~a$w_buff0~0=v_~a$w_buff0~0_5} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_8, ~a$w_buff0~0=v_~a$w_buff0~0_5, Thread0_P1_#t~ite16=|v_Thread0_P1_#t~ite16_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite16] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite6|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [555] L731-2-->L732: Formula: (= v_~a$w_buff1_used~0_6 |v_Thread1_P0_#t~ite6_3|) InVars {Thread1_P0_#t~ite6=|v_Thread1_P0_#t~ite6_3|} OutVars{~a$w_buff1_used~0=v_~a$w_buff1_used~0_6, Thread1_P0_#t~ite6=|v_Thread1_P0_#t~ite6_4|} AuxVars[] AssignedVars[~a$w_buff1_used~0, Thread1_P0_#t~ite6] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [557] L732-->L732-2: Formula: (and (or (= 0 (mod v_~a$r_buff0_thd1~0_10 256)) (= 0 (mod v_~a$w_buff0_used~0_11 256))) (= |v_Thread1_P0_#t~ite7_2| v_~a$r_buff0_thd1~0_10)) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_11, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_10} OutVars{Thread1_P0_#t~ite7=|v_Thread1_P0_#t~ite7_2|, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_11, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_10} AuxVars[] AssignedVars[Thread1_P0_#t~ite7] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite7|=1, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [558] L732-2-->L733: Formula: (= v_~a$r_buff0_thd1~0_11 |v_Thread1_P0_#t~ite7_3|) InVars {Thread1_P0_#t~ite7=|v_Thread1_P0_#t~ite7_3|} OutVars{Thread1_P0_#t~ite7=|v_Thread1_P0_#t~ite7_4|, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_11} AuxVars[] AssignedVars[Thread1_P0_#t~ite7, ~a$r_buff0_thd1~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [560] L733-->L733-2: Formula: (and (or (= 0 (mod v_~a$w_buff0_used~0_13 256)) (= (mod v_~a$r_buff0_thd1~0_13 256) 0)) (= |v_Thread1_P0_#t~ite8_2| v_~a$r_buff1_thd1~0_7) (or (= 0 (mod v_~a$r_buff1_thd1~0_7 256)) (= (mod v_~a$w_buff1_used~0_8 256) 0))) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_13, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_13, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_8, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_7} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_13, Thread1_P0_#t~ite8=|v_Thread1_P0_#t~ite8_2|, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_13, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_8, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_7} AuxVars[] AssignedVars[Thread1_P0_#t~ite8] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0_#t~ite8|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 [561] L733-2-->L738: Formula: (and (= v_~a$r_buff1_thd1~0_8 |v_Thread1_P0_#t~ite8_3|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1))) InVars {Thread1_P0_#t~ite8=|v_Thread1_P0_#t~ite8_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{Thread1_P0_#t~ite8=|v_Thread1_P0_#t~ite8_4|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_8} AuxVars[] AssignedVars[~a$r_buff1_thd1~0, Thread1_P0_#t~ite8, ~__unbuffered_cnt~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite16|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [574] L757-8-->L758: Formula: (= v_~a$w_buff0~0_10 |v_Thread0_P1_#t~ite16_2|) InVars {Thread0_P1_#t~ite16=|v_Thread0_P1_#t~ite16_2|} OutVars{Thread0_P1_#t~ite14=|v_Thread0_P1_#t~ite14_1|, ~a$w_buff0~0=v_~a$w_buff0~0_10, Thread0_P1_#t~ite15=|v_Thread0_P1_#t~ite15_1|, Thread0_P1_#t~ite16=|v_Thread0_P1_#t~ite16_3|} AuxVars[] AssignedVars[~a$w_buff0~0, Thread0_P1_#t~ite14, Thread0_P1_#t~ite15, Thread0_P1_#t~ite16] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [577] L758-->L758-8: Formula: (and (= |v_Thread0_P1_#t~ite19_1| v_~a$w_buff1~0_5) (not (= (mod v_~weak$$choice2~0_10 256) 0))) InVars {~a$w_buff1~0=v_~a$w_buff1~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_10} OutVars{Thread0_P1_#t~ite19=|v_Thread0_P1_#t~ite19_1|, ~a$w_buff1~0=v_~a$w_buff1~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_10} AuxVars[] AssignedVars[Thread0_P1_#t~ite19] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite19|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [582] L758-8-->L759: Formula: (= v_~a$w_buff1~0_9 |v_Thread0_P1_#t~ite19_2|) InVars {Thread0_P1_#t~ite19=|v_Thread0_P1_#t~ite19_2|} OutVars{Thread0_P1_#t~ite18=|v_Thread0_P1_#t~ite18_1|, Thread0_P1_#t~ite19=|v_Thread0_P1_#t~ite19_3|, ~a$w_buff1~0=v_~a$w_buff1~0_9, Thread0_P1_#t~ite17=|v_Thread0_P1_#t~ite17_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite18, Thread0_P1_#t~ite19, ~a$w_buff1~0, Thread0_P1_#t~ite17] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [586] L759-->L759-8: Formula: (and (not (= (mod v_~weak$$choice2~0_12 256) 0)) (= |v_Thread0_P1_#t~ite22_1| v_~a$w_buff0_used~0_50)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_12, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_50} OutVars{Thread0_P1_#t~ite22=|v_Thread0_P1_#t~ite22_1|, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_50, ~weak$$choice2~0=v_~weak$$choice2~0_12} AuxVars[] AssignedVars[Thread0_P1_#t~ite22] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite22|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [591] L759-8-->L760: Formula: (= v_~a$w_buff0_used~0_15 |v_Thread0_P1_#t~ite22_2|) InVars {Thread0_P1_#t~ite22=|v_Thread0_P1_#t~ite22_2|} OutVars{Thread0_P1_#t~ite22=|v_Thread0_P1_#t~ite22_3|, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_15, Thread0_P1_#t~ite21=|v_Thread0_P1_#t~ite21_1|, Thread0_P1_#t~ite20=|v_Thread0_P1_#t~ite20_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite20, Thread0_P1_#t~ite22, ~a$w_buff0_used~0, Thread0_P1_#t~ite21] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [595] L760-->L760-8: Formula: (and (= |v_Thread0_P1_#t~ite25_1| v_~a$w_buff1_used~0_9) (not (= (mod v_~weak$$choice2~0_1 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_1, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_9} OutVars{~a$w_buff1_used~0=v_~a$w_buff1_used~0_9, ~weak$$choice2~0=v_~weak$$choice2~0_1, Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite25] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite25|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [600] L760-8-->L761: Formula: (= v_~a$w_buff1_used~0_12 |v_Thread0_P1_#t~ite25_2|) InVars {Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_2|} OutVars{Thread0_P1_#t~ite24=|v_Thread0_P1_#t~ite24_1|, Thread0_P1_#t~ite23=|v_Thread0_P1_#t~ite23_1|, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_12, Thread0_P1_#t~ite25=|v_Thread0_P1_#t~ite25_3|} AuxVars[] AssignedVars[Thread0_P1_#t~ite24, Thread0_P1_#t~ite23, ~a$w_buff1_used~0, Thread0_P1_#t~ite25] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [604] L761-->L761-8: Formula: (and (= |v_Thread0_P1_#t~ite28_1| v_~a$r_buff0_thd2~0_7) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_3} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_3, Thread0_P1_#t~ite28=|v_Thread0_P1_#t~ite28_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite28] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite28|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [609] L761-8-->L762: Formula: (= v_~a$r_buff0_thd2~0_12 |v_Thread0_P1_#t~ite28_2|) InVars {Thread0_P1_#t~ite28=|v_Thread0_P1_#t~ite28_2|} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_12, Thread0_P1_#t~ite26=|v_Thread0_P1_#t~ite26_1|, Thread0_P1_#t~ite28=|v_Thread0_P1_#t~ite28_3|, Thread0_P1_#t~ite27=|v_Thread0_P1_#t~ite27_1|} AuxVars[] AssignedVars[~a$r_buff0_thd2~0, Thread0_P1_#t~ite26, Thread0_P1_#t~ite28, Thread0_P1_#t~ite27] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [613] L762-->L762-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_5 256))) (= |v_Thread0_P1_#t~ite31_1| v_~a$r_buff1_thd2~0_6)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_6} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_5, Thread0_P1_#t~ite31=|v_Thread0_P1_#t~ite31_1|, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_6} AuxVars[] AssignedVars[Thread0_P1_#t~ite31] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite31|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [618] L762-8-->L764: Formula: (and (= v_~a$r_buff1_thd2~0_11 |v_Thread0_P1_#t~ite31_2|) (= v_~__unbuffered_p1_EBX~0_1 v_~a~0_5)) InVars {~a~0=v_~a~0_5, Thread0_P1_#t~ite31=|v_Thread0_P1_#t~ite31_2|} OutVars{~a~0=v_~a~0_5, Thread0_P1_#t~ite29=|v_Thread0_P1_#t~ite29_1|, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_1, Thread0_P1_#t~ite31=|v_Thread0_P1_#t~ite31_3|, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_11, Thread0_P1_#t~ite30=|v_Thread0_P1_#t~ite30_1|} AuxVars[] AssignedVars[Thread0_P1_#t~ite29, ~__unbuffered_p1_EBX~0, Thread0_P1_#t~ite31, ~a$r_buff1_thd2~0, Thread0_P1_#t~ite30] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [622] L764-->L764-2: Formula: (and (not (= 0 (mod v_~a$flush_delayed~0_2 256))) (= |v_Thread0_P1_#t~ite32_1| v_~a$mem_tmp~0_2)) InVars {~a$mem_tmp~0=v_~a$mem_tmp~0_2, ~a$flush_delayed~0=v_~a$flush_delayed~0_2} OutVars{~a$mem_tmp~0=v_~a$mem_tmp~0_2, Thread0_P1_#t~ite32=|v_Thread0_P1_#t~ite32_1|, ~a$flush_delayed~0=v_~a$flush_delayed~0_2} AuxVars[] AssignedVars[Thread0_P1_#t~ite32] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite32|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [627] L764-2-->L768: Formula: (and (= v_~a~0_8 |v_Thread0_P1_#t~ite32_3|) (= v_~a$flush_delayed~0_4 0)) InVars {Thread0_P1_#t~ite32=|v_Thread0_P1_#t~ite32_3|} OutVars{~a~0=v_~a~0_8, Thread0_P1_#t~ite32=|v_Thread0_P1_#t~ite32_4|, ~a$flush_delayed~0=v_~a$flush_delayed~0_4} AuxVars[] AssignedVars[~a~0, ~a$flush_delayed~0, Thread0_P1_#t~ite32] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [630] L768-->L768-2: Formula: (or (= 0 (mod v_~a$r_buff0_thd2~0_24 256)) (= (mod v_~a$w_buff0_used~0_35 256) 0)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_24, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_35} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_24, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_35} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [633] L768-2-->L768-4: Formula: (and (or (= 0 (mod v_~a$w_buff1_used~0_22 256)) (= (mod v_~a$r_buff1_thd2~0_15 256) 0)) (= |v_Thread0_P1_#t~ite33_3| v_~a~0_9)) InVars {~a~0=v_~a~0_9, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_22, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_15} OutVars{Thread0_P1_#t~ite33=|v_Thread0_P1_#t~ite33_3|, ~a~0=v_~a~0_9, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_22, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_15} AuxVars[] AssignedVars[Thread0_P1_#t~ite33] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite33|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [636] L768-4-->L768-5: Formula: (= |v_Thread0_P1_#t~ite34_4| |v_Thread0_P1_#t~ite33_4|) InVars {Thread0_P1_#t~ite33=|v_Thread0_P1_#t~ite33_4|} OutVars{Thread0_P1_#t~ite33=|v_Thread0_P1_#t~ite33_4|, Thread0_P1_#t~ite34=|v_Thread0_P1_#t~ite34_4|} AuxVars[] AssignedVars[Thread0_P1_#t~ite34] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite33|=0, |Thread0_P1_#t~ite34|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [631] L768-5-->L769: Formula: (= v_~a~0_10 |v_Thread0_P1_#t~ite34_2|) InVars {Thread0_P1_#t~ite34=|v_Thread0_P1_#t~ite34_2|} OutVars{Thread0_P1_#t~ite33=|v_Thread0_P1_#t~ite33_1|, ~a~0=v_~a~0_10, Thread0_P1_#t~ite34=|v_Thread0_P1_#t~ite34_3|} AuxVars[] AssignedVars[~a~0, Thread0_P1_#t~ite33, Thread0_P1_#t~ite34] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [635] L769-->L769-2: Formula: (and (or (= 0 (mod v_~a$r_buff0_thd2~0_28 256)) (= (mod v_~a$w_buff0_used~0_39 256) 0)) (= |v_Thread0_P1_#t~ite35_2| v_~a$w_buff0_used~0_39)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_28, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_39} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_28, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_39, Thread0_P1_#t~ite35=|v_Thread0_P1_#t~ite35_2|} AuxVars[] AssignedVars[Thread0_P1_#t~ite35] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite35|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [637] L769-2-->L770: Formula: (= v_~a$w_buff0_used~0_40 |v_Thread0_P1_#t~ite35_3|) InVars {Thread0_P1_#t~ite35=|v_Thread0_P1_#t~ite35_3|} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_40, Thread0_P1_#t~ite35=|v_Thread0_P1_#t~ite35_4|} AuxVars[] AssignedVars[~a$w_buff0_used~0, Thread0_P1_#t~ite35] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [639] L770-->L770-2: Formula: (and (or (= (mod v_~a$r_buff1_thd2~0_19 256) 0) (= (mod v_~a$w_buff1_used~0_26 256) 0)) (or (= 0 (mod v_~a$r_buff0_thd2~0_32 256)) (= 0 (mod v_~a$w_buff0_used~0_44 256))) (= |v_Thread0_P1_#t~ite36_2| v_~a$w_buff1_used~0_26)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_32, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_44, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_26, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_19} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_32, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_44, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_26, Thread0_P1_#t~ite36=|v_Thread0_P1_#t~ite36_2|, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_19} AuxVars[] AssignedVars[Thread0_P1_#t~ite36] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite36|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [640] L770-2-->L771: Formula: (= v_~a$w_buff1_used~0_27 |v_Thread0_P1_#t~ite36_3|) InVars {Thread0_P1_#t~ite36=|v_Thread0_P1_#t~ite36_3|} OutVars{Thread0_P1_#t~ite36=|v_Thread0_P1_#t~ite36_4|, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_27} AuxVars[] AssignedVars[~a$w_buff1_used~0, Thread0_P1_#t~ite36] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [642] L771-->L771-2: Formula: (and (or (= 0 (mod v_~a$w_buff0_used~0_48 256)) (= 0 (mod v_~a$r_buff0_thd2~0_36 256))) (= |v_Thread0_P1_#t~ite37_2| v_~a$r_buff0_thd2~0_36)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_36, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_48} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_36, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_48, Thread0_P1_#t~ite37=|v_Thread0_P1_#t~ite37_2|} AuxVars[] AssignedVars[Thread0_P1_#t~ite37] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite37|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [643] L771-2-->L772: Formula: (= v_~a$r_buff0_thd2~0_37 |v_Thread0_P1_#t~ite37_3|) InVars {Thread0_P1_#t~ite37=|v_Thread0_P1_#t~ite37_3|} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_37, Thread0_P1_#t~ite37=|v_Thread0_P1_#t~ite37_4|} AuxVars[] AssignedVars[~a$r_buff0_thd2~0, Thread0_P1_#t~ite37] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [645] L772-->L772-2: Formula: (and (or (= (mod v_~a$w_buff0_used~0_51 256) 0) (= (mod v_~a$r_buff0_thd2~0_39 256) 0)) (or (= 0 (mod v_~a$w_buff1_used~0_29 256)) (= 0 (mod v_~a$r_buff1_thd2~0_21 256))) (= |v_Thread0_P1_#t~ite38_2| v_~a$r_buff1_thd2~0_21)) InVars {~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_39, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_51, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_29, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_21} OutVars{~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_39, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_51, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_29, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_21, Thread0_P1_#t~ite38=|v_Thread0_P1_#t~ite38_2|} AuxVars[] AssignedVars[Thread0_P1_#t~ite38] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread0_P1_#t~ite38|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 [646] L772-2-->L777: Formula: (and (= v_~a$r_buff1_thd2~0_22 |v_Thread0_P1_#t~ite38_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4, Thread0_P1_#t~ite38=|v_Thread0_P1_#t~ite38_3|} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_22, Thread0_P1_#t~ite38=|v_Thread0_P1_#t~ite38_4|} AuxVars[] AssignedVars[~a$r_buff1_thd2~0, ~__unbuffered_cnt~0, Thread0_P1_#t~ite38] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [451] L793-1-->L797: Formula: (= v_~main$tmp_guard0~0_2 (ite (= (ite (= v_~__unbuffered_cnt~0_5 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_2|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet41, ~main$tmp_guard0~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [367] L797-->L799: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_3 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [438] L799-->L799-2: Formula: (or (= 0 (mod v_~a$r_buff0_thd0~0_4 256)) (= 0 (mod v_~a$w_buff0_used~0_57 256))) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_57, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_4} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_57, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_4} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [419] L799-2-->L799-4: Formula: (and (= |v_ULTIMATE.start_main_#t~ite42_3| v_~a~0_12) (or (= (mod v_~a$w_buff1_used~0_34 256) 0) (= (mod v_~a$r_buff1_thd0~0_4 256) 0))) InVars {~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_4, ~a~0=v_~a~0_12, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_34} OutVars{~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_4, ~a~0=v_~a~0_12, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_34, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [423] L799-4-->L799-5: Formula: (= |v_ULTIMATE.start_main_#t~ite43_3| |v_ULTIMATE.start_main_#t~ite42_4|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [424] L799-5-->L800: Formula: (= v_~a~0_13 |v_ULTIMATE.start_main_#t~ite43_5|) InVars {ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|} OutVars{~a~0=v_~a~0_13, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|} AuxVars[] AssignedVars[~a~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [360] L800-->L800-2: Formula: (and (or (= (mod v_~a$w_buff0_used~0_59 256) 0) (= 0 (mod v_~a$r_buff0_thd0~0_6 256))) (= |v_ULTIMATE.start_main_#t~ite44_3| v_~a$w_buff0_used~0_59)) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_59, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_6} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_59, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_6, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [532] L800-2-->L801: Formula: (= v_~a$w_buff0_used~0_60 |v_ULTIMATE.start_main_#t~ite44_5|) InVars {ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_5|} OutVars{~a$w_buff0_used~0=v_~a$w_buff0_used~0_60, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_4|} AuxVars[] AssignedVars[~a$w_buff0_used~0, ULTIMATE.start_main_#t~ite44] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [476] L801-->L801-2: Formula: (and (or (= (mod v_~a$w_buff0_used~0_62 256) 0) (= (mod v_~a$r_buff0_thd0~0_8 256) 0)) (= |v_ULTIMATE.start_main_#t~ite45_3| v_~a$w_buff1_used~0_36) (or (= (mod v_~a$r_buff1_thd0~0_6 256) 0) (= (mod v_~a$w_buff1_used~0_36 256) 0))) InVars {~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_6, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_62, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_36, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_8} OutVars{~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_6, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_62, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_36, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_8, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite45] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [483] L801-2-->L802: Formula: (= v_~a$w_buff1_used~0_37 |v_ULTIMATE.start_main_#t~ite45_5|) InVars {ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_5|} OutVars{ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_4|, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_37} AuxVars[] AssignedVars[~a$w_buff1_used~0, ULTIMATE.start_main_#t~ite45] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [409] L802-->L802-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite46_3| v_~a$r_buff0_thd0~0_10) (or (= (mod v_~a$r_buff0_thd0~0_10 256) 0) (= 0 (mod v_~a$w_buff0_used~0_64 256)))) InVars {~a$w_buff0_used~0=v_~a$w_buff0_used~0_64, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_10} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_3|, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_64, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_10} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [412] L802-2-->L803: Formula: (= v_~a$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite46_5|) InVars {ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_5|} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_4|, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_11} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ~a$r_buff0_thd0~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [516] L803-->L803-2: Formula: (and (or (= 0 (mod v_~a$w_buff1_used~0_39 256)) (= 0 (mod v_~a$r_buff1_thd0~0_8 256))) (or (= 0 (mod v_~a$r_buff0_thd0~0_13 256)) (= 0 (mod v_~a$w_buff0_used~0_66 256))) (= |v_ULTIMATE.start_main_#t~ite47_3| v_~a$r_buff1_thd0~0_8)) InVars {~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_8, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_66, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_13, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_39} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_3|, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_8, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_66, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_13, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_39} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [519] L803-2-->L808: Formula: (and (= v_~a$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite47_5|) (= v_~main$tmp_guard1~0_2 (ite (= (ite (not (and (= 0 v_~__unbuffered_p1_EBX~0_3) (= v_~__unbuffered_p0_EBX~0_2 0) (= 1 v_~__unbuffered_p1_EAX~0_2) (= v_~__unbuffered_p0_EAX~0_2 1))) 1 0) 0) 0 1))) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_5|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_2, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_2, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_4|, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ~a$r_buff1_thd0~0, ~main$tmp_guard1~0] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [366] L808-->L808-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_3 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [370] L808-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [407] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [405] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 [402] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P1_thidvar0=1, Thread0_P1_~arg.base=0, Thread0_P1_~arg.offset=0, Thread1_P0___VERIFIER_assert_~expression=1, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P1_#in~arg.base|=0, |Thread0_P1_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread1_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [?] -1 ~a$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [?] -1 ~a$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [?] -1 ~a$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [?] -1 ~a$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [?] -1 ~a$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [?] -1 ~a$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [?] -1 ~a$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [?] -1 ~a$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [?] -1 ~a$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [?] -1 ~a$read_delayed_var~0.base, ~a$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a~0=0] [?] -1 ~a$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [?] -1 ~a$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [?] -1 ~a$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [?] -1 ~a$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t839~0.base, main_~#t839~0.offset, main_~#t840~0.base, main_~#t840~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t839~0.base, main_~#t839~0.offset := #Ultimate.alloc(4); srcloc: L790 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t839~0.base, main_~#t839~0.offset, 4); srcloc: L790-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~a$w_buff1~0 := ~a$w_buff0~0;~a$w_buff0~0 := 1;~a$w_buff1_used~0 := ~a$w_buff0_used~0;~a$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t840~0.base, main_~#t840~0.offset := #Ultimate.alloc(4); srcloc: L792 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t840~0.base, main_~#t840~0.offset, 4); srcloc: L792-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0;~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0;~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0;~a$r_buff0_thd1~0 := 1;~x~0 := 1;~__unbuffered_p0_EAX~0 := ~x~0;~__unbuffered_p0_EBX~0 := ~y~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [?] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256;#t~ite4 := ~a$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 1;~z~0 := 1;~__unbuffered_p1_EAX~0 := ~z~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~a$flush_delayed~0 := ~weak$$choice2~0;~a$mem_tmp~0 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256);#t~ite13 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a~0 := #t~ite4;havoc #t~ite4;havoc #t~ite3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256));#t~ite6 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~a$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256);#t~ite7 := ~a$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256));#t~ite8 := ~a$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff0~0 := #t~ite16;havoc #t~ite15;havoc #t~ite16;havoc #t~ite14; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~a$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff1~0 := #t~ite19;havoc #t~ite19;havoc #t~ite17;havoc #t~ite18; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~a$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff0_used~0 := #t~ite22;havoc #t~ite21;havoc #t~ite20;havoc #t~ite22; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff1_used~0 := #t~ite25;havoc #t~ite23;havoc #t~ite25;havoc #t~ite24; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~a$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff0_thd2~0 := #t~ite28;havoc #t~ite26;havoc #t~ite27;havoc #t~ite28; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~a$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff1_thd2~0 := #t~ite31;havoc #t~ite31;havoc #t~ite29;havoc #t~ite30;~__unbuffered_p1_EBX~0 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~a$flush_delayed~0 % 256;#t~ite32 := ~a$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a~0 := #t~ite32;havoc #t~ite32;~a$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256);#t~ite33 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a~0 := #t~ite34;havoc #t~ite34;havoc #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256);#t~ite35 := ~a$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256));#t~ite36 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256);#t~ite37 := ~a$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256));#t~ite38 := ~a$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256);main_#t~ite42 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256);main_#t~ite44 := ~a$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256));main_#t~ite45 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256);main_#t~ite46 := ~a$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256));main_#t~ite47 := ~a$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [?] -1 ~a$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [?] -1 ~a$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [?] -1 ~a$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [?] -1 ~a$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [?] -1 ~a$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [?] -1 ~a$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [?] -1 ~a$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [?] -1 ~a$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [?] -1 ~a$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [?] -1 ~a$read_delayed_var~0.base, ~a$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a~0=0] [?] -1 ~a$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [?] -1 ~a$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [?] -1 ~a$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [?] -1 ~a$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t839~0.base, main_~#t839~0.offset, main_~#t840~0.base, main_~#t840~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t839~0.base, main_~#t839~0.offset := #Ultimate.alloc(4); srcloc: L790 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t839~0.base, main_~#t839~0.offset, 4); srcloc: L790-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~a$w_buff1~0 := ~a$w_buff0~0;~a$w_buff0~0 := 1;~a$w_buff1_used~0 := ~a$w_buff0_used~0;~a$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t840~0.base, main_~#t840~0.offset := #Ultimate.alloc(4); srcloc: L792 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t840~0.base, main_~#t840~0.offset, 4); srcloc: L792-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0;~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0;~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0;~a$r_buff0_thd1~0 := 1;~x~0 := 1;~__unbuffered_p0_EAX~0 := ~x~0;~__unbuffered_p0_EBX~0 := ~y~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [?] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256;#t~ite4 := ~a$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 1;~z~0 := 1;~__unbuffered_p1_EAX~0 := ~z~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~a$flush_delayed~0 := ~weak$$choice2~0;~a$mem_tmp~0 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256);#t~ite13 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a~0 := #t~ite4;havoc #t~ite4;havoc #t~ite3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256));#t~ite6 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~a$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256);#t~ite7 := ~a$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256));#t~ite8 := ~a$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 0 ~a$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff0~0 := #t~ite16;havoc #t~ite15;havoc #t~ite16;havoc #t~ite14; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~a$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff1~0 := #t~ite19;havoc #t~ite19;havoc #t~ite17;havoc #t~ite18; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~a$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff0_used~0 := #t~ite22;havoc #t~ite21;havoc #t~ite20;havoc #t~ite22; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff1_used~0 := #t~ite25;havoc #t~ite23;havoc #t~ite25;havoc #t~ite24; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~a$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff0_thd2~0 := #t~ite28;havoc #t~ite26;havoc #t~ite27;havoc #t~ite28; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~a$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff1_thd2~0 := #t~ite31;havoc #t~ite31;havoc #t~ite29;havoc #t~ite30;~__unbuffered_p1_EBX~0 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume 0 != ~a$flush_delayed~0 % 256;#t~ite32 := ~a$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a~0 := #t~ite32;havoc #t~ite32;~a$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256);#t~ite33 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a~0 := #t~ite34;havoc #t~ite34;havoc #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256);#t~ite35 := ~a$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256));#t~ite36 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256);#t~ite37 := ~a$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256));#t~ite38 := ~a$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] 1 ~a$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256);main_#t~ite42 := ~a~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256);main_#t~ite44 := ~a$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256));main_#t~ite45 := ~a$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256);main_#t~ite46 := ~a$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256));main_#t~ite47 := ~a$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 ~a$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t839~0.base|=6, |ULTIMATE.start_main_~#t839~0.offset|=0, |ULTIMATE.start_main_~#t840~0.base|=5, |ULTIMATE.start_main_~#t840~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L677] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L681] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [L682] -1 ~a$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [L683] -1 ~a$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [L684] -1 ~a$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [L685] -1 ~a$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [L686] -1 ~a$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [L687] -1 ~a$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [L688] -1 ~a$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [L689] -1 ~a$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [L690] -1 ~a$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [L691] -1 ~a$read_delayed_var~0.base, ~a$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a~0=0] [L692] -1 ~a$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [L693] -1 ~a$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [L694] -1 ~a$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [L695] -1 ~a$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [L696] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L697] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L699] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L701] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L703] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L704] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L705] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t839~0.base, main_~#t839~0.offset, main_~#t840~0.base, main_~#t840~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L790] -1 call main_~#t839~0.base, main_~#t839~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 call write~int(0, main_~#t839~0.base, main_~#t839~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L706-L739] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L709] 0 ~a$w_buff1~0 := ~a$w_buff0~0; [L710] 0 ~a$w_buff0~0 := 1; [L711] 0 ~a$w_buff1_used~0 := ~a$w_buff0_used~0; [L712] 0 ~a$w_buff0_used~0 := 1; [L713] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$w_buff0_used~0 % 256) then 1 else 0); [L713] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L792] -1 call main_~#t840~0.base, main_~#t840~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] -1 call write~int(1, main_~#t840~0.base, main_~#t840~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L714] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0; [L715] 0 ~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0; [L716] 0 ~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0; [L717] 0 ~a$r_buff0_thd1~0 := 1; [L720] 0 ~x~0 := 1; [L723] 0 ~__unbuffered_p0_EAX~0 := ~x~0; [L726] 0 ~__unbuffered_p0_EBX~0 := ~y~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L729] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256; [L729] 0 #t~ite4 := ~a$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L740-L778] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L743] 1 ~y~0 := 1; [L746] 1 ~z~0 := 1; [L749] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L752] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L752] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L753] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L753] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L754] 1 ~a$flush_delayed~0 := ~weak$$choice2~0; [L755] 1 ~a$mem_tmp~0 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 assume (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256); [L756] 1 #t~ite13 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L729] 0 ~a~0 := #t~ite4; [L729] 0 havoc #t~ite4; [L729] 0 havoc #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256; [L730] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 ~a$w_buff0_used~0 := #t~ite5; [L730] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 ~a~0 := #t~ite13; [L756] 1 havoc #t~ite13; [L756] 1 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)); [L731] 0 #t~ite6 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 assume 0 != ~weak$$choice2~0 % 256; [L757] 1 #t~ite16 := ~a$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 ~a$w_buff1_used~0 := #t~ite6; [L731] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256); [L732] 0 #t~ite7 := ~a$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 ~a$r_buff0_thd1~0 := #t~ite7; [L732] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)); [L733] 0 #t~ite8 := ~a$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 ~a$r_buff1_thd1~0 := #t~ite8; [L733] 0 havoc #t~ite8; [L736] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 ~a$w_buff0~0 := #t~ite16; [L757] 1 havoc #t~ite15; [L757] 1 havoc #t~ite16; [L757] 1 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 assume 0 != ~weak$$choice2~0 % 256; [L758] 1 #t~ite19 := ~a$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 ~a$w_buff1~0 := #t~ite19; [L758] 1 havoc #t~ite19; [L758] 1 havoc #t~ite17; [L758] 1 havoc #t~ite18; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 assume 0 != ~weak$$choice2~0 % 256; [L759] 1 #t~ite22 := ~a$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 ~a$w_buff0_used~0 := #t~ite22; [L759] 1 havoc #t~ite21; [L759] 1 havoc #t~ite20; [L759] 1 havoc #t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 assume 0 != ~weak$$choice2~0 % 256; [L760] 1 #t~ite25 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 ~a$w_buff1_used~0 := #t~ite25; [L760] 1 havoc #t~ite23; [L760] 1 havoc #t~ite25; [L760] 1 havoc #t~ite24; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 assume 0 != ~weak$$choice2~0 % 256; [L761] 1 #t~ite28 := ~a$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 ~a$r_buff0_thd2~0 := #t~ite28; [L761] 1 havoc #t~ite26; [L761] 1 havoc #t~ite27; [L761] 1 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 assume 0 != ~weak$$choice2~0 % 256; [L762] 1 #t~ite31 := ~a$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 ~a$r_buff1_thd2~0 := #t~ite31; [L762] 1 havoc #t~ite31; [L762] 1 havoc #t~ite29; [L762] 1 havoc #t~ite30; [L763] 1 ~__unbuffered_p1_EBX~0 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 assume 0 != ~a$flush_delayed~0 % 256; [L764] 1 #t~ite32 := ~a$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 ~a~0 := #t~ite32; [L764] 1 havoc #t~ite32; [L765] 1 ~a$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256); [L768] 1 #t~ite33 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 ~a~0 := #t~ite34; [L768] 1 havoc #t~ite34; [L768] 1 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); [L769] 1 #t~ite35 := ~a$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 ~a$w_buff0_used~0 := #t~ite35; [L769] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)); [L770] 1 #t~ite36 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 ~a$w_buff1_used~0 := #t~ite36; [L770] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); [L771] 1 #t~ite37 := ~a$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 ~a$r_buff0_thd2~0 := #t~ite37; [L771] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)); [L772] 1 #t~ite38 := ~a$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 ~a$r_buff1_thd2~0 := #t~ite38; [L772] 1 havoc #t~ite38; [L775] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L793] -1 havoc main_#t~nondet41; [L795] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L797] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256); [L799] -1 main_#t~ite42 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 ~a~0 := main_#t~ite43; [L799] -1 havoc main_#t~ite42; [L799] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); [L800] -1 main_#t~ite44 := ~a$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 ~a$w_buff0_used~0 := main_#t~ite44; [L800] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)); [L801] -1 main_#t~ite45 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 ~a$w_buff1_used~0 := main_#t~ite45; [L801] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); [L802] -1 main_#t~ite46 := ~a$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 ~a$r_buff0_thd0~0 := main_#t~ite46; [L802] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)); [L803] -1 main_#t~ite47 := ~a$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 ~a$r_buff1_thd0~0 := main_#t~ite47; [L803] -1 havoc main_#t~ite47; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L677] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L681] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [L682] -1 ~a$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [L683] -1 ~a$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [L684] -1 ~a$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [L685] -1 ~a$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [L686] -1 ~a$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [L687] -1 ~a$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [L688] -1 ~a$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [L689] -1 ~a$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [L690] -1 ~a$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [L691] -1 ~a$read_delayed_var~0.base, ~a$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a~0=0] [L692] -1 ~a$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [L693] -1 ~a$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [L694] -1 ~a$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [L695] -1 ~a$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [L696] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L697] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L699] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L701] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L703] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L704] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L705] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t839~0.base, main_~#t839~0.offset, main_~#t840~0.base, main_~#t840~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L790] -1 call main_~#t839~0.base, main_~#t839~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 call write~int(0, main_~#t839~0.base, main_~#t839~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L706-L739] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L709] 0 ~a$w_buff1~0 := ~a$w_buff0~0; [L710] 0 ~a$w_buff0~0 := 1; [L711] 0 ~a$w_buff1_used~0 := ~a$w_buff0_used~0; [L712] 0 ~a$w_buff0_used~0 := 1; [L713] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$w_buff0_used~0 % 256) then 1 else 0); [L713] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L792] -1 call main_~#t840~0.base, main_~#t840~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] -1 call write~int(1, main_~#t840~0.base, main_~#t840~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L714] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0; [L715] 0 ~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0; [L716] 0 ~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0; [L717] 0 ~a$r_buff0_thd1~0 := 1; [L720] 0 ~x~0 := 1; [L723] 0 ~__unbuffered_p0_EAX~0 := ~x~0; [L726] 0 ~__unbuffered_p0_EBX~0 := ~y~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L729] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256; [L729] 0 #t~ite4 := ~a$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L740-L778] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L743] 1 ~y~0 := 1; [L746] 1 ~z~0 := 1; [L749] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L752] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L752] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L753] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L753] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L754] 1 ~a$flush_delayed~0 := ~weak$$choice2~0; [L755] 1 ~a$mem_tmp~0 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 assume (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256); [L756] 1 #t~ite13 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L729] 0 ~a~0 := #t~ite4; [L729] 0 havoc #t~ite4; [L729] 0 havoc #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 assume 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256; [L730] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 ~a$w_buff0_used~0 := #t~ite5; [L730] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 ~a~0 := #t~ite13; [L756] 1 havoc #t~ite13; [L756] 1 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)); [L731] 0 #t~ite6 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 assume 0 != ~weak$$choice2~0 % 256; [L757] 1 #t~ite16 := ~a$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 ~a$w_buff1_used~0 := #t~ite6; [L731] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256); [L732] 0 #t~ite7 := ~a$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 ~a$r_buff0_thd1~0 := #t~ite7; [L732] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)); [L733] 0 #t~ite8 := ~a$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 ~a$r_buff1_thd1~0 := #t~ite8; [L733] 0 havoc #t~ite8; [L736] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 ~a$w_buff0~0 := #t~ite16; [L757] 1 havoc #t~ite15; [L757] 1 havoc #t~ite16; [L757] 1 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 assume 0 != ~weak$$choice2~0 % 256; [L758] 1 #t~ite19 := ~a$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 ~a$w_buff1~0 := #t~ite19; [L758] 1 havoc #t~ite19; [L758] 1 havoc #t~ite17; [L758] 1 havoc #t~ite18; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 assume 0 != ~weak$$choice2~0 % 256; [L759] 1 #t~ite22 := ~a$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 ~a$w_buff0_used~0 := #t~ite22; [L759] 1 havoc #t~ite21; [L759] 1 havoc #t~ite20; [L759] 1 havoc #t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 assume 0 != ~weak$$choice2~0 % 256; [L760] 1 #t~ite25 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 ~a$w_buff1_used~0 := #t~ite25; [L760] 1 havoc #t~ite23; [L760] 1 havoc #t~ite25; [L760] 1 havoc #t~ite24; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 assume 0 != ~weak$$choice2~0 % 256; [L761] 1 #t~ite28 := ~a$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 ~a$r_buff0_thd2~0 := #t~ite28; [L761] 1 havoc #t~ite26; [L761] 1 havoc #t~ite27; [L761] 1 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 assume 0 != ~weak$$choice2~0 % 256; [L762] 1 #t~ite31 := ~a$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 ~a$r_buff1_thd2~0 := #t~ite31; [L762] 1 havoc #t~ite31; [L762] 1 havoc #t~ite29; [L762] 1 havoc #t~ite30; [L763] 1 ~__unbuffered_p1_EBX~0 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 assume 0 != ~a$flush_delayed~0 % 256; [L764] 1 #t~ite32 := ~a$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 ~a~0 := #t~ite32; [L764] 1 havoc #t~ite32; [L765] 1 ~a$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256); [L768] 1 #t~ite33 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 ~a~0 := #t~ite34; [L768] 1 havoc #t~ite34; [L768] 1 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); [L769] 1 #t~ite35 := ~a$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 ~a$w_buff0_used~0 := #t~ite35; [L769] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)); [L770] 1 #t~ite36 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 ~a$w_buff1_used~0 := #t~ite36; [L770] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256); [L771] 1 #t~ite37 := ~a$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 ~a$r_buff0_thd2~0 := #t~ite37; [L771] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)); [L772] 1 #t~ite38 := ~a$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 ~a$r_buff1_thd2~0 := #t~ite38; [L772] 1 havoc #t~ite38; [L775] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L793] -1 havoc main_#t~nondet41; [L795] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L797] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 assume !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256); [L799] -1 main_#t~ite42 := ~a~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 ~a~0 := main_#t~ite43; [L799] -1 havoc main_#t~ite42; [L799] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); [L800] -1 main_#t~ite44 := ~a$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 ~a$w_buff0_used~0 := main_#t~ite44; [L800] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)); [L801] -1 main_#t~ite45 := ~a$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 ~a$w_buff1_used~0 := main_#t~ite45; [L801] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 assume !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256); [L802] -1 main_#t~ite46 := ~a$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 ~a$r_buff0_thd0~0 := main_#t~ite46; [L802] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 assume !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)); [L803] -1 main_#t~ite47 := ~a$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 ~a$r_buff1_thd0~0 := main_#t~ite47; [L803] -1 havoc main_#t~ite47; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0.base=6, main_~#t839~0.offset=0, main_~#t840~0.base=5, main_~#t840~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0.base=0, ~a$read_delayed_var~0.offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L677] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L681] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [L682] -1 ~a$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [L683] -1 ~a$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [L684] -1 ~a$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [L685] -1 ~a$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [L686] -1 ~a$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [L687] -1 ~a$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [L688] -1 ~a$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [L689] -1 ~a$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [L690] -1 ~a$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [L691] -1 ~a$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a~0=0] [L692] -1 ~a$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [L693] -1 ~a$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [L694] -1 ~a$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [L695] -1 ~a$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [L696] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L697] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L699] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L701] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L703] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L704] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L705] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t839~0, main_~#t840~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L790] FCALL -1 call main_~#t839~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FCALL -1 call write~int(0, main_~#t839~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L706-L739] 0 ~arg := #in~arg; [L709] 0 ~a$w_buff1~0 := ~a$w_buff0~0; [L710] 0 ~a$w_buff0~0 := 1; [L711] 0 ~a$w_buff1_used~0 := ~a$w_buff0_used~0; [L712] 0 ~a$w_buff0_used~0 := 1; [L713] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$w_buff0_used~0 % 256) then 1 else 0); [L713] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L792] FCALL -1 call main_~#t840~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FCALL -1 call write~int(1, main_~#t840~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L714] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0; [L715] 0 ~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0; [L716] 0 ~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0; [L717] 0 ~a$r_buff0_thd1~0 := 1; [L720] 0 ~x~0 := 1; [L723] 0 ~__unbuffered_p0_EAX~0 := ~x~0; [L726] 0 ~__unbuffered_p0_EBX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L729] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L729] 0 #t~ite4 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L740-L778] 1 ~arg := #in~arg; [L743] 1 ~y~0 := 1; [L746] 1 ~z~0 := 1; [L749] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L752] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L752] 1 havoc #t~nondet10; [L753] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L753] 1 havoc #t~nondet11; [L754] 1 ~a$flush_delayed~0 := ~weak$$choice2~0; [L755] 1 ~a$mem_tmp~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] COND TRUE 1 (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256) [L756] 1 #t~ite13 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L729] 0 ~a~0 := #t~ite4; [L729] 0 havoc #t~ite4; [L729] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L730] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 ~a$w_buff0_used~0 := #t~ite5; [L730] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 ~a~0 := #t~ite13; [L756] 1 havoc #t~ite13; [L756] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L731] 0 #t~ite6 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L757] 1 #t~ite16 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 ~a$w_buff1_used~0 := #t~ite6; [L731] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] COND FALSE 0 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) [L732] 0 #t~ite7 := ~a$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 ~a$r_buff0_thd1~0 := #t~ite7; [L732] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L733] 0 #t~ite8 := ~a$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 ~a$r_buff1_thd1~0 := #t~ite8; [L733] 0 havoc #t~ite8; [L736] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 ~a$w_buff0~0 := #t~ite16; [L757] 1 havoc #t~ite15; [L757] 1 havoc #t~ite16; [L757] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L758] 1 #t~ite19 := ~a$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 ~a$w_buff1~0 := #t~ite19; [L758] 1 havoc #t~ite19; [L758] 1 havoc #t~ite17; [L758] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L759] 1 #t~ite22 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 ~a$w_buff0_used~0 := #t~ite22; [L759] 1 havoc #t~ite21; [L759] 1 havoc #t~ite20; [L759] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L760] 1 #t~ite25 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 ~a$w_buff1_used~0 := #t~ite25; [L760] 1 havoc #t~ite23; [L760] 1 havoc #t~ite25; [L760] 1 havoc #t~ite24; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L761] 1 #t~ite28 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 ~a$r_buff0_thd2~0 := #t~ite28; [L761] 1 havoc #t~ite26; [L761] 1 havoc #t~ite27; [L761] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L762] 1 #t~ite31 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 ~a$r_buff1_thd2~0 := #t~ite31; [L762] 1 havoc #t~ite31; [L762] 1 havoc #t~ite29; [L762] 1 havoc #t~ite30; [L763] 1 ~__unbuffered_p1_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] COND TRUE 1 0 != ~a$flush_delayed~0 % 256 [L764] 1 #t~ite32 := ~a$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 ~a~0 := #t~ite32; [L764] 1 havoc #t~ite32; [L765] 1 ~a$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256) [L768] 1 #t~ite33 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 ~a~0 := #t~ite34; [L768] 1 havoc #t~ite34; [L768] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L769] 1 #t~ite35 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 ~a$w_buff0_used~0 := #t~ite35; [L769] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L770] 1 #t~ite36 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 ~a$w_buff1_used~0 := #t~ite36; [L770] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L771] 1 #t~ite37 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 ~a$r_buff0_thd2~0 := #t~ite37; [L771] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L772] 1 #t~ite38 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 ~a$r_buff1_thd2~0 := #t~ite38; [L772] 1 havoc #t~ite38; [L775] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L793] -1 havoc main_#t~nondet41; [L795] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L797] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256) [L799] -1 main_#t~ite42 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 ~a~0 := main_#t~ite43; [L799] -1 havoc main_#t~ite42; [L799] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L800] -1 main_#t~ite44 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 ~a$w_buff0_used~0 := main_#t~ite44; [L800] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L801] -1 main_#t~ite45 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 ~a$w_buff1_used~0 := main_#t~ite45; [L801] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L802] -1 main_#t~ite46 := ~a$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 ~a$r_buff0_thd0~0 := main_#t~ite46; [L802] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L803] -1 main_#t~ite47 := ~a$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 ~a$r_buff1_thd0~0 := main_#t~ite47; [L803] -1 havoc main_#t~ite47; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L677] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L681] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [L682] -1 ~a$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [L683] -1 ~a$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [L684] -1 ~a$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [L685] -1 ~a$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [L686] -1 ~a$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [L687] -1 ~a$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [L688] -1 ~a$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [L689] -1 ~a$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [L690] -1 ~a$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [L691] -1 ~a$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a~0=0] [L692] -1 ~a$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [L693] -1 ~a$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [L694] -1 ~a$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [L695] -1 ~a$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [L696] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L697] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L699] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L701] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L703] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L704] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L705] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t839~0, main_~#t840~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L790] FCALL -1 call main_~#t839~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FCALL -1 call write~int(0, main_~#t839~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L706-L739] 0 ~arg := #in~arg; [L709] 0 ~a$w_buff1~0 := ~a$w_buff0~0; [L710] 0 ~a$w_buff0~0 := 1; [L711] 0 ~a$w_buff1_used~0 := ~a$w_buff0_used~0; [L712] 0 ~a$w_buff0_used~0 := 1; [L713] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$w_buff0_used~0 % 256) then 1 else 0); [L713] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L792] FCALL -1 call main_~#t840~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FCALL -1 call write~int(1, main_~#t840~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L714] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0; [L715] 0 ~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0; [L716] 0 ~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0; [L717] 0 ~a$r_buff0_thd1~0 := 1; [L720] 0 ~x~0 := 1; [L723] 0 ~__unbuffered_p0_EAX~0 := ~x~0; [L726] 0 ~__unbuffered_p0_EBX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L729] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L729] 0 #t~ite4 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L740-L778] 1 ~arg := #in~arg; [L743] 1 ~y~0 := 1; [L746] 1 ~z~0 := 1; [L749] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L752] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L752] 1 havoc #t~nondet10; [L753] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L753] 1 havoc #t~nondet11; [L754] 1 ~a$flush_delayed~0 := ~weak$$choice2~0; [L755] 1 ~a$mem_tmp~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] COND TRUE 1 (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256) [L756] 1 #t~ite13 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L729] 0 ~a~0 := #t~ite4; [L729] 0 havoc #t~ite4; [L729] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L730] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 ~a$w_buff0_used~0 := #t~ite5; [L730] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 ~a~0 := #t~ite13; [L756] 1 havoc #t~ite13; [L756] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L731] 0 #t~ite6 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L757] 1 #t~ite16 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 ~a$w_buff1_used~0 := #t~ite6; [L731] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] COND FALSE 0 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) [L732] 0 #t~ite7 := ~a$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 ~a$r_buff0_thd1~0 := #t~ite7; [L732] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L733] 0 #t~ite8 := ~a$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 ~a$r_buff1_thd1~0 := #t~ite8; [L733] 0 havoc #t~ite8; [L736] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 ~a$w_buff0~0 := #t~ite16; [L757] 1 havoc #t~ite15; [L757] 1 havoc #t~ite16; [L757] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L758] 1 #t~ite19 := ~a$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 ~a$w_buff1~0 := #t~ite19; [L758] 1 havoc #t~ite19; [L758] 1 havoc #t~ite17; [L758] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L759] 1 #t~ite22 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 ~a$w_buff0_used~0 := #t~ite22; [L759] 1 havoc #t~ite21; [L759] 1 havoc #t~ite20; [L759] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L760] 1 #t~ite25 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 ~a$w_buff1_used~0 := #t~ite25; [L760] 1 havoc #t~ite23; [L760] 1 havoc #t~ite25; [L760] 1 havoc #t~ite24; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L761] 1 #t~ite28 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 ~a$r_buff0_thd2~0 := #t~ite28; [L761] 1 havoc #t~ite26; [L761] 1 havoc #t~ite27; [L761] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L762] 1 #t~ite31 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 ~a$r_buff1_thd2~0 := #t~ite31; [L762] 1 havoc #t~ite31; [L762] 1 havoc #t~ite29; [L762] 1 havoc #t~ite30; [L763] 1 ~__unbuffered_p1_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] COND TRUE 1 0 != ~a$flush_delayed~0 % 256 [L764] 1 #t~ite32 := ~a$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 ~a~0 := #t~ite32; [L764] 1 havoc #t~ite32; [L765] 1 ~a$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256) [L768] 1 #t~ite33 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 ~a~0 := #t~ite34; [L768] 1 havoc #t~ite34; [L768] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L769] 1 #t~ite35 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 ~a$w_buff0_used~0 := #t~ite35; [L769] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L770] 1 #t~ite36 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 ~a$w_buff1_used~0 := #t~ite36; [L770] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L771] 1 #t~ite37 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 ~a$r_buff0_thd2~0 := #t~ite37; [L771] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L772] 1 #t~ite38 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 ~a$r_buff1_thd2~0 := #t~ite38; [L772] 1 havoc #t~ite38; [L775] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L793] -1 havoc main_#t~nondet41; [L795] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L797] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256) [L799] -1 main_#t~ite42 := ~a~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 ~a~0 := main_#t~ite43; [L799] -1 havoc main_#t~ite42; [L799] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L800] -1 main_#t~ite44 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 ~a$w_buff0_used~0 := main_#t~ite44; [L800] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L801] -1 main_#t~ite45 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 ~a$w_buff1_used~0 := main_#t~ite45; [L801] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L802] -1 main_#t~ite46 := ~a$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 ~a$r_buff0_thd0~0 := main_#t~ite46; [L802] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L803] -1 main_#t~ite47 := ~a$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 ~a$r_buff1_thd0~0 := main_#t~ite47; [L803] -1 havoc main_#t~ite47; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L808] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t839~0!base=6, main_~#t839~0!offset=0, main_~#t840~0!base=5, main_~#t840~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L677] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L681] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [L682] -1 ~a$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [L683] -1 ~a$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [L684] -1 ~a$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [L685] -1 ~a$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [L686] -1 ~a$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [L687] -1 ~a$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [L688] -1 ~a$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [L689] -1 ~a$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [L690] -1 ~a$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [L691] -1 ~a$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a~0=0] [L692] -1 ~a$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [L693] -1 ~a$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [L694] -1 ~a$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [L695] -1 ~a$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [L696] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L697] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L699] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L701] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L703] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L704] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L705] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L790] FCALL -1 call ~#t839~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FCALL -1 call write~int(0, ~#t839~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L706-L739] 0 ~arg := #in~arg; [L709] 0 ~a$w_buff1~0 := ~a$w_buff0~0; [L710] 0 ~a$w_buff0~0 := 1; [L711] 0 ~a$w_buff1_used~0 := ~a$w_buff0_used~0; [L712] 0 ~a$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L792] FCALL -1 call ~#t840~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FCALL -1 call write~int(1, ~#t840~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L714] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0; [L715] 0 ~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0; [L716] 0 ~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0; [L717] 0 ~a$r_buff0_thd1~0 := 1; [L720] 0 ~x~0 := 1; [L723] 0 ~__unbuffered_p0_EAX~0 := ~x~0; [L726] 0 ~__unbuffered_p0_EBX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L729] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L729] 0 #t~ite4 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L740-L778] 1 ~arg := #in~arg; [L743] 1 ~y~0 := 1; [L746] 1 ~z~0 := 1; [L749] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L752] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L752] 1 havoc #t~nondet10; [L753] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L753] 1 havoc #t~nondet11; [L754] 1 ~a$flush_delayed~0 := ~weak$$choice2~0; [L755] 1 ~a$mem_tmp~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] COND TRUE 1 (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256) [L756] 1 #t~ite13 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L729] 0 ~a~0 := #t~ite4; [L729] 0 havoc #t~ite4; [L729] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L730] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 ~a$w_buff0_used~0 := #t~ite5; [L730] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 ~a~0 := #t~ite13; [L756] 1 havoc #t~ite13; [L756] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L731] 0 #t~ite6 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L757] 1 #t~ite16 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 ~a$w_buff1_used~0 := #t~ite6; [L731] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] COND FALSE 0 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) [L732] 0 #t~ite7 := ~a$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 ~a$r_buff0_thd1~0 := #t~ite7; [L732] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L733] 0 #t~ite8 := ~a$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 ~a$r_buff1_thd1~0 := #t~ite8; [L733] 0 havoc #t~ite8; [L736] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 ~a$w_buff0~0 := #t~ite16; [L757] 1 havoc #t~ite15; [L757] 1 havoc #t~ite16; [L757] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L758] 1 #t~ite19 := ~a$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 ~a$w_buff1~0 := #t~ite19; [L758] 1 havoc #t~ite19; [L758] 1 havoc #t~ite17; [L758] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L759] 1 #t~ite22 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 ~a$w_buff0_used~0 := #t~ite22; [L759] 1 havoc #t~ite21; [L759] 1 havoc #t~ite20; [L759] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L760] 1 #t~ite25 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 ~a$w_buff1_used~0 := #t~ite25; [L760] 1 havoc #t~ite23; [L760] 1 havoc #t~ite25; [L760] 1 havoc #t~ite24; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L761] 1 #t~ite28 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 ~a$r_buff0_thd2~0 := #t~ite28; [L761] 1 havoc #t~ite26; [L761] 1 havoc #t~ite27; [L761] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L762] 1 #t~ite31 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 ~a$r_buff1_thd2~0 := #t~ite31; [L762] 1 havoc #t~ite31; [L762] 1 havoc #t~ite29; [L762] 1 havoc #t~ite30; [L763] 1 ~__unbuffered_p1_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] COND TRUE 1 0 != ~a$flush_delayed~0 % 256 [L764] 1 #t~ite32 := ~a$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 ~a~0 := #t~ite32; [L764] 1 havoc #t~ite32; [L765] 1 ~a$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256) [L768] 1 #t~ite33 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 ~a~0 := #t~ite34; [L768] 1 havoc #t~ite34; [L768] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L769] 1 #t~ite35 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 ~a$w_buff0_used~0 := #t~ite35; [L769] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L770] 1 #t~ite36 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 ~a$w_buff1_used~0 := #t~ite36; [L770] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L771] 1 #t~ite37 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 ~a$r_buff0_thd2~0 := #t~ite37; [L771] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L772] 1 #t~ite38 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 ~a$r_buff1_thd2~0 := #t~ite38; [L772] 1 havoc #t~ite38; [L775] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L793] -1 havoc #t~nondet41; [L795] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L797] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256) [L799] -1 #t~ite42 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 ~a~0 := #t~ite43; [L799] -1 havoc #t~ite42; [L799] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L800] -1 #t~ite44 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 ~a$w_buff0_used~0 := #t~ite44; [L800] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L801] -1 #t~ite45 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 ~a$w_buff1_used~0 := #t~ite45; [L801] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L802] -1 #t~ite46 := ~a$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 ~a$r_buff0_thd0~0 := #t~ite46; [L802] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L803] -1 #t~ite47 := ~a$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 ~a$r_buff1_thd0~0 := #t~ite47; [L803] -1 havoc #t~ite47; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p0_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0] [L677] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0] [L679] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L681] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a~0=0] [L682] -1 ~a$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a~0=0] [L683] -1 ~a$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a~0=0] [L684] -1 ~a$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a~0=0] [L685] -1 ~a$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a~0=0] [L686] -1 ~a$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a~0=0] [L687] -1 ~a$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a~0=0] [L688] -1 ~a$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a~0=0] [L689] -1 ~a$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a~0=0] [L690] -1 ~a$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed~0=0, ~a~0=0] [L691] -1 ~a$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a~0=0] [L692] -1 ~a$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0~0=0, ~a~0=0] [L693] -1 ~a$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a~0=0] [L694] -1 ~a$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1~0=0, ~a~0=0] [L695] -1 ~a$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0] [L696] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0] [L697] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L699] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L701] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L703] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L704] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L705] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L790] FCALL -1 call ~#t839~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FCALL -1 call write~int(0, ~#t839~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=0, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L706-L739] 0 ~arg := #in~arg; [L709] 0 ~a$w_buff1~0 := ~a$w_buff0~0; [L710] 0 ~a$w_buff0~0 := 1; [L711] 0 ~a$w_buff1_used~0 := ~a$w_buff0_used~0; [L712] 0 ~a$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L791] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L792] FCALL -1 call ~#t840~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FCALL -1 call write~int(1, ~#t840~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L793] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=0, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L714] 0 ~a$r_buff1_thd0~0 := ~a$r_buff0_thd0~0; [L715] 0 ~a$r_buff1_thd1~0 := ~a$r_buff0_thd1~0; [L716] 0 ~a$r_buff1_thd2~0 := ~a$r_buff0_thd2~0; [L717] 0 ~a$r_buff0_thd1~0 := 1; [L720] 0 ~x~0 := 1; [L723] 0 ~__unbuffered_p0_EAX~0 := ~x~0; [L726] 0 ~__unbuffered_p0_EBX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L729] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L729] 0 #t~ite4 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z~0=0] [L740-L778] 1 ~arg := #in~arg; [L743] 1 ~y~0 := 1; [L746] 1 ~z~0 := 1; [L749] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L752] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L752] 1 havoc #t~nondet10; [L753] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L753] 1 havoc #t~nondet11; [L754] 1 ~a$flush_delayed~0 := ~weak$$choice2~0; [L755] 1 ~a$mem_tmp~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] COND TRUE 1 (0 == ~a$w_buff0_used~0 % 256 || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$w_buff1_used~0 % 256)) || (0 == ~a$r_buff0_thd2~0 % 256 && 0 == ~a$r_buff1_thd2~0 % 256) [L756] 1 #t~ite13 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L729] 0 ~a~0 := #t~ite4; [L729] 0 havoc #t~ite4; [L729] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] COND TRUE 0 0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256 [L730] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=1, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L730] 0 ~a$w_buff0_used~0 := #t~ite5; [L730] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L756] 1 ~a~0 := #t~ite13; [L756] 1 havoc #t~ite13; [L756] 1 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L731] 0 #t~ite6 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L757] 1 #t~ite16 := ~a$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L731] 0 ~a$w_buff1_used~0 := #t~ite6; [L731] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] COND FALSE 0 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) [L732] 0 #t~ite7 := ~a$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L732] 0 ~a$r_buff0_thd1~0 := #t~ite7; [L732] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] COND FALSE 0 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd1~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd1~0 % 256)) [L733] 0 #t~ite8 := ~a$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L733] 0 ~a$r_buff1_thd1~0 := #t~ite8; [L733] 0 havoc #t~ite8; [L736] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L757] 1 ~a$w_buff0~0 := #t~ite16; [L757] 1 havoc #t~ite15; [L757] 1 havoc #t~ite16; [L757] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L758] 1 #t~ite19 := ~a$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L758] 1 ~a$w_buff1~0 := #t~ite19; [L758] 1 havoc #t~ite19; [L758] 1 havoc #t~ite17; [L758] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L759] 1 #t~ite22 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L759] 1 ~a$w_buff0_used~0 := #t~ite22; [L759] 1 havoc #t~ite21; [L759] 1 havoc #t~ite20; [L759] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L760] 1 #t~ite25 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L760] 1 ~a$w_buff1_used~0 := #t~ite25; [L760] 1 havoc #t~ite23; [L760] 1 havoc #t~ite25; [L760] 1 havoc #t~ite24; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L761] 1 #t~ite28 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L761] 1 ~a$r_buff0_thd2~0 := #t~ite28; [L761] 1 havoc #t~ite26; [L761] 1 havoc #t~ite27; [L761] 1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L762] 1 #t~ite31 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L762] 1 ~a$r_buff1_thd2~0 := #t~ite31; [L762] 1 havoc #t~ite31; [L762] 1 havoc #t~ite29; [L762] 1 havoc #t~ite30; [L763] 1 ~__unbuffered_p1_EBX~0 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] COND TRUE 1 0 != ~a$flush_delayed~0 % 256 [L764] 1 #t~ite32 := ~a$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=1, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L764] 1 ~a~0 := #t~ite32; [L764] 1 havoc #t~ite32; [L765] 1 ~a$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] COND FALSE 1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256) [L768] 1 #t~ite33 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L768] 1 ~a~0 := #t~ite34; [L768] 1 havoc #t~ite34; [L768] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L769] 1 #t~ite35 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L769] 1 ~a$w_buff0_used~0 := #t~ite35; [L769] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L770] 1 #t~ite36 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L770] 1 ~a$w_buff1_used~0 := #t~ite36; [L770] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] COND FALSE 1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) [L771] 1 #t~ite37 := ~a$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L771] 1 ~a$r_buff0_thd2~0 := #t~ite37; [L771] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] COND FALSE 1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd2~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd2~0 % 256)) [L772] 1 #t~ite38 := ~a$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L772] 1 ~a$r_buff1_thd2~0 := #t~ite38; [L772] 1 havoc #t~ite38; [L775] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L793] -1 havoc #t~nondet41; [L795] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L797] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] COND FALSE -1 !(0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256) [L799] -1 #t~ite42 := ~a~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L799] -1 ~a~0 := #t~ite43; [L799] -1 havoc #t~ite42; [L799] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L800] -1 #t~ite44 := ~a$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L800] -1 ~a$w_buff0_used~0 := #t~ite44; [L800] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L801] -1 #t~ite45 := ~a$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L801] -1 ~a$w_buff1_used~0 := #t~ite45; [L801] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] COND FALSE -1 !(0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) [L802] -1 #t~ite46 := ~a$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L802] -1 ~a$r_buff0_thd0~0 := #t~ite46; [L802] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] COND FALSE -1 !((0 != ~a$w_buff0_used~0 % 256 && 0 != ~a$r_buff0_thd0~0 % 256) || (0 != ~a$w_buff1_used~0 % 256 && 0 != ~a$r_buff1_thd0~0 % 256)) [L803] -1 #t~ite47 := ~a$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L803] -1 ~a$r_buff1_thd0~0 := #t~ite47; [L803] -1 havoc #t~ite47; [L806] -1 ~main$tmp_guard1~0 := (if 0 == (if !(((1 == ~__unbuffered_p0_EAX~0 && 0 == ~__unbuffered_p0_EBX~0) && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=1, ~__unbuffered_p0_EBX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~a$flush_delayed~0=0, ~a$mem_tmp~0=0, ~a$r_buff0_thd0~0=0, ~a$r_buff0_thd1~0=1, ~a$r_buff0_thd2~0=0, ~a$r_buff1_thd0~0=0, ~a$r_buff1_thd1~0=0, ~a$r_buff1_thd2~0=0, ~a$read_delayed_var~0!base=0, ~a$read_delayed_var~0!offset=0, ~a$read_delayed~0=0, ~a$w_buff0_used~0=0, ~a$w_buff0~0=1, ~a$w_buff1_used~0=0, ~a$w_buff1~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z~0=1] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L675] -1 int __unbuffered_p0_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0] [L677] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0] [L679] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L681] -1 int a = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0] [L682] -1 _Bool a$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0] [L683] -1 int a$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0] [L684] -1 _Bool a$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0] [L685] -1 _Bool a$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0] [L686] -1 _Bool a$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0] [L687] -1 _Bool a$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0] [L688] -1 _Bool a$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0] [L689] -1 _Bool a$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0] [L690] -1 _Bool a$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0] [L691] -1 int *a$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}] [L692] -1 int a$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0] [L693] -1 _Bool a$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0] [L694] -1 int a$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0] [L695] -1 _Bool a$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0] [L696] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0] [L697] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0] [L699] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L701] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L703] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L704] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0] [L705] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L790] -1 pthread_t t839; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L791] FCALL, FORK -1 pthread_create(&t839, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L709] 0 a$w_buff1 = a$w_buff0 [L710] 0 a$w_buff0 = 1 [L711] 0 a$w_buff1_used = a$w_buff0_used [L712] 0 a$w_buff0_used = (_Bool)1 [L792] -1 pthread_t t840; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L793] FCALL, FORK -1 pthread_create(&t840, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L714] 0 a$r_buff1_thd0 = a$r_buff0_thd0 [L715] 0 a$r_buff1_thd1 = a$r_buff0_thd1 [L716] 0 a$r_buff1_thd2 = a$r_buff0_thd2 [L717] 0 a$r_buff0_thd1 = (_Bool)1 [L720] 0 x = 1 [L723] 0 __unbuffered_p0_EAX = x [L726] 0 __unbuffered_p0_EBX = y VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0] [L729] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd1 ? a$w_buff1 : a) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0] [L743] 1 y = 1 [L746] 1 z = 1 [L749] 1 __unbuffered_p1_EAX = z [L752] 1 weak$$choice0 = __VERIFIER_nondet_pointer() [L753] 1 weak$$choice2 = __VERIFIER_nondet_pointer() [L754] 1 a$flush_delayed = weak$$choice2 [L755] 1 a$mem_tmp = a VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L756] EXPR 1 !a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff1) VAL [!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L729] 0 a = a$w_buff0_used && a$r_buff0_thd1 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd1 ? a$w_buff1 : a) [L730] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$w_buff0_used VAL [!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=1, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L730] 0 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$w_buff0_used [L756] 1 a = !a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff1) [L731] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L757] EXPR 1 weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0))=1, x=1, y=1, z=1] [L731] 0 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$w_buff1_used [L732] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$r_buff0_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0))=1, x=1, y=1, z=1] [L732] 0 a$r_buff0_thd1 = a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$r_buff0_thd1 [L733] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$r_buff1_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0))=1, x=1, y=1, z=1] [L733] 0 a$r_buff1_thd1 = a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$r_buff1_thd1 [L736] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0))=1, x=1, y=1, z=1] [L757] 1 a$w_buff0 = weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0)) [L758] EXPR 1 weak$$choice2 ? a$w_buff1 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff1 : a$w_buff1)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff1 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff1 : a$w_buff1))=0, x=1, y=1, z=1] [L758] 1 a$w_buff1 = weak$$choice2 ? a$w_buff1 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff1 : a$w_buff1)) [L759] EXPR 1 weak$$choice2 ? a$w_buff0_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used))=0, x=1, y=1, z=1] [L759] 1 a$w_buff0_used = weak$$choice2 ? a$w_buff0_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used)) [L760] EXPR 1 weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=1] [L760] 1 a$w_buff1_used = weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L761] EXPR 1 weak$$choice2 ? a$r_buff0_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff0_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$r_buff0_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff0_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2))=0, x=1, y=1, z=1] [L761] 1 a$r_buff0_thd2 = weak$$choice2 ? a$r_buff0_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff0_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2)) [L762] EXPR 1 weak$$choice2 ? a$r_buff1_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff1_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$r_buff1_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff1_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=1] [L762] 1 a$r_buff1_thd2 = weak$$choice2 ? a$r_buff1_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff1_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L763] 1 __unbuffered_p1_EBX = a VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L764] EXPR 1 a$flush_delayed ? a$mem_tmp : a VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$flush_delayed ? a$mem_tmp : a=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L764] 1 a = a$flush_delayed ? a$mem_tmp : a [L765] 1 a$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L768] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L768] EXPR 1 a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L768] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a)=0, a$w_buff1=0, a$w_buff1_used=0, a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L768] 1 a = a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a) [L769] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L769] 1 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used [L770] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$w_buff1_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L770] 1 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$w_buff1_used [L771] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L771] 1 a$r_buff0_thd2 = a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2 [L772] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$r_buff1_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$r_buff1_thd2=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L772] 1 a$r_buff1_thd2 = a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$r_buff1_thd2 [L775] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L795] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L799] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L799] EXPR -1 a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L799] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L799] -1 a = a$w_buff0_used && a$r_buff0_thd0 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a) [L800] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L800] -1 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$w_buff0_used [L801] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L801] -1 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$w_buff1_used [L802] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L802] -1 a$r_buff0_thd0 = a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$r_buff0_thd0 [L803] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L803] -1 a$r_buff1_thd0 = a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$r_buff1_thd0 [L806] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 1 && __unbuffered_p0_EBX == 0 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] ----- [2018-11-23 03:16:23,538 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_c418dcd5-d4ba-492c-8f3e-258001a33967/bin-2019/uautomizer/witness.graphml [2018-11-23 03:16:23,538 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 03:16:23,539 INFO L168 Benchmark]: Toolchain (without parser) took 25853.07 ms. Allocated memory was 1.0 GB in the beginning and 2.7 GB in the end (delta: 1.6 GB). Free memory was 956.6 MB in the beginning and 1.2 GB in the end (delta: -259.9 MB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2018-11-23 03:16:23,540 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 03:16:23,540 INFO L168 Benchmark]: CACSL2BoogieTranslator took 437.13 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 137.9 MB). Free memory was 956.6 MB in the beginning and 1.1 GB in the end (delta: -159.0 MB). Peak memory consumption was 35.1 MB. Max. memory is 11.5 GB. [2018-11-23 03:16:23,540 INFO L168 Benchmark]: Boogie Procedure Inliner took 40.79 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-23 03:16:23,541 INFO L168 Benchmark]: Boogie Preprocessor took 20.65 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 03:16:23,541 INFO L168 Benchmark]: RCFGBuilder took 451.17 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 51.5 MB). Peak memory consumption was 51.5 MB. Max. memory is 11.5 GB. [2018-11-23 03:16:23,541 INFO L168 Benchmark]: TraceAbstraction took 19792.53 ms. Allocated memory was 1.2 GB in the beginning and 2.7 GB in the end (delta: 1.5 GB). Free memory was 1.1 GB in the beginning and 1.4 GB in the end (delta: -288.7 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. [2018-11-23 03:16:23,541 INFO L168 Benchmark]: Witness Printer took 5107.26 ms. Allocated memory is still 2.7 GB. Free memory was 1.4 GB in the beginning and 1.2 GB in the end (delta: 133.6 MB). Peak memory consumption was 133.6 MB. Max. memory is 11.5 GB. [2018-11-23 03:16:23,543 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 437.13 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 137.9 MB). Free memory was 956.6 MB in the beginning and 1.1 GB in the end (delta: -159.0 MB). Peak memory consumption was 35.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 40.79 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 20.65 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 451.17 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 51.5 MB). Peak memory consumption was 51.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 19792.53 ms. Allocated memory was 1.2 GB in the beginning and 2.7 GB in the end (delta: 1.5 GB). Free memory was 1.1 GB in the beginning and 1.4 GB in the end (delta: -288.7 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. * Witness Printer took 5107.26 ms. Allocated memory is still 2.7 GB. Free memory was 1.4 GB in the beginning and 1.2 GB in the end (delta: 133.6 MB). Peak memory consumption was 133.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L675] -1 int __unbuffered_p0_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0] [L677] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0] [L679] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L681] -1 int a = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0] [L682] -1 _Bool a$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0] [L683] -1 int a$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0] [L684] -1 _Bool a$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0] [L685] -1 _Bool a$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0] [L686] -1 _Bool a$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0] [L687] -1 _Bool a$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0] [L688] -1 _Bool a$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0] [L689] -1 _Bool a$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0] [L690] -1 _Bool a$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0] [L691] -1 int *a$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}] [L692] -1 int a$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0] [L693] -1 _Bool a$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0] [L694] -1 int a$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0] [L695] -1 _Bool a$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0] [L696] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0] [L697] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0] [L699] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L701] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L703] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L704] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0] [L705] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L790] -1 pthread_t t839; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L791] FCALL, FORK -1 pthread_create(&t839, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L709] 0 a$w_buff1 = a$w_buff0 [L710] 0 a$w_buff0 = 1 [L711] 0 a$w_buff1_used = a$w_buff0_used [L712] 0 a$w_buff0_used = (_Bool)1 [L792] -1 pthread_t t840; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L793] FCALL, FORK -1 pthread_create(&t840, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L714] 0 a$r_buff1_thd0 = a$r_buff0_thd0 [L715] 0 a$r_buff1_thd1 = a$r_buff0_thd1 [L716] 0 a$r_buff1_thd2 = a$r_buff0_thd2 [L717] 0 a$r_buff0_thd1 = (_Bool)1 [L720] 0 x = 1 [L723] 0 __unbuffered_p0_EAX = x [L726] 0 __unbuffered_p0_EBX = y VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0] [L729] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd1 ? a$w_buff1 : a) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0] [L743] 1 y = 1 [L746] 1 z = 1 [L749] 1 __unbuffered_p1_EAX = z [L752] 1 weak$$choice0 = __VERIFIER_nondet_pointer() [L753] 1 weak$$choice2 = __VERIFIER_nondet_pointer() [L754] 1 a$flush_delayed = weak$$choice2 [L755] 1 a$mem_tmp = a VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L756] EXPR 1 !a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff1) VAL [!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L729] 0 a = a$w_buff0_used && a$r_buff0_thd1 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd1 ? a$w_buff1 : a) [L730] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$w_buff0_used VAL [!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=1, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L730] 0 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$w_buff0_used [L756] 1 a = !a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff1) [L731] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L757] EXPR 1 weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0))=1, x=1, y=1, z=1] [L731] 0 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$w_buff1_used [L732] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$r_buff0_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0))=1, x=1, y=1, z=1] [L732] 0 a$r_buff0_thd1 = a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$r_buff0_thd1 [L733] EXPR 0 a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$r_buff1_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0))=1, x=1, y=1, z=1] [L733] 0 a$r_buff1_thd1 = a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$r_buff1_thd1 [L736] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0))=1, x=1, y=1, z=1] [L757] 1 a$w_buff0 = weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : a$w_buff0)) [L758] EXPR 1 weak$$choice2 ? a$w_buff1 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff1 : a$w_buff1)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff1 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff1 : a$w_buff1))=0, x=1, y=1, z=1] [L758] 1 a$w_buff1 = weak$$choice2 ? a$w_buff1 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1 : (a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff1 : a$w_buff1)) [L759] EXPR 1 weak$$choice2 ? a$w_buff0_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff0_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used))=0, x=1, y=1, z=1] [L759] 1 a$w_buff0_used = weak$$choice2 ? a$w_buff0_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff0_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used)) [L760] EXPR 1 weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=1] [L760] 1 a$w_buff1_used = weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L761] EXPR 1 weak$$choice2 ? a$r_buff0_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff0_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$r_buff0_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff0_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2))=0, x=1, y=1, z=1] [L761] 1 a$r_buff0_thd2 = weak$$choice2 ? a$r_buff0_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff0_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2)) [L762] EXPR 1 weak$$choice2 ? a$r_buff1_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff1_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? a$r_buff1_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff1_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=1] [L762] 1 a$r_buff1_thd2 = weak$$choice2 ? a$r_buff1_thd2 : (!a$w_buff0_used || !a$r_buff0_thd2 && !a$w_buff1_used || !a$r_buff0_thd2 && !a$r_buff1_thd2 ? a$r_buff1_thd2 : (a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L763] 1 __unbuffered_p1_EBX = a VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L764] EXPR 1 a$flush_delayed ? a$mem_tmp : a VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=1, a$flush_delayed ? a$mem_tmp : a=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L764] 1 a = a$flush_delayed ? a$mem_tmp : a [L765] 1 a$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L768] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L768] EXPR 1 a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L768] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a)=0, a$w_buff1=0, a$w_buff1_used=0, a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L768] 1 a = a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a) [L769] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L769] 1 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used [L770] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$w_buff1_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L770] 1 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$w_buff1_used [L771] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L771] 1 a$r_buff0_thd2 = a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2 [L772] EXPR 1 a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$r_buff1_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$r_buff1_thd2=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L772] 1 a$r_buff1_thd2 = a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$r_buff1_thd2 [L775] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L795] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L799] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L799] EXPR -1 a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L799] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L799] -1 a = a$w_buff0_used && a$r_buff0_thd0 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a) [L800] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L800] -1 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$w_buff0_used [L801] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L801] -1 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$w_buff1_used [L802] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L802] -1 a$r_buff0_thd0 = a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$r_buff0_thd0 [L803] EXPR -1 a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L803] -1 a$r_buff1_thd0 = a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$r_buff1_thd0 [L806] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 1 && __unbuffered_p0_EBX == 0 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=1, y=1, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 226 locations, 3 error locations. UNSAFE Result, 19.7s OverallTime, 32 OverallIterations, 1 TraceHistogramMax, 8.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 8420 SDtfs, 9269 SDslu, 20037 SDs, 0 SdLazy, 7269 SolverSat, 310 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 307 GetRequests, 73 SyntacticMatches, 29 SemanticMatches, 205 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 235 ImplicationChecksByTransitivity, 2.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=34931occurred in iteration=13, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 4.8s AutomataMinimizationTime, 31 MinimizatonAttempts, 69338 StatesRemovedByMinimization, 30 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 2.0s InterpolantComputationTime, 2532 NumberOfCodeBlocks, 2532 NumberOfCodeBlocksAsserted, 32 NumberOfCheckSat, 2402 ConstructedInterpolants, 0 QuantifiedInterpolants, 584139 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 31 InterpolantComputations, 31 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...