./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix033_tso.opt_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix033_tso.opt_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6b730660e2a081dac222ac1f77cb78bf07f46cb9 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-22 21:49:54,404 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-22 21:49:54,405 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-22 21:49:54,413 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-22 21:49:54,413 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-22 21:49:54,413 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-22 21:49:54,414 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-22 21:49:54,415 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-22 21:49:54,416 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-22 21:49:54,416 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-22 21:49:54,417 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-22 21:49:54,417 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-22 21:49:54,418 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-22 21:49:54,419 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-22 21:49:54,419 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-22 21:49:54,420 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-22 21:49:54,420 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-22 21:49:54,422 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-22 21:49:54,423 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-22 21:49:54,424 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-22 21:49:54,425 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-22 21:49:54,425 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-22 21:49:54,427 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-22 21:49:54,427 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-22 21:49:54,427 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-22 21:49:54,428 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-22 21:49:54,429 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-22 21:49:54,429 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-22 21:49:54,430 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-22 21:49:54,431 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-22 21:49:54,431 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-22 21:49:54,431 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-22 21:49:54,431 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-22 21:49:54,432 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-22 21:49:54,432 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-22 21:49:54,433 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-22 21:49:54,433 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-22 21:49:54,442 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-22 21:49:54,442 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-22 21:49:54,443 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-22 21:49:54,443 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-22 21:49:54,443 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-22 21:49:54,444 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-22 21:49:54,444 INFO L133 SettingsManager]: * Use SBE=true [2018-11-22 21:49:54,444 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-22 21:49:54,444 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-22 21:49:54,444 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-22 21:49:54,444 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-22 21:49:54,444 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-22 21:49:54,445 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-22 21:49:54,445 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-22 21:49:54,445 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-22 21:49:54,445 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-22 21:49:54,445 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-22 21:49:54,445 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-22 21:49:54,445 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-22 21:49:54,445 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-22 21:49:54,445 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-22 21:49:54,445 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-22 21:49:54,445 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-22 21:49:54,446 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-22 21:49:54,446 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-22 21:49:54,446 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-22 21:49:54,446 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-22 21:49:54,446 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-22 21:49:54,446 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-22 21:49:54,446 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-22 21:49:54,446 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6b730660e2a081dac222ac1f77cb78bf07f46cb9 [2018-11-22 21:49:54,472 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-22 21:49:54,480 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-22 21:49:54,482 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-22 21:49:54,483 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-22 21:49:54,484 INFO L276 PluginConnector]: CDTParser initialized [2018-11-22 21:49:54,484 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix033_tso.opt_false-unreach-call.i [2018-11-22 21:49:54,520 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer/data/4232b0014/f2e8eaae3b9b4033acde29192765eaff/FLAG0c97c3c35 [2018-11-22 21:49:54,979 INFO L307 CDTParser]: Found 1 translation units. [2018-11-22 21:49:54,980 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/sv-benchmarks/c/pthread-wmm/mix033_tso.opt_false-unreach-call.i [2018-11-22 21:49:54,990 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer/data/4232b0014/f2e8eaae3b9b4033acde29192765eaff/FLAG0c97c3c35 [2018-11-22 21:49:54,999 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer/data/4232b0014/f2e8eaae3b9b4033acde29192765eaff [2018-11-22 21:49:55,001 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-22 21:49:55,002 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-22 21:49:55,003 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-22 21:49:55,003 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-22 21:49:55,005 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-22 21:49:55,005 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 09:49:55" (1/1) ... [2018-11-22 21:49:55,007 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3e1fb88e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55, skipping insertion in model container [2018-11-22 21:49:55,007 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 09:49:55" (1/1) ... [2018-11-22 21:49:55,014 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-22 21:49:55,047 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-22 21:49:55,283 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 21:49:55,290 INFO L191 MainTranslator]: Completed pre-run [2018-11-22 21:49:55,377 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 21:49:55,418 INFO L195 MainTranslator]: Completed translation [2018-11-22 21:49:55,419 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55 WrapperNode [2018-11-22 21:49:55,419 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-22 21:49:55,419 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-22 21:49:55,420 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-22 21:49:55,420 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-22 21:49:55,427 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55" (1/1) ... [2018-11-22 21:49:55,437 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55" (1/1) ... [2018-11-22 21:49:55,457 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-22 21:49:55,457 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-22 21:49:55,457 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-22 21:49:55,457 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-22 21:49:55,463 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55" (1/1) ... [2018-11-22 21:49:55,464 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55" (1/1) ... [2018-11-22 21:49:55,466 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55" (1/1) ... [2018-11-22 21:49:55,467 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55" (1/1) ... [2018-11-22 21:49:55,473 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55" (1/1) ... [2018-11-22 21:49:55,475 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55" (1/1) ... [2018-11-22 21:49:55,477 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55" (1/1) ... [2018-11-22 21:49:55,479 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-22 21:49:55,480 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-22 21:49:55,480 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-22 21:49:55,480 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-22 21:49:55,481 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-22 21:49:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-22 21:49:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-22 21:49:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2018-11-22 21:49:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-22 21:49:55,519 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2018-11-22 21:49:55,520 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2018-11-22 21:49:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2018-11-22 21:49:55,520 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2018-11-22 21:49:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2018-11-22 21:49:55,520 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2018-11-22 21:49:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2018-11-22 21:49:55,520 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-22 21:49:55,520 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-22 21:49:55,521 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-22 21:49:56,111 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-22 21:49:56,111 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-22 21:49:56,111 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 09:49:56 BoogieIcfgContainer [2018-11-22 21:49:56,111 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-22 21:49:56,112 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-22 21:49:56,112 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-22 21:49:56,115 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-22 21:49:56,115 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 22.11 09:49:55" (1/3) ... [2018-11-22 21:49:56,115 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3ea48122 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.11 09:49:56, skipping insertion in model container [2018-11-22 21:49:56,115 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 09:49:55" (2/3) ... [2018-11-22 21:49:56,116 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3ea48122 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.11 09:49:56, skipping insertion in model container [2018-11-22 21:49:56,116 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 09:49:56" (3/3) ... [2018-11-22 21:49:56,117 INFO L112 eAbstractionObserver]: Analyzing ICFG mix033_tso.opt_false-unreach-call.i [2018-11-22 21:49:56,149 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,149 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,149 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,150 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,150 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet3.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,150 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet3.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,150 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,150 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,150 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet3.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,150 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet3.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet5.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet4.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet4.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet5.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet4.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,152 WARN L317 ript$VariableManager]: TermVariabe Thread2_P1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet5.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,152 WARN L317 ript$VariableManager]: TermVariabe Thread2_P1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet4.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet5.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,155 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,155 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,155 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,155 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,155 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,155 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,156 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,156 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,156 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,156 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,156 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,156 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,156 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,156 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,156 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,157 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,157 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,157 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,157 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,157 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,157 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,157 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,157 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,157 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,158 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,158 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,158 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,158 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,158 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,158 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,158 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,158 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,158 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,159 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,159 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,159 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,159 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,159 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,159 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,159 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,159 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,159 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,160 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,160 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,160 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,160 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,160 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,160 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,160 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,160 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,160 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,161 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,161 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,161 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,161 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,161 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,161 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,161 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,161 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,162 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,162 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,162 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,162 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,162 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,163 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,163 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,163 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,163 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,163 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,163 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,163 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,164 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,164 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,164 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,164 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet27.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,164 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet27.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,165 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,165 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,165 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet27.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,165 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet27.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,166 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,166 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,166 WARN L317 ript$VariableManager]: TermVariabe Thread0_P2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,166 WARN L317 ript$VariableManager]: TermVariabe Thread0_P2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,166 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,166 WARN L317 ript$VariableManager]: TermVariabe Thread0_P2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,167 WARN L317 ript$VariableManager]: TermVariabe Thread0_P2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,167 WARN L317 ript$VariableManager]: TermVariabe Thread0_P2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,167 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,167 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,167 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,168 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,168 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,168 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,168 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,168 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,169 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,169 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,169 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,169 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,169 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,169 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,170 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,170 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,170 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,170 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,170 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,171 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,171 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,171 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,171 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,171 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,172 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~nondet34.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,172 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~nondet34.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,172 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,172 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,172 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~nondet34.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,172 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~nondet34.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 21:49:56,182 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-22 21:49:56,183 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-22 21:49:56,191 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2018-11-22 21:49:56,205 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2018-11-22 21:49:56,227 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-22 21:49:56,227 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-22 21:49:56,227 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-22 21:49:56,227 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-22 21:49:56,228 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-22 21:49:56,228 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-22 21:49:56,228 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-22 21:49:56,228 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-22 21:49:56,228 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-22 21:49:56,239 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 148places, 179 transitions [2018-11-22 21:50:19,020 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 149047 states. [2018-11-22 21:50:19,022 INFO L276 IsEmpty]: Start isEmpty. Operand 149047 states. [2018-11-22 21:50:19,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-22 21:50:19,029 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:50:19,030 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:50:19,031 INFO L423 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:50:19,035 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:50:19,035 INFO L82 PathProgramCache]: Analyzing trace with hash -552567723, now seen corresponding path program 1 times [2018-11-22 21:50:19,036 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:50:19,037 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:50:19,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:50:19,077 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:50:19,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:50:19,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:50:19,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:50:19,238 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:50:19,239 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:50:19,241 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:50:19,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:50:19,250 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:50:19,251 INFO L87 Difference]: Start difference. First operand 149047 states. Second operand 4 states. [2018-11-22 21:50:23,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:50:23,038 INFO L93 Difference]: Finished difference Result 257067 states and 1188606 transitions. [2018-11-22 21:50:23,038 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-22 21:50:23,040 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 48 [2018-11-22 21:50:23,040 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:50:23,755 INFO L225 Difference]: With dead ends: 257067 [2018-11-22 21:50:23,756 INFO L226 Difference]: Without dead ends: 174817 [2018-11-22 21:50:23,757 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:50:24,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174817 states. [2018-11-22 21:50:27,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174817 to 110557. [2018-11-22 21:50:27,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110557 states. [2018-11-22 21:50:27,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110557 states to 110557 states and 511488 transitions. [2018-11-22 21:50:27,528 INFO L78 Accepts]: Start accepts. Automaton has 110557 states and 511488 transitions. Word has length 48 [2018-11-22 21:50:27,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:50:27,529 INFO L480 AbstractCegarLoop]: Abstraction has 110557 states and 511488 transitions. [2018-11-22 21:50:27,529 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:50:27,529 INFO L276 IsEmpty]: Start isEmpty. Operand 110557 states and 511488 transitions. [2018-11-22 21:50:27,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-22 21:50:27,545 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:50:27,545 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:50:27,545 INFO L423 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:50:27,546 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:50:27,546 INFO L82 PathProgramCache]: Analyzing trace with hash -1274372901, now seen corresponding path program 1 times [2018-11-22 21:50:27,546 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:50:27,546 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:50:27,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:50:27,551 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:50:27,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:50:27,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:50:27,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:50:27,617 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:50:27,617 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:50:27,619 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 21:50:27,619 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:50:27,619 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:50:27,619 INFO L87 Difference]: Start difference. First operand 110557 states and 511488 transitions. Second operand 3 states. [2018-11-22 21:50:28,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:50:28,286 INFO L93 Difference]: Finished difference Result 110557 states and 511383 transitions. [2018-11-22 21:50:28,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:50:28,287 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2018-11-22 21:50:28,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:50:28,619 INFO L225 Difference]: With dead ends: 110557 [2018-11-22 21:50:28,619 INFO L226 Difference]: Without dead ends: 110557 [2018-11-22 21:50:28,620 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:50:32,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110557 states. [2018-11-22 21:50:33,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110557 to 110557. [2018-11-22 21:50:33,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110557 states. [2018-11-22 21:50:34,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110557 states to 110557 states and 511383 transitions. [2018-11-22 21:50:34,065 INFO L78 Accepts]: Start accepts. Automaton has 110557 states and 511383 transitions. Word has length 56 [2018-11-22 21:50:34,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:50:34,065 INFO L480 AbstractCegarLoop]: Abstraction has 110557 states and 511383 transitions. [2018-11-22 21:50:34,065 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 21:50:34,065 INFO L276 IsEmpty]: Start isEmpty. Operand 110557 states and 511383 transitions. [2018-11-22 21:50:34,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-22 21:50:34,075 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:50:34,075 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:50:34,075 INFO L423 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:50:34,075 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:50:34,075 INFO L82 PathProgramCache]: Analyzing trace with hash 468437434, now seen corresponding path program 1 times [2018-11-22 21:50:34,075 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:50:34,076 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:50:34,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:50:34,078 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:50:34,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:50:34,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:50:34,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:50:34,136 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:50:34,136 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:50:34,136 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:50:34,136 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:50:34,136 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:50:34,136 INFO L87 Difference]: Start difference. First operand 110557 states and 511383 transitions. Second operand 5 states. [2018-11-22 21:50:35,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:50:35,886 INFO L93 Difference]: Finished difference Result 240607 states and 1068638 transitions. [2018-11-22 21:50:35,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 21:50:35,887 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2018-11-22 21:50:35,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:50:36,542 INFO L225 Difference]: With dead ends: 240607 [2018-11-22 21:50:36,542 INFO L226 Difference]: Without dead ends: 237057 [2018-11-22 21:50:36,542 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-22 21:50:37,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237057 states. [2018-11-22 21:50:40,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237057 to 160437. [2018-11-22 21:50:40,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160437 states. [2018-11-22 21:50:40,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160437 states to 160437 states and 716827 transitions. [2018-11-22 21:50:40,905 INFO L78 Accepts]: Start accepts. Automaton has 160437 states and 716827 transitions. Word has length 56 [2018-11-22 21:50:40,905 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:50:40,905 INFO L480 AbstractCegarLoop]: Abstraction has 160437 states and 716827 transitions. [2018-11-22 21:50:40,905 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:50:40,905 INFO L276 IsEmpty]: Start isEmpty. Operand 160437 states and 716827 transitions. [2018-11-22 21:50:40,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-22 21:50:40,915 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:50:40,915 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:50:40,915 INFO L423 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:50:40,916 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:50:40,916 INFO L82 PathProgramCache]: Analyzing trace with hash 1683293826, now seen corresponding path program 1 times [2018-11-22 21:50:40,916 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:50:40,916 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:50:40,917 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:50:40,918 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:50:40,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:50:40,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:50:40,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:50:40,980 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:50:40,980 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:50:40,981 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:50:40,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:50:40,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:50:40,981 INFO L87 Difference]: Start difference. First operand 160437 states and 716827 transitions. Second operand 5 states. [2018-11-22 21:50:46,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:50:46,895 INFO L93 Difference]: Finished difference Result 317177 states and 1405159 transitions. [2018-11-22 21:50:46,896 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 21:50:46,896 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 57 [2018-11-22 21:50:46,896 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:50:47,664 INFO L225 Difference]: With dead ends: 317177 [2018-11-22 21:50:47,664 INFO L226 Difference]: Without dead ends: 314277 [2018-11-22 21:50:47,665 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-22 21:50:49,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314277 states. [2018-11-22 21:50:51,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314277 to 178277. [2018-11-22 21:50:51,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178277 states. [2018-11-22 21:50:52,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178277 states to 178277 states and 791364 transitions. [2018-11-22 21:50:52,316 INFO L78 Accepts]: Start accepts. Automaton has 178277 states and 791364 transitions. Word has length 57 [2018-11-22 21:50:52,316 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:50:52,316 INFO L480 AbstractCegarLoop]: Abstraction has 178277 states and 791364 transitions. [2018-11-22 21:50:52,316 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:50:52,316 INFO L276 IsEmpty]: Start isEmpty. Operand 178277 states and 791364 transitions. [2018-11-22 21:50:52,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-11-22 21:50:52,329 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:50:52,329 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:50:52,329 INFO L423 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:50:52,329 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:50:52,329 INFO L82 PathProgramCache]: Analyzing trace with hash -674729880, now seen corresponding path program 1 times [2018-11-22 21:50:52,330 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:50:52,330 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:50:52,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:50:52,331 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:50:52,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:50:52,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:50:52,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:50:52,380 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:50:52,380 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:50:52,380 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 21:50:52,380 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:50:52,380 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:50:52,380 INFO L87 Difference]: Start difference. First operand 178277 states and 791364 transitions. Second operand 3 states. [2018-11-22 21:50:54,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:50:54,082 INFO L93 Difference]: Finished difference Result 231657 states and 1011133 transitions. [2018-11-22 21:50:54,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:50:54,083 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2018-11-22 21:50:54,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:50:54,677 INFO L225 Difference]: With dead ends: 231657 [2018-11-22 21:50:54,677 INFO L226 Difference]: Without dead ends: 231657 [2018-11-22 21:50:54,678 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:50:55,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231657 states. [2018-11-22 21:50:58,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231657 to 202942. [2018-11-22 21:50:58,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202942 states. [2018-11-22 21:51:05,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202942 states to 202942 states and 893421 transitions. [2018-11-22 21:51:05,110 INFO L78 Accepts]: Start accepts. Automaton has 202942 states and 893421 transitions. Word has length 59 [2018-11-22 21:51:05,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:51:05,111 INFO L480 AbstractCegarLoop]: Abstraction has 202942 states and 893421 transitions. [2018-11-22 21:51:05,111 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 21:51:05,111 INFO L276 IsEmpty]: Start isEmpty. Operand 202942 states and 893421 transitions. [2018-11-22 21:51:05,142 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-22 21:51:05,142 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:51:05,142 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:51:05,143 INFO L423 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:51:05,143 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:51:05,143 INFO L82 PathProgramCache]: Analyzing trace with hash 978550790, now seen corresponding path program 1 times [2018-11-22 21:51:05,143 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:51:05,143 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:51:05,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:51:05,145 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:51:05,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:51:05,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:51:05,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:51:05,229 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:51:05,229 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:51:05,229 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:51:05,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:51:05,230 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:51:05,230 INFO L87 Difference]: Start difference. First operand 202942 states and 893421 transitions. Second operand 6 states. [2018-11-22 21:51:07,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:51:07,267 INFO L93 Difference]: Finished difference Result 278037 states and 1213527 transitions. [2018-11-22 21:51:07,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 21:51:07,267 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 63 [2018-11-22 21:51:07,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:51:07,993 INFO L225 Difference]: With dead ends: 278037 [2018-11-22 21:51:07,993 INFO L226 Difference]: Without dead ends: 273332 [2018-11-22 21:51:07,993 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-22 21:51:09,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 273332 states. [2018-11-22 21:51:13,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 273332 to 256762. [2018-11-22 21:51:13,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 256762 states. [2018-11-22 21:51:13,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 256762 states to 256762 states and 1124197 transitions. [2018-11-22 21:51:13,920 INFO L78 Accepts]: Start accepts. Automaton has 256762 states and 1124197 transitions. Word has length 63 [2018-11-22 21:51:13,920 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:51:13,920 INFO L480 AbstractCegarLoop]: Abstraction has 256762 states and 1124197 transitions. [2018-11-22 21:51:13,920 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:51:13,920 INFO L276 IsEmpty]: Start isEmpty. Operand 256762 states and 1124197 transitions. [2018-11-22 21:51:13,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-22 21:51:13,962 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:51:13,962 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:51:13,962 INFO L423 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:51:13,962 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:51:13,962 INFO L82 PathProgramCache]: Analyzing trace with hash -818400569, now seen corresponding path program 1 times [2018-11-22 21:51:13,962 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:51:13,963 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:51:13,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:51:13,964 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:51:13,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:51:13,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:51:14,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:51:14,077 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:51:14,077 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-22 21:51:14,077 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-22 21:51:14,077 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-22 21:51:14,077 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:51:14,078 INFO L87 Difference]: Start difference. First operand 256762 states and 1124197 transitions. Second operand 7 states. [2018-11-22 21:51:16,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:51:16,869 INFO L93 Difference]: Finished difference Result 367257 states and 1557913 transitions. [2018-11-22 21:51:16,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-22 21:51:16,870 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 63 [2018-11-22 21:51:16,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:51:17,831 INFO L225 Difference]: With dead ends: 367257 [2018-11-22 21:51:17,831 INFO L226 Difference]: Without dead ends: 367257 [2018-11-22 21:51:17,831 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-11-22 21:51:25,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367257 states. [2018-11-22 21:51:29,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367257 to 302982. [2018-11-22 21:51:29,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 302982 states. [2018-11-22 21:51:30,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302982 states to 302982 states and 1302893 transitions. [2018-11-22 21:51:30,401 INFO L78 Accepts]: Start accepts. Automaton has 302982 states and 1302893 transitions. Word has length 63 [2018-11-22 21:51:30,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:51:30,401 INFO L480 AbstractCegarLoop]: Abstraction has 302982 states and 1302893 transitions. [2018-11-22 21:51:30,401 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-22 21:51:30,402 INFO L276 IsEmpty]: Start isEmpty. Operand 302982 states and 1302893 transitions. [2018-11-22 21:51:30,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-22 21:51:30,442 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:51:30,442 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:51:30,442 INFO L423 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:51:30,442 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:51:30,442 INFO L82 PathProgramCache]: Analyzing trace with hash 69103112, now seen corresponding path program 1 times [2018-11-22 21:51:30,442 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:51:30,442 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:51:30,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:51:30,444 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:51:30,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:51:30,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:51:30,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:51:30,496 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:51:30,496 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:51:30,496 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:51:30,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:51:30,497 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:51:30,497 INFO L87 Difference]: Start difference. First operand 302982 states and 1302893 transitions. Second operand 4 states. [2018-11-22 21:51:32,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:51:32,581 INFO L93 Difference]: Finished difference Result 261613 states and 1104583 transitions. [2018-11-22 21:51:32,581 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 21:51:32,582 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 63 [2018-11-22 21:51:32,582 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:51:33,216 INFO L225 Difference]: With dead ends: 261613 [2018-11-22 21:51:33,216 INFO L226 Difference]: Without dead ends: 254858 [2018-11-22 21:51:33,217 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:51:34,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 254858 states. [2018-11-22 21:51:43,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 254858 to 254858. [2018-11-22 21:51:43,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 254858 states. [2018-11-22 21:51:44,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254858 states to 254858 states and 1081014 transitions. [2018-11-22 21:51:44,731 INFO L78 Accepts]: Start accepts. Automaton has 254858 states and 1081014 transitions. Word has length 63 [2018-11-22 21:51:44,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:51:44,731 INFO L480 AbstractCegarLoop]: Abstraction has 254858 states and 1081014 transitions. [2018-11-22 21:51:44,731 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:51:44,731 INFO L276 IsEmpty]: Start isEmpty. Operand 254858 states and 1081014 transitions. [2018-11-22 21:51:44,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-22 21:51:44,757 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:51:44,757 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:51:44,758 INFO L423 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:51:44,758 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:51:44,758 INFO L82 PathProgramCache]: Analyzing trace with hash 2071932979, now seen corresponding path program 1 times [2018-11-22 21:51:44,758 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:51:44,758 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:51:44,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:51:44,759 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:51:44,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:51:44,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:51:45,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:51:45,351 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:51:45,351 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:51:45,351 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:51:45,351 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:51:45,352 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:51:45,352 INFO L87 Difference]: Start difference. First operand 254858 states and 1081014 transitions. Second operand 6 states. [2018-11-22 21:51:48,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:51:48,393 INFO L93 Difference]: Finished difference Result 407574 states and 1714377 transitions. [2018-11-22 21:51:48,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-22 21:51:48,394 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 63 [2018-11-22 21:51:48,394 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:51:49,414 INFO L225 Difference]: With dead ends: 407574 [2018-11-22 21:51:49,415 INFO L226 Difference]: Without dead ends: 400393 [2018-11-22 21:51:49,415 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2018-11-22 21:51:50,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 400393 states. [2018-11-22 21:51:55,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 400393 to 259070. [2018-11-22 21:51:55,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 259070 states. [2018-11-22 21:51:56,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 259070 states to 259070 states and 1099301 transitions. [2018-11-22 21:51:56,554 INFO L78 Accepts]: Start accepts. Automaton has 259070 states and 1099301 transitions. Word has length 63 [2018-11-22 21:51:56,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:51:56,554 INFO L480 AbstractCegarLoop]: Abstraction has 259070 states and 1099301 transitions. [2018-11-22 21:51:56,554 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:51:56,554 INFO L276 IsEmpty]: Start isEmpty. Operand 259070 states and 1099301 transitions. [2018-11-22 21:51:56,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-22 21:51:56,596 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:51:56,596 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:51:56,597 INFO L423 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:51:56,597 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:51:56,597 INFO L82 PathProgramCache]: Analyzing trace with hash -1391724770, now seen corresponding path program 1 times [2018-11-22 21:51:56,597 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:51:56,597 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:51:56,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:51:56,599 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:51:56,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:51:56,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:51:56,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:51:56,645 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:51:56,645 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:51:56,645 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:51:56,645 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:51:56,645 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:51:56,645 INFO L87 Difference]: Start difference. First operand 259070 states and 1099301 transitions. Second operand 5 states. [2018-11-22 21:51:56,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:51:56,881 INFO L93 Difference]: Finished difference Result 57902 states and 224525 transitions. [2018-11-22 21:51:56,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:51:56,881 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 64 [2018-11-22 21:51:56,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:51:56,988 INFO L225 Difference]: With dead ends: 57902 [2018-11-22 21:51:56,988 INFO L226 Difference]: Without dead ends: 50986 [2018-11-22 21:51:56,988 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:51:57,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50986 states. [2018-11-22 21:51:57,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50986 to 50746. [2018-11-22 21:51:57,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50746 states. [2018-11-22 21:52:01,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50746 states to 50746 states and 196312 transitions. [2018-11-22 21:52:01,758 INFO L78 Accepts]: Start accepts. Automaton has 50746 states and 196312 transitions. Word has length 64 [2018-11-22 21:52:01,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:01,758 INFO L480 AbstractCegarLoop]: Abstraction has 50746 states and 196312 transitions. [2018-11-22 21:52:01,758 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:52:01,758 INFO L276 IsEmpty]: Start isEmpty. Operand 50746 states and 196312 transitions. [2018-11-22 21:52:01,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-11-22 21:52:01,773 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:01,774 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:01,774 INFO L423 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:01,774 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:01,774 INFO L82 PathProgramCache]: Analyzing trace with hash -276513334, now seen corresponding path program 1 times [2018-11-22 21:52:01,774 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:01,774 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:01,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:01,776 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:01,776 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:01,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:01,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:01,840 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:01,840 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:52:01,840 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:52:01,841 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:52:01,841 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:52:01,841 INFO L87 Difference]: Start difference. First operand 50746 states and 196312 transitions. Second operand 4 states. [2018-11-22 21:52:02,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:02,106 INFO L93 Difference]: Finished difference Result 59865 states and 230931 transitions. [2018-11-22 21:52:02,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 21:52:02,106 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 74 [2018-11-22 21:52:02,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:02,221 INFO L225 Difference]: With dead ends: 59865 [2018-11-22 21:52:02,221 INFO L226 Difference]: Without dead ends: 59865 [2018-11-22 21:52:02,222 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:52:02,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59865 states. [2018-11-22 21:52:02,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59865 to 53961. [2018-11-22 21:52:02,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53961 states. [2018-11-22 21:52:03,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53961 states to 53961 states and 208379 transitions. [2018-11-22 21:52:03,012 INFO L78 Accepts]: Start accepts. Automaton has 53961 states and 208379 transitions. Word has length 74 [2018-11-22 21:52:03,013 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:03,013 INFO L480 AbstractCegarLoop]: Abstraction has 53961 states and 208379 transitions. [2018-11-22 21:52:03,013 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:52:03,013 INFO L276 IsEmpty]: Start isEmpty. Operand 53961 states and 208379 transitions. [2018-11-22 21:52:03,030 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-11-22 21:52:03,030 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:03,030 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:03,030 INFO L423 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:03,031 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:03,031 INFO L82 PathProgramCache]: Analyzing trace with hash 1466297001, now seen corresponding path program 1 times [2018-11-22 21:52:03,031 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:03,031 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:03,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:03,032 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:03,033 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:03,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:03,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:03,091 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:03,091 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:52:03,092 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:52:03,092 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:52:03,092 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:52:03,092 INFO L87 Difference]: Start difference. First operand 53961 states and 208379 transitions. Second operand 6 states. [2018-11-22 21:52:04,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:04,028 INFO L93 Difference]: Finished difference Result 98120 states and 377173 transitions. [2018-11-22 21:52:04,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-22 21:52:04,028 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2018-11-22 21:52:04,028 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:04,212 INFO L225 Difference]: With dead ends: 98120 [2018-11-22 21:52:04,212 INFO L226 Difference]: Without dead ends: 97800 [2018-11-22 21:52:04,213 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2018-11-22 21:52:04,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97800 states. [2018-11-22 21:52:05,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97800 to 58186. [2018-11-22 21:52:05,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58186 states. [2018-11-22 21:52:05,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58186 states to 58186 states and 223570 transitions. [2018-11-22 21:52:05,276 INFO L78 Accepts]: Start accepts. Automaton has 58186 states and 223570 transitions. Word has length 74 [2018-11-22 21:52:05,276 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:05,277 INFO L480 AbstractCegarLoop]: Abstraction has 58186 states and 223570 transitions. [2018-11-22 21:52:05,277 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:52:05,277 INFO L276 IsEmpty]: Start isEmpty. Operand 58186 states and 223570 transitions. [2018-11-22 21:52:05,299 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-22 21:52:05,299 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:05,299 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:05,299 INFO L423 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:05,299 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:05,299 INFO L82 PathProgramCache]: Analyzing trace with hash 1987377366, now seen corresponding path program 1 times [2018-11-22 21:52:05,300 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:05,300 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:05,301 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:05,301 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:05,301 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:05,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:05,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:05,355 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:05,356 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 21:52:05,356 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 21:52:05,356 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 21:52:05,356 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:52:05,356 INFO L87 Difference]: Start difference. First operand 58186 states and 223570 transitions. Second operand 4 states. [2018-11-22 21:52:05,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:05,689 INFO L93 Difference]: Finished difference Result 73349 states and 278574 transitions. [2018-11-22 21:52:05,689 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-22 21:52:05,689 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 76 [2018-11-22 21:52:05,690 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:05,826 INFO L225 Difference]: With dead ends: 73349 [2018-11-22 21:52:05,827 INFO L226 Difference]: Without dead ends: 73349 [2018-11-22 21:52:05,827 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 21:52:06,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73349 states. [2018-11-22 21:52:06,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73349 to 66713. [2018-11-22 21:52:06,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66713 states. [2018-11-22 21:52:06,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66713 states to 66713 states and 254002 transitions. [2018-11-22 21:52:06,934 INFO L78 Accepts]: Start accepts. Automaton has 66713 states and 254002 transitions. Word has length 76 [2018-11-22 21:52:06,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:06,934 INFO L480 AbstractCegarLoop]: Abstraction has 66713 states and 254002 transitions. [2018-11-22 21:52:06,934 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 21:52:06,934 INFO L276 IsEmpty]: Start isEmpty. Operand 66713 states and 254002 transitions. [2018-11-22 21:52:06,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-22 21:52:06,966 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:06,966 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:06,966 INFO L423 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:06,966 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:06,967 INFO L82 PathProgramCache]: Analyzing trace with hash -89831977, now seen corresponding path program 1 times [2018-11-22 21:52:06,967 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:06,967 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:06,968 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:06,968 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:06,968 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:06,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:07,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:07,015 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:07,015 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 21:52:07,016 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 21:52:07,016 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 21:52:07,016 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:52:07,016 INFO L87 Difference]: Start difference. First operand 66713 states and 254002 transitions. Second operand 3 states. [2018-11-22 21:52:07,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:07,364 INFO L93 Difference]: Finished difference Result 69475 states and 263647 transitions. [2018-11-22 21:52:07,364 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 21:52:07,364 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2018-11-22 21:52:07,364 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:07,493 INFO L225 Difference]: With dead ends: 69475 [2018-11-22 21:52:07,493 INFO L226 Difference]: Without dead ends: 69475 [2018-11-22 21:52:07,494 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 21:52:07,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69475 states. [2018-11-22 21:52:08,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69475 to 68223. [2018-11-22 21:52:08,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68223 states. [2018-11-22 21:52:08,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68223 states to 68223 states and 259246 transitions. [2018-11-22 21:52:08,606 INFO L78 Accepts]: Start accepts. Automaton has 68223 states and 259246 transitions. Word has length 76 [2018-11-22 21:52:08,607 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:08,607 INFO L480 AbstractCegarLoop]: Abstraction has 68223 states and 259246 transitions. [2018-11-22 21:52:08,607 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 21:52:08,607 INFO L276 IsEmpty]: Start isEmpty. Operand 68223 states and 259246 transitions. [2018-11-22 21:52:08,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-22 21:52:08,645 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:08,645 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:08,645 INFO L423 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:08,645 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:08,645 INFO L82 PathProgramCache]: Analyzing trace with hash 2086484495, now seen corresponding path program 1 times [2018-11-22 21:52:08,645 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:08,645 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:08,647 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:08,647 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:08,647 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:08,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:08,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:08,706 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:08,706 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:52:08,706 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:52:08,706 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:52:08,706 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:52:08,707 INFO L87 Difference]: Start difference. First operand 68223 states and 259246 transitions. Second operand 6 states. [2018-11-22 21:52:09,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:09,299 INFO L93 Difference]: Finished difference Result 82930 states and 311777 transitions. [2018-11-22 21:52:09,299 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 21:52:09,299 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 78 [2018-11-22 21:52:09,299 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:09,451 INFO L225 Difference]: With dead ends: 82930 [2018-11-22 21:52:09,451 INFO L226 Difference]: Without dead ends: 82930 [2018-11-22 21:52:09,451 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:52:09,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82930 states. [2018-11-22 21:52:10,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82930 to 78446. [2018-11-22 21:52:10,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78446 states. [2018-11-22 21:52:10,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78446 states to 78446 states and 296295 transitions. [2018-11-22 21:52:10,745 INFO L78 Accepts]: Start accepts. Automaton has 78446 states and 296295 transitions. Word has length 78 [2018-11-22 21:52:10,746 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:10,746 INFO L480 AbstractCegarLoop]: Abstraction has 78446 states and 296295 transitions. [2018-11-22 21:52:10,746 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:52:10,746 INFO L276 IsEmpty]: Start isEmpty. Operand 78446 states and 296295 transitions. [2018-11-22 21:52:10,792 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-22 21:52:10,793 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:10,793 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:10,793 INFO L423 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:10,793 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:10,793 INFO L82 PathProgramCache]: Analyzing trace with hash 9275152, now seen corresponding path program 1 times [2018-11-22 21:52:10,793 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:10,793 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:10,794 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:10,794 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:10,794 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:10,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:10,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:10,860 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:10,861 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:52:10,861 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:52:10,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:52:10,861 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:52:10,861 INFO L87 Difference]: Start difference. First operand 78446 states and 296295 transitions. Second operand 6 states. [2018-11-22 21:52:11,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:11,334 INFO L93 Difference]: Finished difference Result 91980 states and 338638 transitions. [2018-11-22 21:52:11,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 21:52:11,334 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 78 [2018-11-22 21:52:11,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:11,500 INFO L225 Difference]: With dead ends: 91980 [2018-11-22 21:52:11,500 INFO L226 Difference]: Without dead ends: 91980 [2018-11-22 21:52:11,500 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-11-22 21:52:11,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91980 states. [2018-11-22 21:52:12,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91980 to 80035. [2018-11-22 21:52:12,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80035 states. [2018-11-22 21:52:12,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80035 states to 80035 states and 297460 transitions. [2018-11-22 21:52:12,875 INFO L78 Accepts]: Start accepts. Automaton has 80035 states and 297460 transitions. Word has length 78 [2018-11-22 21:52:12,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:12,875 INFO L480 AbstractCegarLoop]: Abstraction has 80035 states and 297460 transitions. [2018-11-22 21:52:12,876 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:52:12,876 INFO L276 IsEmpty]: Start isEmpty. Operand 80035 states and 297460 transitions. [2018-11-22 21:52:12,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-22 21:52:12,922 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:12,922 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:12,922 INFO L423 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:12,922 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:12,922 INFO L82 PathProgramCache]: Analyzing trace with hash 220626065, now seen corresponding path program 1 times [2018-11-22 21:52:12,922 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:12,922 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:12,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:12,924 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:12,924 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:12,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:12,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:12,980 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:12,980 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:52:12,981 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:52:12,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:52:12,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:52:12,981 INFO L87 Difference]: Start difference. First operand 80035 states and 297460 transitions. Second operand 5 states. [2018-11-22 21:52:13,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:13,453 INFO L93 Difference]: Finished difference Result 101344 states and 374908 transitions. [2018-11-22 21:52:13,453 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 21:52:13,453 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 78 [2018-11-22 21:52:13,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:13,652 INFO L225 Difference]: With dead ends: 101344 [2018-11-22 21:52:13,652 INFO L226 Difference]: Without dead ends: 101344 [2018-11-22 21:52:13,652 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:52:13,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101344 states. [2018-11-22 21:52:14,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101344 to 85990. [2018-11-22 21:52:14,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85990 states. [2018-11-22 21:52:15,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85990 states to 85990 states and 317478 transitions. [2018-11-22 21:52:15,140 INFO L78 Accepts]: Start accepts. Automaton has 85990 states and 317478 transitions. Word has length 78 [2018-11-22 21:52:15,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:15,140 INFO L480 AbstractCegarLoop]: Abstraction has 85990 states and 317478 transitions. [2018-11-22 21:52:15,140 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:52:15,140 INFO L276 IsEmpty]: Start isEmpty. Operand 85990 states and 317478 transitions. [2018-11-22 21:52:15,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-22 21:52:15,190 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:15,190 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:15,190 INFO L423 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:15,190 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:15,190 INFO L82 PathProgramCache]: Analyzing trace with hash -289908112, now seen corresponding path program 1 times [2018-11-22 21:52:15,190 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:15,190 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:15,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:15,191 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:15,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:15,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:15,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:15,261 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:15,262 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:52:15,262 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:52:15,262 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:52:15,262 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:52:15,262 INFO L87 Difference]: Start difference. First operand 85990 states and 317478 transitions. Second operand 5 states. [2018-11-22 21:52:15,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:15,881 INFO L93 Difference]: Finished difference Result 115113 states and 423726 transitions. [2018-11-22 21:52:15,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 21:52:15,881 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 78 [2018-11-22 21:52:15,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:16,103 INFO L225 Difference]: With dead ends: 115113 [2018-11-22 21:52:16,103 INFO L226 Difference]: Without dead ends: 115113 [2018-11-22 21:52:16,104 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-22 21:52:16,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115113 states. [2018-11-22 21:52:17,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115113 to 90923. [2018-11-22 21:52:17,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90923 states. [2018-11-22 21:52:17,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90923 states to 90923 states and 335672 transitions. [2018-11-22 21:52:17,816 INFO L78 Accepts]: Start accepts. Automaton has 90923 states and 335672 transitions. Word has length 78 [2018-11-22 21:52:17,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:17,816 INFO L480 AbstractCegarLoop]: Abstraction has 90923 states and 335672 transitions. [2018-11-22 21:52:17,816 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:52:17,817 INFO L276 IsEmpty]: Start isEmpty. Operand 90923 states and 335672 transitions. [2018-11-22 21:52:17,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-22 21:52:17,866 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:17,866 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:17,866 INFO L423 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:17,867 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:17,867 INFO L82 PathProgramCache]: Analyzing trace with hash -2097362575, now seen corresponding path program 1 times [2018-11-22 21:52:17,867 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:17,867 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:17,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:17,868 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:17,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:17,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:17,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:17,921 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:17,921 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:52:17,921 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:52:17,921 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:52:17,921 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:52:17,921 INFO L87 Difference]: Start difference. First operand 90923 states and 335672 transitions. Second operand 6 states. [2018-11-22 21:52:18,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:18,033 INFO L93 Difference]: Finished difference Result 32107 states and 101608 transitions. [2018-11-22 21:52:18,034 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 21:52:18,034 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 78 [2018-11-22 21:52:18,034 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:18,064 INFO L225 Difference]: With dead ends: 32107 [2018-11-22 21:52:18,064 INFO L226 Difference]: Without dead ends: 25826 [2018-11-22 21:52:18,064 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2018-11-22 21:52:18,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25826 states. [2018-11-22 21:52:18,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25826 to 22406. [2018-11-22 21:52:18,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22406 states. [2018-11-22 21:52:18,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22406 states to 22406 states and 70115 transitions. [2018-11-22 21:52:18,310 INFO L78 Accepts]: Start accepts. Automaton has 22406 states and 70115 transitions. Word has length 78 [2018-11-22 21:52:18,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:18,311 INFO L480 AbstractCegarLoop]: Abstraction has 22406 states and 70115 transitions. [2018-11-22 21:52:18,311 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:52:18,311 INFO L276 IsEmpty]: Start isEmpty. Operand 22406 states and 70115 transitions. [2018-11-22 21:52:18,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-22 21:52:18,331 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:18,331 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:18,332 INFO L423 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:18,332 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:18,332 INFO L82 PathProgramCache]: Analyzing trace with hash 1243988963, now seen corresponding path program 1 times [2018-11-22 21:52:18,332 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:18,332 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:18,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:18,333 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:18,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:18,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:18,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:18,400 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:18,400 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-22 21:52:18,400 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-22 21:52:18,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-22 21:52:18,400 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:52:18,400 INFO L87 Difference]: Start difference. First operand 22406 states and 70115 transitions. Second operand 7 states. [2018-11-22 21:52:18,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:18,762 INFO L93 Difference]: Finished difference Result 28184 states and 87908 transitions. [2018-11-22 21:52:18,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 21:52:18,762 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 93 [2018-11-22 21:52:18,762 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:18,794 INFO L225 Difference]: With dead ends: 28184 [2018-11-22 21:52:18,794 INFO L226 Difference]: Without dead ends: 28184 [2018-11-22 21:52:18,794 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:52:18,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28184 states. [2018-11-22 21:52:19,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28184 to 23156. [2018-11-22 21:52:19,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23156 states. [2018-11-22 21:52:19,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23156 states to 23156 states and 72665 transitions. [2018-11-22 21:52:19,060 INFO L78 Accepts]: Start accepts. Automaton has 23156 states and 72665 transitions. Word has length 93 [2018-11-22 21:52:19,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:19,060 INFO L480 AbstractCegarLoop]: Abstraction has 23156 states and 72665 transitions. [2018-11-22 21:52:19,061 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-22 21:52:19,061 INFO L276 IsEmpty]: Start isEmpty. Operand 23156 states and 72665 transitions. [2018-11-22 21:52:19,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-22 21:52:19,081 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:19,081 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:19,081 INFO L423 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:19,081 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:19,081 INFO L82 PathProgramCache]: Analyzing trace with hash -1996886328, now seen corresponding path program 1 times [2018-11-22 21:52:19,081 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:19,082 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:19,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:19,083 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:19,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:19,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:19,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:19,137 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:19,138 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 21:52:19,138 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 21:52:19,138 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 21:52:19,138 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 21:52:19,138 INFO L87 Difference]: Start difference. First operand 23156 states and 72665 transitions. Second operand 5 states. [2018-11-22 21:52:19,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:19,310 INFO L93 Difference]: Finished difference Result 26790 states and 83199 transitions. [2018-11-22 21:52:19,311 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 21:52:19,311 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 93 [2018-11-22 21:52:19,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:19,341 INFO L225 Difference]: With dead ends: 26790 [2018-11-22 21:52:19,342 INFO L226 Difference]: Without dead ends: 26620 [2018-11-22 21:52:19,342 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-22 21:52:19,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26620 states. [2018-11-22 21:52:19,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26620 to 23936. [2018-11-22 21:52:19,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23936 states. [2018-11-22 21:52:19,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23936 states to 23936 states and 74829 transitions. [2018-11-22 21:52:19,644 INFO L78 Accepts]: Start accepts. Automaton has 23936 states and 74829 transitions. Word has length 93 [2018-11-22 21:52:19,644 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:19,644 INFO L480 AbstractCegarLoop]: Abstraction has 23936 states and 74829 transitions. [2018-11-22 21:52:19,644 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 21:52:19,644 INFO L276 IsEmpty]: Start isEmpty. Operand 23936 states and 74829 transitions. [2018-11-22 21:52:19,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-22 21:52:19,664 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:19,664 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:19,664 INFO L423 AbstractCegarLoop]: === Iteration 22 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:19,664 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:19,664 INFO L82 PathProgramCache]: Analyzing trace with hash 240665687, now seen corresponding path program 2 times [2018-11-22 21:52:19,664 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:19,664 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:19,666 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:19,666 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:19,666 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:19,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:19,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:19,757 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:19,757 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 21:52:19,757 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 21:52:19,757 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 21:52:19,757 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-22 21:52:19,757 INFO L87 Difference]: Start difference. First operand 23936 states and 74829 transitions. Second operand 6 states. [2018-11-22 21:52:19,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:19,849 INFO L93 Difference]: Finished difference Result 23872 states and 74045 transitions. [2018-11-22 21:52:19,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 21:52:19,849 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 93 [2018-11-22 21:52:19,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:19,874 INFO L225 Difference]: With dead ends: 23872 [2018-11-22 21:52:19,874 INFO L226 Difference]: Without dead ends: 23872 [2018-11-22 21:52:19,874 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:52:19,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23872 states. [2018-11-22 21:52:20,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23872 to 16028. [2018-11-22 21:52:20,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16028 states. [2018-11-22 21:52:20,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16028 states to 16028 states and 50193 transitions. [2018-11-22 21:52:20,082 INFO L78 Accepts]: Start accepts. Automaton has 16028 states and 50193 transitions. Word has length 93 [2018-11-22 21:52:20,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:20,082 INFO L480 AbstractCegarLoop]: Abstraction has 16028 states and 50193 transitions. [2018-11-22 21:52:20,082 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 21:52:20,082 INFO L276 IsEmpty]: Start isEmpty. Operand 16028 states and 50193 transitions. [2018-11-22 21:52:20,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-22 21:52:20,096 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:20,096 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:20,096 INFO L423 AbstractCegarLoop]: === Iteration 23 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:20,097 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:20,097 INFO L82 PathProgramCache]: Analyzing trace with hash -1039801887, now seen corresponding path program 1 times [2018-11-22 21:52:20,097 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:20,097 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:20,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:20,098 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:52:20,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:20,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:20,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:20,214 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:20,214 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-22 21:52:20,214 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-22 21:52:20,214 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-22 21:52:20,214 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-22 21:52:20,215 INFO L87 Difference]: Start difference. First operand 16028 states and 50193 transitions. Second operand 8 states. [2018-11-22 21:52:20,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:20,503 INFO L93 Difference]: Finished difference Result 19085 states and 59341 transitions. [2018-11-22 21:52:20,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-22 21:52:20,503 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 95 [2018-11-22 21:52:20,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:20,531 INFO L225 Difference]: With dead ends: 19085 [2018-11-22 21:52:20,531 INFO L226 Difference]: Without dead ends: 19085 [2018-11-22 21:52:20,532 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=74, Invalid=166, Unknown=0, NotChecked=0, Total=240 [2018-11-22 21:52:20,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19085 states. [2018-11-22 21:52:20,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19085 to 18316. [2018-11-22 21:52:20,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18316 states. [2018-11-22 21:52:20,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18316 states to 18316 states and 57194 transitions. [2018-11-22 21:52:20,798 INFO L78 Accepts]: Start accepts. Automaton has 18316 states and 57194 transitions. Word has length 95 [2018-11-22 21:52:20,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:20,798 INFO L480 AbstractCegarLoop]: Abstraction has 18316 states and 57194 transitions. [2018-11-22 21:52:20,798 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-22 21:52:20,798 INFO L276 IsEmpty]: Start isEmpty. Operand 18316 states and 57194 transitions. [2018-11-22 21:52:20,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-22 21:52:20,820 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:20,820 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:20,820 INFO L423 AbstractCegarLoop]: === Iteration 24 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:20,821 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:20,821 INFO L82 PathProgramCache]: Analyzing trace with hash -152298206, now seen corresponding path program 1 times [2018-11-22 21:52:20,821 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:20,821 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:20,822 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:20,822 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:20,822 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:20,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:20,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:20,940 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:20,940 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-22 21:52:20,940 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-22 21:52:20,940 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-22 21:52:20,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-11-22 21:52:20,941 INFO L87 Difference]: Start difference. First operand 18316 states and 57194 transitions. Second operand 10 states. [2018-11-22 21:52:21,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:21,617 INFO L93 Difference]: Finished difference Result 34508 states and 107414 transitions. [2018-11-22 21:52:21,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 21:52:21,617 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 95 [2018-11-22 21:52:21,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:21,636 INFO L225 Difference]: With dead ends: 34508 [2018-11-22 21:52:21,636 INFO L226 Difference]: Without dead ends: 16352 [2018-11-22 21:52:21,636 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=69, Invalid=171, Unknown=0, NotChecked=0, Total=240 [2018-11-22 21:52:21,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16352 states. [2018-11-22 21:52:21,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16352 to 16352. [2018-11-22 21:52:21,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16352 states. [2018-11-22 21:52:21,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16352 states to 16352 states and 50902 transitions. [2018-11-22 21:52:21,799 INFO L78 Accepts]: Start accepts. Automaton has 16352 states and 50902 transitions. Word has length 95 [2018-11-22 21:52:21,799 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:21,799 INFO L480 AbstractCegarLoop]: Abstraction has 16352 states and 50902 transitions. [2018-11-22 21:52:21,799 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-22 21:52:21,800 INFO L276 IsEmpty]: Start isEmpty. Operand 16352 states and 50902 transitions. [2018-11-22 21:52:21,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-22 21:52:21,814 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:21,814 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:21,814 INFO L423 AbstractCegarLoop]: === Iteration 25 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:21,815 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:21,815 INFO L82 PathProgramCache]: Analyzing trace with hash 1733203426, now seen corresponding path program 2 times [2018-11-22 21:52:21,815 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:21,815 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:21,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:21,816 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 21:52:21,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:21,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:21,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:21,888 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:21,888 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-22 21:52:21,888 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-22 21:52:21,888 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-22 21:52:21,888 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-22 21:52:21,888 INFO L87 Difference]: Start difference. First operand 16352 states and 50902 transitions. Second operand 7 states. [2018-11-22 21:52:22,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:22,384 INFO L93 Difference]: Finished difference Result 28237 states and 87870 transitions. [2018-11-22 21:52:22,385 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 21:52:22,385 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 95 [2018-11-22 21:52:22,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:22,402 INFO L225 Difference]: With dead ends: 28237 [2018-11-22 21:52:22,402 INFO L226 Difference]: Without dead ends: 11338 [2018-11-22 21:52:22,402 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2018-11-22 21:52:22,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11338 states. [2018-11-22 21:52:22,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11338 to 11338. [2018-11-22 21:52:22,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11338 states. [2018-11-22 21:52:22,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11338 states to 11338 states and 35212 transitions. [2018-11-22 21:52:22,557 INFO L78 Accepts]: Start accepts. Automaton has 11338 states and 35212 transitions. Word has length 95 [2018-11-22 21:52:22,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:22,558 INFO L480 AbstractCegarLoop]: Abstraction has 11338 states and 35212 transitions. [2018-11-22 21:52:22,558 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-22 21:52:22,558 INFO L276 IsEmpty]: Start isEmpty. Operand 11338 states and 35212 transitions. [2018-11-22 21:52:22,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-22 21:52:22,573 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:22,573 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:22,573 INFO L423 AbstractCegarLoop]: === Iteration 26 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:22,574 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:22,575 INFO L82 PathProgramCache]: Analyzing trace with hash 706283744, now seen corresponding path program 3 times [2018-11-22 21:52:22,575 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:22,575 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:22,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:22,576 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:52:22,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:22,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 21:52:22,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 21:52:22,703 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 21:52:22,703 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-11-22 21:52:22,703 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-22 21:52:22,703 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-22 21:52:22,703 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-11-22 21:52:22,704 INFO L87 Difference]: Start difference. First operand 11338 states and 35212 transitions. Second operand 11 states. [2018-11-22 21:52:23,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 21:52:23,438 INFO L93 Difference]: Finished difference Result 19630 states and 60855 transitions. [2018-11-22 21:52:23,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-22 21:52:23,439 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 95 [2018-11-22 21:52:23,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 21:52:23,457 INFO L225 Difference]: With dead ends: 19630 [2018-11-22 21:52:23,457 INFO L226 Difference]: Without dead ends: 12828 [2018-11-22 21:52:23,458 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=70, Invalid=310, Unknown=0, NotChecked=0, Total=380 [2018-11-22 21:52:23,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12828 states. [2018-11-22 21:52:23,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12828 to 11468. [2018-11-22 21:52:23,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11468 states. [2018-11-22 21:52:23,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11468 states to 11468 states and 35405 transitions. [2018-11-22 21:52:23,600 INFO L78 Accepts]: Start accepts. Automaton has 11468 states and 35405 transitions. Word has length 95 [2018-11-22 21:52:23,600 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 21:52:23,600 INFO L480 AbstractCegarLoop]: Abstraction has 11468 states and 35405 transitions. [2018-11-22 21:52:23,600 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-22 21:52:23,600 INFO L276 IsEmpty]: Start isEmpty. Operand 11468 states and 35405 transitions. [2018-11-22 21:52:23,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-22 21:52:23,609 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 21:52:23,609 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 21:52:23,609 INFO L423 AbstractCegarLoop]: === Iteration 27 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 21:52:23,610 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 21:52:23,610 INFO L82 PathProgramCache]: Analyzing trace with hash -1113263938, now seen corresponding path program 4 times [2018-11-22 21:52:23,610 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 21:52:23,610 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 21:52:23,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:23,611 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 21:52:23,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 21:52:23,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:52:23,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 21:52:23,664 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [457] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [337] L-1-->L672: Formula: (= |v_#valid_7| (store |v_#valid_8| 0 0)) InVars {#valid=|v_#valid_8|} OutVars{#valid=|v_#valid_7|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [428] L672-->L674: Formula: (= v_~__unbuffered_cnt~0_8 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_8} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [476] L674-->L676: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [325] L676-->L678: Formula: (= v_~__unbuffered_p1_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 [394] L678-->L680: Formula: (= v_~__unbuffered_p2_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p2_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 [433] L680-->L682: Formula: (= v_~__unbuffered_p2_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p2_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 [491] L682-->L684: Formula: (= v_~a~0_2 0) InVars {} OutVars{~a~0=v_~a~0_2} AuxVars[] AssignedVars[~a~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 [361] L684-->L685: Formula: (= v_~b~0_3 0) InVars {} OutVars{~b~0=v_~b~0_3} AuxVars[] AssignedVars[~b~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [?] -1 [474] L685-->L686: Formula: (= v_~main$tmp_guard0~0_3 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [?] -1 [398] L686-->L688: Formula: (= v_~main$tmp_guard1~0_3 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [464] L688-->L690: Formula: (= v_~x~0_4 0) InVars {} OutVars{~x~0=v_~x~0_4} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [498] L690-->L692: Formula: (= v_~y~0_2 0) InVars {} OutVars{~y~0=v_~y~0_2} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 [364] L692-->L693: Formula: (= v_~z~0_11 0) InVars {} OutVars{~z~0=v_~z~0_11} AuxVars[] AssignedVars[~z~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [489] L693-->L694: Formula: (= v_~z$flush_delayed~0_5 0) InVars {} OutVars{~z$flush_delayed~0=v_~z$flush_delayed~0_5} AuxVars[] AssignedVars[~z$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 [426] L694-->L695: Formula: (= v_~z$mem_tmp~0_3 0) InVars {} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_3} AuxVars[] AssignedVars[~z$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 [360] L695-->L696: Formula: (= v_~z$r_buff0_thd0~0_13 0) InVars {} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_13} AuxVars[] AssignedVars[~z$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 [473] L696-->L697: Formula: (= v_~z$r_buff0_thd1~0_2 0) InVars {} OutVars{~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_2} AuxVars[] AssignedVars[~z$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 [397] L697-->L698: Formula: (= v_~z$r_buff0_thd2~0_32 0) InVars {} OutVars{~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32} AuxVars[] AssignedVars[~z$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 [351] L698-->L699: Formula: (= v_~z$r_buff0_thd3~0_14 0) InVars {} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_14} AuxVars[] AssignedVars[~z$r_buff0_thd3~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 [463] L699-->L700: Formula: (= v_~z$r_buff1_thd0~0_9 0) InVars {} OutVars{~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_9} AuxVars[] AssignedVars[~z$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 [393] L700-->L701: Formula: (= v_~z$r_buff1_thd1~0_2 0) InVars {} OutVars{~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_2} AuxVars[] AssignedVars[~z$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 [496] L701-->L702: Formula: (= v_~z$r_buff1_thd2~0_18 0) InVars {} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_18} AuxVars[] AssignedVars[~z$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 [432] L702-->L703: Formula: (= v_~z$r_buff1_thd3~0_9 0) InVars {} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_9} AuxVars[] AssignedVars[~z$r_buff1_thd3~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 [384] L703-->L704: Formula: (= v_~z$read_delayed~0_1 0) InVars {} OutVars{~z$read_delayed~0=v_~z$read_delayed~0_1} AuxVars[] AssignedVars[~z$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [488] L704-->L705: Formula: (and (= v_~z$read_delayed_var~0.offset_1 0) (= v_~z$read_delayed_var~0.base_1 0)) InVars {} OutVars{~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_1, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [425] L705-->L706: Formula: (= v_~z$w_buff0~0_11 0) InVars {} OutVars{~z$w_buff0~0=v_~z$w_buff0~0_11} AuxVars[] AssignedVars[~z$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [359] L706-->L707: Formula: (= v_~z$w_buff0_used~0_55 0) InVars {} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_55} AuxVars[] AssignedVars[~z$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [470] L707-->L708: Formula: (= v_~z$w_buff1~0_10 0) InVars {} OutVars{~z$w_buff1~0=v_~z$w_buff1~0_10} AuxVars[] AssignedVars[~z$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [396] L708-->L709: Formula: (= v_~z$w_buff1_used~0_32 0) InVars {} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_32} AuxVars[] AssignedVars[~z$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [348] L709-->L710: Formula: (= v_~weak$$choice0~0_2 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [462] L710-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [490] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [487] L-1-2-->L806: Formula: true InVars {} OutVars{ULTIMATE.start_main_~#t896~0.offset=|v_ULTIMATE.start_main_~#t896~0.offset_3|, ULTIMATE.start_main_~#t898~0.offset=|v_ULTIMATE.start_main_~#t898~0.offset_4|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_5|, ULTIMATE.start_main_#t~nondet36=|v_ULTIMATE.start_main_#t~nondet36_1|, ULTIMATE.start_main_#t~nondet35=|v_ULTIMATE.start_main_#t~nondet35_1|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_5|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|, ULTIMATE.start_main_~#t898~0.base=|v_ULTIMATE.start_main_~#t898~0.base_4|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_5|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_5|, ULTIMATE.start_main_~#t897~0.offset=|v_ULTIMATE.start_main_~#t897~0.offset_3|, ULTIMATE.start_main_#t~nondet37=|v_ULTIMATE.start_main_#t~nondet37_2|, ULTIMATE.start_main_~#t897~0.base=|v_ULTIMATE.start_main_~#t897~0.base_3|, ULTIMATE.start_main_~#t896~0.base=|v_ULTIMATE.start_main_~#t896~0.base_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t896~0.offset, ULTIMATE.start_main_~#t898~0.offset, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet36, ULTIMATE.start_main_#t~nondet35, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_~#t898~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_~#t897~0.offset, ULTIMATE.start_main_#t~nondet37, ULTIMATE.start_main_~#t897~0.base, ULTIMATE.start_main_~#t896~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [480] L806-->L806-1: Formula: (and (= |v_#length_1| (store |v_#length_2| |v_ULTIMATE.start_main_~#t896~0.base_4| 4)) (= |v_ULTIMATE.start_main_~#t896~0.offset_4| 0) (= |v_#valid_9| (store |v_#valid_10| |v_ULTIMATE.start_main_~#t896~0.base_4| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t896~0.base_4|)) (= 0 (select |v_#valid_10| |v_ULTIMATE.start_main_~#t896~0.base_4|))) InVars {#length=|v_#length_2|, #valid=|v_#valid_10|} OutVars{ULTIMATE.start_main_~#t896~0.offset=|v_ULTIMATE.start_main_~#t896~0.offset_4|, #length=|v_#length_1|, ULTIMATE.start_main_~#t896~0.base=|v_ULTIMATE.start_main_~#t896~0.base_4|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t896~0.offset, #valid, #length, ULTIMATE.start_main_~#t896~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [483] L806-1-->L807: Formula: (= |v_#memory_int_3| (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t896~0.base_5| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t896~0.base_5|) |v_ULTIMATE.start_main_~#t896~0.offset_5| 0))) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t896~0.offset=|v_ULTIMATE.start_main_~#t896~0.offset_5|, ULTIMATE.start_main_~#t896~0.base=|v_ULTIMATE.start_main_~#t896~0.base_5|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t896~0.offset=|v_ULTIMATE.start_main_~#t896~0.offset_5|, ULTIMATE.start_main_~#t896~0.base=|v_ULTIMATE.start_main_~#t896~0.base_5|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [603] L807-->P0ENTRY: Formula: (and (= 0 |v_Thread1_P0_#in~arg.base_3|) (= 0 v_Thread1_P0_thidvar0_2) (= 0 |v_Thread1_P0_#in~arg.offset_3|)) InVars {} OutVars{Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_3|, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_3|, Thread1_P0_thidvar0=v_Thread1_P0_thidvar0_2} AuxVars[] AssignedVars[Thread1_P0_#in~arg.base, Thread1_P0_#in~arg.offset, Thread1_P0_thidvar0] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [416] L807-1-->L808: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet35=|v_ULTIMATE.start_main_#t~nondet35_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet35] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [342] L808-->L808-1: Formula: (and (= |v_ULTIMATE.start_main_~#t897~0.offset_4| 0) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t897~0.base_4| 4)) (= 0 (select |v_#valid_12| |v_ULTIMATE.start_main_~#t897~0.base_4|)) (not (= 0 |v_ULTIMATE.start_main_~#t897~0.base_4|)) (= |v_#valid_11| (store |v_#valid_12| |v_ULTIMATE.start_main_~#t897~0.base_4| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_12|} OutVars{ULTIMATE.start_main_~#t897~0.base=|v_ULTIMATE.start_main_~#t897~0.base_4|, #length=|v_#length_3|, ULTIMATE.start_main_~#t897~0.offset=|v_ULTIMATE.start_main_~#t897~0.offset_4|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t897~0.offset, #valid, ULTIMATE.start_main_~#t897~0.base, #length] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [343] L808-1-->L809: Formula: (= |v_#memory_int_5| (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#t897~0.base_5| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#t897~0.base_5|) |v_ULTIMATE.start_main_~#t897~0.offset_5| 1))) InVars {#memory_int=|v_#memory_int_6|, ULTIMATE.start_main_~#t897~0.base=|v_ULTIMATE.start_main_~#t897~0.base_5|, ULTIMATE.start_main_~#t897~0.offset=|v_ULTIMATE.start_main_~#t897~0.offset_5|} OutVars{#memory_int=|v_#memory_int_5|, ULTIMATE.start_main_~#t897~0.base=|v_ULTIMATE.start_main_~#t897~0.base_5|, ULTIMATE.start_main_~#t897~0.offset=|v_ULTIMATE.start_main_~#t897~0.offset_5|} AuxVars[] AssignedVars[#memory_int] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [604] L809-->P1ENTRY: Formula: (and (= |v_Thread2_P1_#in~arg.base_3| 0) (= v_Thread2_P1_thidvar0_2 1) (= 0 |v_Thread2_P1_#in~arg.offset_3|)) InVars {} OutVars{Thread2_P1_#in~arg.base=|v_Thread2_P1_#in~arg.base_3|, Thread2_P1_thidvar0=v_Thread2_P1_thidvar0_2, Thread2_P1_#in~arg.offset=|v_Thread2_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread2_P1_#in~arg.base, Thread2_P1_thidvar0, Thread2_P1_#in~arg.offset] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [458] L809-1-->L810: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet36=|v_ULTIMATE.start_main_#t~nondet36_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet36] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [408] L810-->L810-1: Formula: (and (= (store |v_#valid_14| |v_ULTIMATE.start_main_~#t898~0.base_5| 1) |v_#valid_13|) (not (= 0 |v_ULTIMATE.start_main_~#t898~0.base_5|)) (= |v_ULTIMATE.start_main_~#t898~0.offset_5| 0) (= (select |v_#valid_14| |v_ULTIMATE.start_main_~#t898~0.base_5|) 0) (= (store |v_#length_6| |v_ULTIMATE.start_main_~#t898~0.base_5| 4) |v_#length_5|)) InVars {#length=|v_#length_6|, #valid=|v_#valid_14|} OutVars{ULTIMATE.start_main_~#t898~0.base=|v_ULTIMATE.start_main_~#t898~0.base_5|, #length=|v_#length_5|, ULTIMATE.start_main_~#t898~0.offset=|v_ULTIMATE.start_main_~#t898~0.offset_5|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t898~0.base, ULTIMATE.start_main_~#t898~0.offset, #valid, #length] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [385] L810-1-->L811: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t898~0.base_1| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t898~0.base_1|) |v_ULTIMATE.start_main_~#t898~0.offset_1| 2))) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t898~0.base=|v_ULTIMATE.start_main_~#t898~0.base_1|, ULTIMATE.start_main_~#t898~0.offset=|v_ULTIMATE.start_main_~#t898~0.offset_1|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t898~0.base=|v_ULTIMATE.start_main_~#t898~0.base_1|, ULTIMATE.start_main_~#t898~0.offset=|v_ULTIMATE.start_main_~#t898~0.offset_1|} AuxVars[] AssignedVars[#memory_int] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [602] L811-->P2ENTRY: Formula: (and (= |v_Thread0_P2_#in~arg.offset_3| 0) (= 0 |v_Thread0_P2_#in~arg.base_3|) (= 2 v_Thread0_P2_thidvar0_2)) InVars {} OutVars{Thread0_P2_#in~arg.base=|v_Thread0_P2_#in~arg.base_3|, Thread0_P2_thidvar0=v_Thread0_P2_thidvar0_2, Thread0_P2_#in~arg.offset=|v_Thread0_P2_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P2_#in~arg.base, Thread0_P2_thidvar0, Thread0_P2_#in~arg.offset] VAL [Thread0_P2_thidvar0=2, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [575] P2ENTRY-->L4: Formula: (and (= v_Thread0_P2_~arg.offset_1 |v_Thread0_P2_#in~arg.offset_1|) (= |v_Thread0_P2___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= (mod v_~z$w_buff1_used~0_21 256) 0)) (not (= (mod v_~z$w_buff0_used~0_36 256) 0)))) 1 0)) (= v_Thread0_P2___VERIFIER_assert_~expression_1 |v_Thread0_P2___VERIFIER_assert_#in~expression_1|) (= v_~z$w_buff0_used~0_36 1) (= v_Thread0_P2_~arg.base_1 |v_Thread0_P2_#in~arg.base_1|) (= v_~z$w_buff0~0_7 1) (= v_~z$w_buff1_used~0_21 v_~z$w_buff0_used~0_37) (= v_~z$w_buff1~0_7 v_~z$w_buff0~0_8)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_37, ~z$w_buff0~0=v_~z$w_buff0~0_8, Thread0_P2_#in~arg.offset=|v_Thread0_P2_#in~arg.offset_1|, Thread0_P2_#in~arg.base=|v_Thread0_P2_#in~arg.base_1|} OutVars{Thread0_P2_~arg.offset=v_Thread0_P2_~arg.offset_1, Thread0_P2_~arg.base=v_Thread0_P2_~arg.base_1, Thread0_P2___VERIFIER_assert_~expression=v_Thread0_P2___VERIFIER_assert_~expression_1, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_36, ~z$w_buff0~0=v_~z$w_buff0~0_7, Thread0_P2___VERIFIER_assert_#in~expression=|v_Thread0_P2___VERIFIER_assert_#in~expression_1|, Thread0_P2_#in~arg.base=|v_Thread0_P2_#in~arg.base_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_21, ~z$w_buff1~0=v_~z$w_buff1~0_7, Thread0_P2_#in~arg.offset=|v_Thread0_P2_#in~arg.offset_1|} AuxVars[] AssignedVars[Thread0_P2_~arg.offset, Thread0_P2_~arg.base, Thread0_P2___VERIFIER_assert_~expression, ~z$w_buff0_used~0, ~z$w_buff0~0, Thread0_P2___VERIFIER_assert_#in~expression, ~z$w_buff1_used~0, ~z$w_buff1~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [577] L4-->L4-3: Formula: (not (= 0 v_Thread0_P2___VERIFIER_assert_~expression_3)) InVars {Thread0_P2___VERIFIER_assert_~expression=v_Thread0_P2___VERIFIER_assert_~expression_3} OutVars{Thread0_P2___VERIFIER_assert_~expression=v_Thread0_P2___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [580] L4-3-->L784: Formula: (and (= v_~z$r_buff1_thd2~0_17 v_~z$r_buff0_thd2~0_31) (= v_~a~0_1 1) (= v_~__unbuffered_p2_EAX~0_1 v_~a~0_1) (= v_~__unbuffered_p2_EBX~0_1 v_~b~0_2) (= v_~z$r_buff1_thd1~0_1 v_~z$r_buff0_thd1~0_1) (= v_~z$r_buff0_thd3~0_7 1) (= v_~z$r_buff1_thd0~0_1 v_~z$r_buff0_thd0~0_1) (= v_~z$r_buff1_thd3~0_5 v_~z$r_buff0_thd3~0_8)) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_8, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_1, ~b~0=v_~b~0_2, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_31} OutVars{~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_1, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_5, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_17, ~a~0=v_~a~0_1, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~b~0=v_~b~0_2, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_1, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_1, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_7, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_1, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_1, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_31} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p2_EBX~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~z$r_buff0_thd3~0, ~__unbuffered_p2_EAX~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [581] L784-->L784-5: Formula: (and (= |v_Thread0_P2_#t~ite29_1| v_~z$w_buff0~0_9) (not (= (mod v_~z$w_buff0_used~0_38 256) 0)) (not (= 0 (mod v_~z$r_buff0_thd3~0_9 256)))) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_9, ~z$w_buff0~0=v_~z$w_buff0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_38} OutVars{Thread0_P2_#t~ite29=|v_Thread0_P2_#t~ite29_1|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_9, ~z$w_buff0~0=v_~z$w_buff0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_38} AuxVars[] AssignedVars[Thread0_P2_#t~ite29] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [504] P0ENTRY-->L724: Formula: (and (= v_Thread1_P0_~arg.base_1 |v_Thread1_P0_#in~arg.base_1|) (= v_Thread1_P0_~arg.offset_1 |v_Thread1_P0_#in~arg.offset_1|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1)) (= v_~b~0_1 1) (= v_~x~0_1 1)) InVars {Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, Thread1_P0_~arg.offset=v_Thread1_P0_~arg.offset_1, ~b~0=v_~b~0_1, Thread1_P0_~arg.base=v_Thread1_P0_~arg.base_1, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x~0=v_~x~0_1} AuxVars[] AssignedVars[Thread1_P0_~arg.offset, ~b~0, Thread1_P0_~arg.base, ~__unbuffered_cnt~0, ~x~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [508] P1ENTRY-->L742: Formula: (and (= v_Thread2_P1_~arg.offset_1 |v_Thread2_P1_#in~arg.offset_1|) (= v_~z$mem_tmp~0_1 v_~z~0_1) (= v_~weak$$choice2~0_2 (ite (= (+ |v_Thread2_P1_#t~nondet5.base_1| |v_Thread2_P1_#t~nondet5.offset_1|) 0) 0 1)) (= v_Thread2_P1_~arg.base_1 |v_Thread2_P1_#in~arg.base_1|) (= v_~x~0_2 2) (= v_~weak$$choice0~0_1 (ite (= (+ |v_Thread2_P1_#t~nondet4.base_1| |v_Thread2_P1_#t~nondet4.offset_1|) 0) 0 1)) (= v_~z$flush_delayed~0_1 v_~weak$$choice2~0_2) (= v_~__unbuffered_p1_EAX~0_1 v_~y~0_1) (= v_~y~0_1 1)) InVars {Thread2_P1_#in~arg.base=|v_Thread2_P1_#in~arg.base_1|, Thread2_P1_#t~nondet5.base=|v_Thread2_P1_#t~nondet5.base_1|, Thread2_P1_#t~nondet5.offset=|v_Thread2_P1_#t~nondet5.offset_1|, Thread2_P1_#t~nondet4.base=|v_Thread2_P1_#t~nondet4.base_1|, ~z~0=v_~z~0_1, Thread2_P1_#t~nondet4.offset=|v_Thread2_P1_#t~nondet4.offset_1|, Thread2_P1_#in~arg.offset=|v_Thread2_P1_#in~arg.offset_1|} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_1, Thread2_P1_#in~arg.base=|v_Thread2_P1_#in~arg.base_1|, Thread2_P1_~arg.offset=v_Thread2_P1_~arg.offset_1, Thread2_P1_#t~nondet5.base=|v_Thread2_P1_#t~nondet5.base_2|, ~z$flush_delayed~0=v_~z$flush_delayed~0_1, Thread2_P1_#t~nondet4.offset=|v_Thread2_P1_#t~nondet4.offset_2|, Thread2_P1_#in~arg.offset=|v_Thread2_P1_#in~arg.offset_1|, ~weak$$choice0~0=v_~weak$$choice0~0_1, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, Thread2_P1_~arg.base=v_Thread2_P1_~arg.base_1, Thread2_P1_#t~nondet5.offset=|v_Thread2_P1_#t~nondet5.offset_2|, Thread2_P1_#t~nondet4.base=|v_Thread2_P1_#t~nondet4.base_2|, ~z~0=v_~z~0_1, ~weak$$choice2~0=v_~weak$$choice2~0_2, ~y~0=v_~y~0_1, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[~z$mem_tmp~0, Thread2_P1_~arg.offset, Thread2_P1_#t~nondet5.base, ~z$flush_delayed~0, Thread2_P1_#t~nondet4.offset, ~weak$$choice0~0, ~__unbuffered_p1_EAX~0, Thread2_P1_~arg.base, Thread2_P1_#t~nondet5.offset, Thread2_P1_#t~nondet4.base, ~weak$$choice2~0, ~y~0, ~x~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [509] L742-->L742-5: Formula: (and (let ((.cse0 (= (mod v_~z$r_buff0_thd2~0_3 256) 0))) (or (and .cse0 (= 0 (mod v_~z$r_buff1_thd2~0_3 256))) (= (mod v_~z$w_buff0_used~0_3 256) 0) (and (= 0 (mod v_~z$w_buff1_used~0_3 256)) .cse0))) (= |v_Thread2_P1_#t~ite7_1| v_~z~0_2)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_3, ~z~0=v_~z~0_2, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_3, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_3, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_3} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_3, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_3, Thread2_P1_#t~ite7=|v_Thread2_P1_#t~ite7_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_3, ~z~0=v_~z~0_2, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_3} AuxVars[] AssignedVars[Thread2_P1_#t~ite7] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [583] L784-5-->L785: Formula: (= v_~z~0_8 |v_Thread0_P2_#t~ite29_2|) InVars {Thread0_P2_#t~ite29=|v_Thread0_P2_#t~ite29_2|} OutVars{Thread0_P2_#t~ite29=|v_Thread0_P2_#t~ite29_3|, Thread0_P2_#t~ite28=|v_Thread0_P2_#t~ite28_1|, ~z~0=v_~z~0_8} AuxVars[] AssignedVars[Thread0_P2_#t~ite29, Thread0_P2_#t~ite28, ~z~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [586] L785-->L785-2: Formula: (and (not (= 0 (mod v_~z$w_buff0_used~0_40 256))) (= |v_Thread0_P2_#t~ite30_1| 0) (not (= 0 (mod v_~z$r_buff0_thd3~0_11 256)))) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_40, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_11} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_11, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_40, Thread0_P2_#t~ite30=|v_Thread0_P2_#t~ite30_1|} AuxVars[] AssignedVars[Thread0_P2_#t~ite30] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite30|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [589] L785-2-->L786: Formula: (= v_~z$w_buff0_used~0_42 |v_Thread0_P2_#t~ite30_3|) InVars {Thread0_P2_#t~ite30=|v_Thread0_P2_#t~ite30_3|} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_42, Thread0_P2_#t~ite30=|v_Thread0_P2_#t~ite30_4|} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread0_P2_#t~ite30] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [591] L786-->L786-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd3~0_1 256)) (= 0 (mod v_~z$w_buff0_used~0_31 256))) (or (= (mod v_~z$w_buff1_used~0_17 256) 0) (= 0 (mod v_~z$r_buff1_thd3~0_1 256))) (= |v_Thread0_P2_#t~ite31_2| v_~z$w_buff1_used~0_17)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_1, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_31, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_1} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_1, Thread0_P2_#t~ite31=|v_Thread0_P2_#t~ite31_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_31, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_1} AuxVars[] AssignedVars[Thread0_P2_#t~ite31] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite31|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [592] L786-2-->L787: Formula: (= v_~z$w_buff1_used~0_18 |v_Thread0_P2_#t~ite31_3|) InVars {Thread0_P2_#t~ite31=|v_Thread0_P2_#t~ite31_3|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_18, Thread0_P2_#t~ite31=|v_Thread0_P2_#t~ite31_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread0_P2_#t~ite31] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [594] L787-->L787-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd3~0_3 256)) (= (mod v_~z$w_buff0_used~0_33 256) 0)) (= |v_Thread0_P2_#t~ite32_2| v_~z$r_buff0_thd3~0_3)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_33, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_3} OutVars{Thread0_P2_#t~ite32=|v_Thread0_P2_#t~ite32_2|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_3, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_33} AuxVars[] AssignedVars[Thread0_P2_#t~ite32] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite32|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [595] L787-2-->L788: Formula: (= v_~z$r_buff0_thd3~0_4 |v_Thread0_P2_#t~ite32_3|) InVars {Thread0_P2_#t~ite32=|v_Thread0_P2_#t~ite32_3|} OutVars{Thread0_P2_#t~ite32=|v_Thread0_P2_#t~ite32_4|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_4} AuxVars[] AssignedVars[Thread0_P2_#t~ite32, ~z$r_buff0_thd3~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [597] L788-->L788-2: Formula: (and (= |v_Thread0_P2_#t~ite33_2| v_~z$r_buff1_thd3~0_3) (or (= 0 (mod v_~z$r_buff0_thd3~0_6 256)) (= (mod v_~z$w_buff0_used~0_35 256) 0)) (or (= (mod v_~z$r_buff1_thd3~0_3 256) 0) (= (mod v_~z$w_buff1_used~0_20 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_20, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_6, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_35, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_3} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_20, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_6, Thread0_P2_#t~ite33=|v_Thread0_P2_#t~ite33_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_35, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_3} AuxVars[] AssignedVars[Thread0_P2_#t~ite33] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite33|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [598] L788-2-->L793: Formula: (and (= v_~z$r_buff1_thd3~0_4 |v_Thread0_P2_#t~ite33_3|) (= v_~__unbuffered_cnt~0_5 (+ v_~__unbuffered_cnt~0_6 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6, Thread0_P2_#t~ite33=|v_Thread0_P2_#t~ite33_3|} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, Thread0_P2_#t~ite33=|v_Thread0_P2_#t~ite33_4|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_4} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, Thread0_P2_#t~ite33] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 [511] L742-5-->L743: Formula: (= v_~z~0_4 |v_Thread2_P1_#t~ite7_2|) InVars {Thread2_P1_#t~ite7=|v_Thread2_P1_#t~ite7_2|} OutVars{Thread2_P1_#t~ite7=|v_Thread2_P1_#t~ite7_3|, ~z~0=v_~z~0_4, Thread2_P1_#t~ite6=|v_Thread2_P1_#t~ite6_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite7, ~z~0, Thread2_P1_#t~ite6] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [514] L743-->L743-8: Formula: (and (= |v_Thread2_P1_#t~ite10_1| v_~z$w_buff0~0_2) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_2} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_2, Thread2_P1_#t~ite10=|v_Thread2_P1_#t~ite10_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite10] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite10|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [517] L743-8-->L744: Formula: (= v_~z$w_buff0~0_6 |v_Thread2_P1_#t~ite10_2|) InVars {Thread2_P1_#t~ite10=|v_Thread2_P1_#t~ite10_2|} OutVars{Thread2_P1_#t~ite8=|v_Thread2_P1_#t~ite8_1|, Thread2_P1_#t~ite9=|v_Thread2_P1_#t~ite9_1|, ~z$w_buff0~0=v_~z$w_buff0~0_6, Thread2_P1_#t~ite10=|v_Thread2_P1_#t~ite10_3|} AuxVars[] AssignedVars[~z$w_buff0~0, Thread2_P1_#t~ite10, Thread2_P1_#t~ite8, Thread2_P1_#t~ite9] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [520] L744-->L744-8: Formula: (and (= |v_Thread2_P1_#t~ite13_1| v_~z$w_buff1~0_2) (not (= 0 (mod v_~weak$$choice2~0_5 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~z$w_buff1~0=v_~z$w_buff1~0_2} OutVars{Thread2_P1_#t~ite13=|v_Thread2_P1_#t~ite13_1|, ~z$w_buff1~0=v_~z$w_buff1~0_2, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[Thread2_P1_#t~ite13] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite13|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [525] L744-8-->L745: Formula: (= v_~z$w_buff1~0_6 |v_Thread2_P1_#t~ite13_2|) InVars {Thread2_P1_#t~ite13=|v_Thread2_P1_#t~ite13_2|} OutVars{Thread2_P1_#t~ite13=|v_Thread2_P1_#t~ite13_3|, Thread2_P1_#t~ite12=|v_Thread2_P1_#t~ite12_1|, ~z$w_buff1~0=v_~z$w_buff1~0_6, Thread2_P1_#t~ite11=|v_Thread2_P1_#t~ite11_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite11, Thread2_P1_#t~ite13, Thread2_P1_#t~ite12, ~z$w_buff1~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [529] L745-->L745-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_7 256))) (= |v_Thread2_P1_#t~ite16_1| v_~z$w_buff0_used~0_17)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_17} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_17, Thread2_P1_#t~ite16=|v_Thread2_P1_#t~ite16_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite16] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite16|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [534] L745-8-->L746: Formula: (= v_~z$w_buff0_used~0_22 |v_Thread2_P1_#t~ite16_2|) InVars {Thread2_P1_#t~ite16=|v_Thread2_P1_#t~ite16_2|} OutVars{Thread2_P1_#t~ite15=|v_Thread2_P1_#t~ite15_1|, Thread2_P1_#t~ite14=|v_Thread2_P1_#t~ite14_1|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_22, Thread2_P1_#t~ite16=|v_Thread2_P1_#t~ite16_3|} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread2_P1_#t~ite15, Thread2_P1_#t~ite14, Thread2_P1_#t~ite16] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [538] L746-->L746-8: Formula: (and (= |v_Thread2_P1_#t~ite19_1| v_~z$w_buff1_used~0_11) (not (= (mod v_~weak$$choice2~0_9 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_11, ~weak$$choice2~0=v_~weak$$choice2~0_9} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_11, ~weak$$choice2~0=v_~weak$$choice2~0_9, Thread2_P1_#t~ite19=|v_Thread2_P1_#t~ite19_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite19] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite19|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [543] L746-8-->L747: Formula: (= v_~z$w_buff1_used~0_14 |v_Thread2_P1_#t~ite19_2|) InVars {Thread2_P1_#t~ite19=|v_Thread2_P1_#t~ite19_2|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_14, Thread2_P1_#t~ite17=|v_Thread2_P1_#t~ite17_1|, Thread2_P1_#t~ite19=|v_Thread2_P1_#t~ite19_3|, Thread2_P1_#t~ite18=|v_Thread2_P1_#t~ite18_1|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread2_P1_#t~ite17, Thread2_P1_#t~ite19, Thread2_P1_#t~ite18] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [547] L747-->L747-8: Formula: (and (not (= (mod v_~weak$$choice2~0_11 256) 0)) (= |v_Thread2_P1_#t~ite22_1| v_~z$r_buff0_thd2~0_25)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_11, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_11, Thread2_P1_#t~ite22=|v_Thread2_P1_#t~ite22_1|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} AuxVars[] AssignedVars[Thread2_P1_#t~ite22] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite22|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [552] L747-8-->L748: Formula: (= v_~z$r_buff0_thd2~0_30 |v_Thread2_P1_#t~ite22_2|) InVars {Thread2_P1_#t~ite22=|v_Thread2_P1_#t~ite22_2|} OutVars{Thread2_P1_#t~ite21=|v_Thread2_P1_#t~ite21_1|, Thread2_P1_#t~ite22=|v_Thread2_P1_#t~ite22_3|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_30, Thread2_P1_#t~ite20=|v_Thread2_P1_#t~ite20_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite21, Thread2_P1_#t~ite22, Thread2_P1_#t~ite20, ~z$r_buff0_thd2~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [556] L748-->L748-8: Formula: (and (not (= (mod v_~weak$$choice2~0_13 256) 0)) (= |v_Thread2_P1_#t~ite25_1| v_~z$r_buff1_thd2~0_16)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_13, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_16} OutVars{Thread2_P1_#t~ite25=|v_Thread2_P1_#t~ite25_1|, ~weak$$choice2~0=v_~weak$$choice2~0_13, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_16} AuxVars[] AssignedVars[Thread2_P1_#t~ite25] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite25|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [561] L748-8-->L750: Formula: (and (= v_~__unbuffered_p1_EBX~0_1 v_~z~0_3) (= v_~z$r_buff1_thd2~0_5 |v_Thread2_P1_#t~ite25_2|)) InVars {Thread2_P1_#t~ite25=|v_Thread2_P1_#t~ite25_2|, ~z~0=v_~z~0_3} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_1, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_5, Thread2_P1_#t~ite25=|v_Thread2_P1_#t~ite25_3|, Thread2_P1_#t~ite23=|v_Thread2_P1_#t~ite23_1|, Thread2_P1_#t~ite24=|v_Thread2_P1_#t~ite24_1|, ~z~0=v_~z~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0, ~z$r_buff1_thd2~0, Thread2_P1_#t~ite25, Thread2_P1_#t~ite23, Thread2_P1_#t~ite24] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [565] L750-->L750-2: Formula: (and (not (= (mod v_~z$flush_delayed~0_2 256) 0)) (= |v_Thread2_P1_#t~ite26_1| v_~z$mem_tmp~0_2)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_2, ~z$flush_delayed~0=v_~z$flush_delayed~0_2} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_2, Thread2_P1_#t~ite26=|v_Thread2_P1_#t~ite26_1|, ~z$flush_delayed~0=v_~z$flush_delayed~0_2} AuxVars[] AssignedVars[Thread2_P1_#t~ite26] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite26|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [570] L750-2-->L758: Formula: (and (= v_~z~0_6 |v_Thread2_P1_#t~ite26_3|) (= v_~z$flush_delayed~0_4 0) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {Thread2_P1_#t~ite26=|v_Thread2_P1_#t~ite26_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4} OutVars{Thread2_P1_#t~ite26=|v_Thread2_P1_#t~ite26_4|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, ~z$flush_delayed~0=v_~z$flush_delayed~0_4, ~z~0=v_~z~0_6} AuxVars[] AssignedVars[Thread2_P1_#t~ite26, ~__unbuffered_cnt~0, ~z$flush_delayed~0, ~z~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [336] L811-1-->L815: Formula: (= v_~main$tmp_guard0~0_1 (ite (= (ite (= v_~__unbuffered_cnt~0_7 3) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_7} OutVars{ULTIMATE.start_main_#t~nondet37=|v_ULTIMATE.start_main_#t~nondet37_1|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_7, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet37, ~main$tmp_guard0~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [444] L815-->L817: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_2 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [479] L817-->L817-2: Formula: (or (= 0 (mod v_~z$w_buff0_used~0_45 256)) (= (mod v_~z$r_buff0_thd0~0_3 256) 0)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_45, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_3} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_45, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [485] L817-2-->L817-4: Formula: (and (or (= 0 (mod v_~z$w_buff1_used~0_26 256)) (= (mod v_~z$r_buff1_thd0~0_3 256) 0)) (= |v_ULTIMATE.start_main_#t~ite38_2| v_~z~0_9)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_26, ~z~0=v_~z~0_9, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_3} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_26, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_2|, ~z~0=v_~z~0_9, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite38] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [475] L817-4-->L817-5: Formula: (= |v_ULTIMATE.start_main_#t~ite39_2| |v_ULTIMATE.start_main_#t~ite38_3|) InVars {ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_3|} OutVars{ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_2|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_#t~ite39|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [477] L817-5-->L818: Formula: (= v_~z~0_10 |v_ULTIMATE.start_main_#t~ite39_4|) InVars {ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_4|} OutVars{ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_4|, ~z~0=v_~z~0_10, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38, ~z~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [412] L818-->L818-2: Formula: (and (or (= (mod v_~z$r_buff0_thd0~0_5 256) 0) (= (mod v_~z$w_buff0_used~0_47 256) 0)) (= |v_ULTIMATE.start_main_#t~ite40_2| v_~z$w_buff0_used~0_47)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_47, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_5} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_5, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_47} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [419] L818-2-->L819: Formula: (= v_~z$w_buff0_used~0_48 |v_ULTIMATE.start_main_#t~ite40_4|) InVars {ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_4|} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_48, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ~z$w_buff0_used~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [341] L819-->L819-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite41_2| v_~z$w_buff1_used~0_28) (or (= 0 (mod v_~z$w_buff0_used~0_50 256)) (= 0 (mod v_~z$r_buff0_thd0~0_7 256))) (or (= (mod v_~z$r_buff1_thd0~0_5 256) 0) (= (mod v_~z$w_buff1_used~0_28 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_28, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_50, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_5} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_28, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_2|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_50, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_5} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite41|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [345] L819-2-->L820: Formula: (= v_~z$w_buff1_used~0_29 |v_ULTIMATE.start_main_#t~ite41_4|) InVars {ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_4|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_29, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$w_buff1_used~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [453] L820-->L820-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite42_2| v_~z$r_buff0_thd0~0_9) (or (= 0 (mod v_~z$r_buff0_thd0~0_9 256)) (= 0 (mod v_~z$w_buff0_used~0_52 256)))) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_52, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_9} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_52, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [459] L820-2-->L821: Formula: (= v_~z$r_buff0_thd0~0_10 |v_ULTIMATE.start_main_#t~ite42_4|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} OutVars{ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_3|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_10} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [407] L821-->L821-2: Formula: (and (or (= (mod v_~z$r_buff0_thd0~0_12 256) 0) (= 0 (mod v_~z$w_buff0_used~0_54 256))) (or (= (mod v_~z$r_buff1_thd0~0_7 256) 0) (= (mod v_~z$w_buff1_used~0_31 256) 0)) (= |v_ULTIMATE.start_main_#t~ite43_2| v_~z$r_buff1_thd0~0_7)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_31, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_12, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_54, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_7} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_31, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_12, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_54, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [388] L821-2-->L826: Formula: (and (= v_~z$r_buff1_thd0~0_8 |v_ULTIMATE.start_main_#t~ite43_4|) (= v_~main$tmp_guard1~0_1 (ite (= (ite (not (and (= 2 v_~x~0_3) (= v_~__unbuffered_p2_EBX~0_2 0) (= 0 v_~__unbuffered_p1_EBX~0_2) (= 1 v_~__unbuffered_p1_EAX~0_2) (= v_~__unbuffered_p2_EAX~0_2 1))) 1 0) 0) 0 1))) InVars {~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_2, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|, ~x~0=v_~x~0_3} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_8, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_1, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_2, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ~x~0=v_~x~0_3} AuxVars[] AssignedVars[~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite43] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [443] L826-->L826-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_2 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [421] L826-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [379] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [375] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [371] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 ~b~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t896~0.base, main_~#t896~0.offset, main_~#t897~0.base, main_~#t897~0.offset, main_~#t898~0.base, main_~#t898~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t896~0.base, main_~#t896~0.offset := #Ultimate.alloc(4); srcloc: L806 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t896~0.base, main_~#t896~0.offset, 4); srcloc: L806-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t897~0.base, main_~#t897~0.offset := #Ultimate.alloc(4); srcloc: L808 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t897~0.base, main_~#t897~0.offset, 4); srcloc: L808-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet36; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t898~0.base, main_~#t898~0.offset := #Ultimate.alloc(4); srcloc: L810 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(2, main_~#t898~0.base, main_~#t898~0.offset, 4); srcloc: L810-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 2 P2(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0;~z$r_buff0_thd3~0 := 1;~a~0 := 1;~__unbuffered_p2_EAX~0 := ~a~0;~__unbuffered_p2_EBX~0 := ~b~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite29 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~b~0 := 1;~x~0 := 1;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x~0 := 2;~y~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1);havoc #t~nondet4.base, #t~nondet4.offset;~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1);havoc #t~nondet5.base, #t~nondet5.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite7 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite29;havoc #t~ite29;havoc #t~ite28; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite30 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite30;havoc #t~ite30; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite31 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite31|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite31;havoc #t~ite31; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256);#t~ite32 := ~z$r_buff0_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite32|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd3~0 := #t~ite32;havoc #t~ite32; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite33 := ~z$r_buff1_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite33|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd3~0 := #t~ite33;havoc #t~ite33;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 ~z~0 := #t~ite7;havoc #t~ite7;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite10 := ~z$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite10|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0~0 := #t~ite10;havoc #t~ite9;havoc #t~ite10;havoc #t~ite8; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite13 := ~z$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12;havoc #t~ite11; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0_used~0 := #t~ite16;havoc #t~ite14;havoc #t~ite15;havoc #t~ite16; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1_used~0 := #t~ite19;havoc #t~ite19;havoc #t~ite18;havoc #t~ite17; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff0_thd2~0 := #t~ite22;havoc #t~ite22;havoc #t~ite21;havoc #t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff1_thd2~0 := #t~ite25;havoc #t~ite24;havoc #t~ite25;havoc #t~ite23;~__unbuffered_p1_EBX~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~z$flush_delayed~0 % 256;#t~ite26 := ~z$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z~0 := #t~ite26;havoc #t~ite26;~z$flush_delayed~0 := 0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet37;~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite38 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite39 := main_#t~ite38; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_#t~ite39|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite39;havoc main_#t~ite38;havoc main_#t~ite39; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite40 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite40;havoc main_#t~ite40; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite41 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite41|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite41;havoc main_#t~ite41; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite42;havoc main_#t~ite42; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite43;havoc main_#t~ite43;~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 ~b~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t896~0.base, main_~#t896~0.offset, main_~#t897~0.base, main_~#t897~0.offset, main_~#t898~0.base, main_~#t898~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t896~0.base, main_~#t896~0.offset := #Ultimate.alloc(4); srcloc: L806 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t896~0.base, main_~#t896~0.offset, 4); srcloc: L806-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t897~0.base, main_~#t897~0.offset := #Ultimate.alloc(4); srcloc: L808 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t897~0.base, main_~#t897~0.offset, 4); srcloc: L808-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet36; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t898~0.base, main_~#t898~0.offset := #Ultimate.alloc(4); srcloc: L810 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(2, main_~#t898~0.base, main_~#t898~0.offset, 4); srcloc: L810-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 2 P2(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0;~z$r_buff0_thd3~0 := 1;~a~0 := 1;~__unbuffered_p2_EAX~0 := ~a~0;~__unbuffered_p2_EBX~0 := ~b~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite29 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~b~0 := 1;~x~0 := 1;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x~0 := 2;~y~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1);havoc #t~nondet4.base, #t~nondet4.offset;~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1);havoc #t~nondet5.base, #t~nondet5.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite7 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite29;havoc #t~ite29;havoc #t~ite28; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite30 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite30;havoc #t~ite30; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite31 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite31|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite31;havoc #t~ite31; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256);#t~ite32 := ~z$r_buff0_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite32|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd3~0 := #t~ite32;havoc #t~ite32; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite33 := ~z$r_buff1_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite33|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd3~0 := #t~ite33;havoc #t~ite33;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 ~z~0 := #t~ite7;havoc #t~ite7;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite10 := ~z$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite10|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0~0 := #t~ite10;havoc #t~ite9;havoc #t~ite10;havoc #t~ite8; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite13 := ~z$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12;havoc #t~ite11; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0_used~0 := #t~ite16;havoc #t~ite14;havoc #t~ite15;havoc #t~ite16; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1_used~0 := #t~ite19;havoc #t~ite19;havoc #t~ite18;havoc #t~ite17; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff0_thd2~0 := #t~ite22;havoc #t~ite22;havoc #t~ite21;havoc #t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff1_thd2~0 := #t~ite25;havoc #t~ite24;havoc #t~ite25;havoc #t~ite23;~__unbuffered_p1_EBX~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~z$flush_delayed~0 % 256;#t~ite26 := ~z$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z~0 := #t~ite26;havoc #t~ite26;~z$flush_delayed~0 := 0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet37;~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite38 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite39 := main_#t~ite38; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_#t~ite39|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite39;havoc main_#t~ite38;havoc main_#t~ite39; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite40 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite40;havoc main_#t~ite40; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite41 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite41|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite41;havoc main_#t~ite41; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite42;havoc main_#t~ite42; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite43;havoc main_#t~ite43;~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t896~0.base, main_~#t896~0.offset, main_~#t897~0.base, main_~#t897~0.offset, main_~#t898~0.base, main_~#t898~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] -1 call main_~#t896~0.base, main_~#t896~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 call write~int(0, main_~#t896~0.base, main_~#t896~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] -1 call main_~#t897~0.base, main_~#t897~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 call write~int(1, main_~#t897~0.base, main_~#t897~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] -1 call main_~#t898~0.base, main_~#t898~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 call write~int(2, main_~#t898~0.base, main_~#t898~0.offset, 4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1); [L738] 2 havoc #t~nondet4.base, #t~nondet4.offset; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1); [L739] 2 havoc #t~nondet5.base, #t~nondet5.offset; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L785] 0 #t~ite30 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256); [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 assume 0 != ~weak$$choice2~0 % 256; [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 assume 0 != ~weak$$choice2~0 % 256; [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 assume 0 != ~weak$$choice2~0 % 256; [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 assume 0 != ~weak$$choice2~0 % 256; [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 assume 0 != ~weak$$choice2~0 % 256; [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 assume 0 != ~weak$$choice2~0 % 256; [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 assume 0 != ~z$flush_delayed~0 % 256; [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t896~0.base, main_~#t896~0.offset, main_~#t897~0.base, main_~#t897~0.offset, main_~#t898~0.base, main_~#t898~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] -1 call main_~#t896~0.base, main_~#t896~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 call write~int(0, main_~#t896~0.base, main_~#t896~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] -1 call main_~#t897~0.base, main_~#t897~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 call write~int(1, main_~#t897~0.base, main_~#t897~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] -1 call main_~#t898~0.base, main_~#t898~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 call write~int(2, main_~#t898~0.base, main_~#t898~0.offset, 4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1); [L738] 2 havoc #t~nondet4.base, #t~nondet4.offset; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1); [L739] 2 havoc #t~nondet5.base, #t~nondet5.offset; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L785] 0 #t~ite30 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256); [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 assume 0 != ~weak$$choice2~0 % 256; [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 assume 0 != ~weak$$choice2~0 % 256; [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 assume 0 != ~weak$$choice2~0 % 256; [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 assume 0 != ~weak$$choice2~0 % 256; [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 assume 0 != ~weak$$choice2~0 % 256; [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 assume 0 != ~weak$$choice2~0 % 256; [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 assume 0 != ~z$flush_delayed~0 % 256; [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t896~0, main_~#t897~0, main_~#t898~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call main_~#t896~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, main_~#t896~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call main_~#t897~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, main_~#t897~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call main_~#t898~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, main_~#t898~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t896~0, main_~#t897~0, main_~#t898~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call main_~#t896~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, main_~#t896~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call main_~#t897~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, main_~#t897~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call main_~#t898~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, main_~#t898~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call ~#t896~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, ~#t896~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call ~#t897~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, ~#t897~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc #t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call ~#t898~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, ~#t898~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc #t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 #t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 #t~ite39 := #t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := #t~ite39; [L817] -1 havoc #t~ite38; [L817] -1 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := #t~ite40; [L818] -1 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 #t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := #t~ite41; [L819] -1 havoc #t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 #t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := #t~ite42; [L820] -1 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 #t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := #t~ite43; [L821] -1 havoc #t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call ~#t896~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, ~#t896~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call ~#t897~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, ~#t897~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc #t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call ~#t898~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, ~#t898~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc #t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 #t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 #t~ite39 := #t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := #t~ite39; [L817] -1 havoc #t~ite38; [L817] -1 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := #t~ite40; [L818] -1 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 #t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := #t~ite41; [L819] -1 havoc #t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 #t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := #t~ite42; [L820] -1 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 #t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := #t~ite43; [L821] -1 havoc #t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L672] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L674] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L676] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L678] -1 int __unbuffered_p2_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0] [L680] -1 int __unbuffered_p2_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0] [L682] -1 int a = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0] [L684] -1 int b = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0] [L685] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0] [L686] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0] [L688] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L690] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L692] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L693] -1 _Bool z$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0] [L694] -1 int z$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0] [L695] -1 _Bool z$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0] [L696] -1 _Bool z$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0] [L697] -1 _Bool z$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0] [L698] -1 _Bool z$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0] [L699] -1 _Bool z$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0] [L700] -1 _Bool z$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0] [L701] -1 _Bool z$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0] [L702] -1 _Bool z$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0] [L703] -1 _Bool z$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0] [L704] -1 int *z$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}] [L705] -1 int z$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0] [L706] -1 _Bool z$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0] [L707] -1 int z$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0] [L708] -1 _Bool z$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L709] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L710] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L806] -1 pthread_t t896; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L807] FCALL, FORK -1 pthread_create(&t896, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L808] -1 pthread_t t897; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L809] FCALL, FORK -1 pthread_create(&t897, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L810] -1 pthread_t t898; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L811] FCALL, FORK -1 pthread_create(&t898, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L763] 0 z$w_buff1 = z$w_buff0 [L764] 0 z$w_buff0 = 1 [L765] 0 z$w_buff1_used = z$w_buff0_used [L766] 0 z$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] 0 z$r_buff1_thd0 = z$r_buff0_thd0 [L769] 0 z$r_buff1_thd1 = z$r_buff0_thd1 [L770] 0 z$r_buff1_thd2 = z$r_buff0_thd2 [L771] 0 z$r_buff1_thd3 = z$r_buff0_thd3 [L772] 0 z$r_buff0_thd3 = (_Bool)1 [L775] 0 a = 1 [L778] 0 __unbuffered_p2_EAX = a [L781] 0 __unbuffered_p2_EBX = b VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L714] 1 b = 1 [L717] 1 x = 1 [L722] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L729] 2 x = 2 [L732] 2 y = 1 [L735] 2 __unbuffered_p1_EAX = y [L738] 2 weak$$choice0 = __VERIFIER_nondet_pointer() [L739] 2 weak$$choice2 = __VERIFIER_nondet_pointer() [L740] 2 z$flush_delayed = weak$$choice2 [L741] 2 z$mem_tmp = z VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] EXPR 2 !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] 0 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L785] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L785] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L786] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L786] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L787] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L787] 0 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L788] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L788] 0 z$r_buff1_thd3 = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 [L791] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L742] 2 z = !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) [L743] EXPR 2 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0))=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L743] 2 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) [L744] EXPR 2 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L744] 2 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) [L745] EXPR 2 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L745] 2 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) [L746] EXPR 2 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L746] 2 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L747] EXPR 2 weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L747] 2 z$r_buff0_thd2 = weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) [L748] EXPR 2 weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L748] 2 z$r_buff1_thd2 = weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L749] 2 __unbuffered_p1_EBX = z VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L750] EXPR 2 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L750] 2 z = z$flush_delayed ? z$mem_tmp : z [L751] 2 z$flush_delayed = (_Bool)0 [L756] 2 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L813] -1 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] -1 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L818] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] -1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L819] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L819] -1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L820] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L820] -1 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L821] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L821] -1 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L824] -1 main$tmp_guard1 = !(x == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 0) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] ----- [2018-11-22 21:52:25,724 INFO L305 ceAbstractionStarter]: Did not count any witness invariants because Icfg is not BoogieIcfg [2018-11-22 21:52:25,725 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 22.11 09:52:25 BasicIcfg [2018-11-22 21:52:25,726 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-22 21:52:25,726 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-22 21:52:25,726 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-22 21:52:25,726 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-22 21:52:25,748 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 09:49:56" (3/4) ... [2018-11-22 21:52:25,750 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [457] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [337] L-1-->L672: Formula: (= |v_#valid_7| (store |v_#valid_8| 0 0)) InVars {#valid=|v_#valid_8|} OutVars{#valid=|v_#valid_7|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [428] L672-->L674: Formula: (= v_~__unbuffered_cnt~0_8 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_8} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [476] L674-->L676: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [325] L676-->L678: Formula: (= v_~__unbuffered_p1_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 [394] L678-->L680: Formula: (= v_~__unbuffered_p2_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p2_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 [433] L680-->L682: Formula: (= v_~__unbuffered_p2_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p2_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 [491] L682-->L684: Formula: (= v_~a~0_2 0) InVars {} OutVars{~a~0=v_~a~0_2} AuxVars[] AssignedVars[~a~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 [361] L684-->L685: Formula: (= v_~b~0_3 0) InVars {} OutVars{~b~0=v_~b~0_3} AuxVars[] AssignedVars[~b~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [?] -1 [474] L685-->L686: Formula: (= v_~main$tmp_guard0~0_3 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [?] -1 [398] L686-->L688: Formula: (= v_~main$tmp_guard1~0_3 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [464] L688-->L690: Formula: (= v_~x~0_4 0) InVars {} OutVars{~x~0=v_~x~0_4} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [498] L690-->L692: Formula: (= v_~y~0_2 0) InVars {} OutVars{~y~0=v_~y~0_2} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 [364] L692-->L693: Formula: (= v_~z~0_11 0) InVars {} OutVars{~z~0=v_~z~0_11} AuxVars[] AssignedVars[~z~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [489] L693-->L694: Formula: (= v_~z$flush_delayed~0_5 0) InVars {} OutVars{~z$flush_delayed~0=v_~z$flush_delayed~0_5} AuxVars[] AssignedVars[~z$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 [426] L694-->L695: Formula: (= v_~z$mem_tmp~0_3 0) InVars {} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_3} AuxVars[] AssignedVars[~z$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 [360] L695-->L696: Formula: (= v_~z$r_buff0_thd0~0_13 0) InVars {} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_13} AuxVars[] AssignedVars[~z$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 [473] L696-->L697: Formula: (= v_~z$r_buff0_thd1~0_2 0) InVars {} OutVars{~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_2} AuxVars[] AssignedVars[~z$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 [397] L697-->L698: Formula: (= v_~z$r_buff0_thd2~0_32 0) InVars {} OutVars{~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32} AuxVars[] AssignedVars[~z$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 [351] L698-->L699: Formula: (= v_~z$r_buff0_thd3~0_14 0) InVars {} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_14} AuxVars[] AssignedVars[~z$r_buff0_thd3~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 [463] L699-->L700: Formula: (= v_~z$r_buff1_thd0~0_9 0) InVars {} OutVars{~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_9} AuxVars[] AssignedVars[~z$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 [393] L700-->L701: Formula: (= v_~z$r_buff1_thd1~0_2 0) InVars {} OutVars{~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_2} AuxVars[] AssignedVars[~z$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 [496] L701-->L702: Formula: (= v_~z$r_buff1_thd2~0_18 0) InVars {} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_18} AuxVars[] AssignedVars[~z$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 [432] L702-->L703: Formula: (= v_~z$r_buff1_thd3~0_9 0) InVars {} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_9} AuxVars[] AssignedVars[~z$r_buff1_thd3~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 [384] L703-->L704: Formula: (= v_~z$read_delayed~0_1 0) InVars {} OutVars{~z$read_delayed~0=v_~z$read_delayed~0_1} AuxVars[] AssignedVars[~z$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [488] L704-->L705: Formula: (and (= v_~z$read_delayed_var~0.offset_1 0) (= v_~z$read_delayed_var~0.base_1 0)) InVars {} OutVars{~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_1, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [425] L705-->L706: Formula: (= v_~z$w_buff0~0_11 0) InVars {} OutVars{~z$w_buff0~0=v_~z$w_buff0~0_11} AuxVars[] AssignedVars[~z$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [359] L706-->L707: Formula: (= v_~z$w_buff0_used~0_55 0) InVars {} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_55} AuxVars[] AssignedVars[~z$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [470] L707-->L708: Formula: (= v_~z$w_buff1~0_10 0) InVars {} OutVars{~z$w_buff1~0=v_~z$w_buff1~0_10} AuxVars[] AssignedVars[~z$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [396] L708-->L709: Formula: (= v_~z$w_buff1_used~0_32 0) InVars {} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_32} AuxVars[] AssignedVars[~z$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [348] L709-->L710: Formula: (= v_~weak$$choice0~0_2 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [462] L710-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [490] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [487] L-1-2-->L806: Formula: true InVars {} OutVars{ULTIMATE.start_main_~#t896~0.offset=|v_ULTIMATE.start_main_~#t896~0.offset_3|, ULTIMATE.start_main_~#t898~0.offset=|v_ULTIMATE.start_main_~#t898~0.offset_4|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_5|, ULTIMATE.start_main_#t~nondet36=|v_ULTIMATE.start_main_#t~nondet36_1|, ULTIMATE.start_main_#t~nondet35=|v_ULTIMATE.start_main_#t~nondet35_1|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_5|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|, ULTIMATE.start_main_~#t898~0.base=|v_ULTIMATE.start_main_~#t898~0.base_4|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_5|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_5|, ULTIMATE.start_main_~#t897~0.offset=|v_ULTIMATE.start_main_~#t897~0.offset_3|, ULTIMATE.start_main_#t~nondet37=|v_ULTIMATE.start_main_#t~nondet37_2|, ULTIMATE.start_main_~#t897~0.base=|v_ULTIMATE.start_main_~#t897~0.base_3|, ULTIMATE.start_main_~#t896~0.base=|v_ULTIMATE.start_main_~#t896~0.base_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t896~0.offset, ULTIMATE.start_main_~#t898~0.offset, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet36, ULTIMATE.start_main_#t~nondet35, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_~#t898~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_~#t897~0.offset, ULTIMATE.start_main_#t~nondet37, ULTIMATE.start_main_~#t897~0.base, ULTIMATE.start_main_~#t896~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [480] L806-->L806-1: Formula: (and (= |v_#length_1| (store |v_#length_2| |v_ULTIMATE.start_main_~#t896~0.base_4| 4)) (= |v_ULTIMATE.start_main_~#t896~0.offset_4| 0) (= |v_#valid_9| (store |v_#valid_10| |v_ULTIMATE.start_main_~#t896~0.base_4| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t896~0.base_4|)) (= 0 (select |v_#valid_10| |v_ULTIMATE.start_main_~#t896~0.base_4|))) InVars {#length=|v_#length_2|, #valid=|v_#valid_10|} OutVars{ULTIMATE.start_main_~#t896~0.offset=|v_ULTIMATE.start_main_~#t896~0.offset_4|, #length=|v_#length_1|, ULTIMATE.start_main_~#t896~0.base=|v_ULTIMATE.start_main_~#t896~0.base_4|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t896~0.offset, #valid, #length, ULTIMATE.start_main_~#t896~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [483] L806-1-->L807: Formula: (= |v_#memory_int_3| (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t896~0.base_5| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t896~0.base_5|) |v_ULTIMATE.start_main_~#t896~0.offset_5| 0))) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t896~0.offset=|v_ULTIMATE.start_main_~#t896~0.offset_5|, ULTIMATE.start_main_~#t896~0.base=|v_ULTIMATE.start_main_~#t896~0.base_5|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t896~0.offset=|v_ULTIMATE.start_main_~#t896~0.offset_5|, ULTIMATE.start_main_~#t896~0.base=|v_ULTIMATE.start_main_~#t896~0.base_5|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [603] L807-->P0ENTRY: Formula: (and (= 0 |v_Thread1_P0_#in~arg.base_3|) (= 0 v_Thread1_P0_thidvar0_2) (= 0 |v_Thread1_P0_#in~arg.offset_3|)) InVars {} OutVars{Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_3|, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_3|, Thread1_P0_thidvar0=v_Thread1_P0_thidvar0_2} AuxVars[] AssignedVars[Thread1_P0_#in~arg.base, Thread1_P0_#in~arg.offset, Thread1_P0_thidvar0] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [416] L807-1-->L808: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet35=|v_ULTIMATE.start_main_#t~nondet35_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet35] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [342] L808-->L808-1: Formula: (and (= |v_ULTIMATE.start_main_~#t897~0.offset_4| 0) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t897~0.base_4| 4)) (= 0 (select |v_#valid_12| |v_ULTIMATE.start_main_~#t897~0.base_4|)) (not (= 0 |v_ULTIMATE.start_main_~#t897~0.base_4|)) (= |v_#valid_11| (store |v_#valid_12| |v_ULTIMATE.start_main_~#t897~0.base_4| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_12|} OutVars{ULTIMATE.start_main_~#t897~0.base=|v_ULTIMATE.start_main_~#t897~0.base_4|, #length=|v_#length_3|, ULTIMATE.start_main_~#t897~0.offset=|v_ULTIMATE.start_main_~#t897~0.offset_4|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t897~0.offset, #valid, ULTIMATE.start_main_~#t897~0.base, #length] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [343] L808-1-->L809: Formula: (= |v_#memory_int_5| (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#t897~0.base_5| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#t897~0.base_5|) |v_ULTIMATE.start_main_~#t897~0.offset_5| 1))) InVars {#memory_int=|v_#memory_int_6|, ULTIMATE.start_main_~#t897~0.base=|v_ULTIMATE.start_main_~#t897~0.base_5|, ULTIMATE.start_main_~#t897~0.offset=|v_ULTIMATE.start_main_~#t897~0.offset_5|} OutVars{#memory_int=|v_#memory_int_5|, ULTIMATE.start_main_~#t897~0.base=|v_ULTIMATE.start_main_~#t897~0.base_5|, ULTIMATE.start_main_~#t897~0.offset=|v_ULTIMATE.start_main_~#t897~0.offset_5|} AuxVars[] AssignedVars[#memory_int] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [604] L809-->P1ENTRY: Formula: (and (= |v_Thread2_P1_#in~arg.base_3| 0) (= v_Thread2_P1_thidvar0_2 1) (= 0 |v_Thread2_P1_#in~arg.offset_3|)) InVars {} OutVars{Thread2_P1_#in~arg.base=|v_Thread2_P1_#in~arg.base_3|, Thread2_P1_thidvar0=v_Thread2_P1_thidvar0_2, Thread2_P1_#in~arg.offset=|v_Thread2_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread2_P1_#in~arg.base, Thread2_P1_thidvar0, Thread2_P1_#in~arg.offset] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [458] L809-1-->L810: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet36=|v_ULTIMATE.start_main_#t~nondet36_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet36] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [408] L810-->L810-1: Formula: (and (= (store |v_#valid_14| |v_ULTIMATE.start_main_~#t898~0.base_5| 1) |v_#valid_13|) (not (= 0 |v_ULTIMATE.start_main_~#t898~0.base_5|)) (= |v_ULTIMATE.start_main_~#t898~0.offset_5| 0) (= (select |v_#valid_14| |v_ULTIMATE.start_main_~#t898~0.base_5|) 0) (= (store |v_#length_6| |v_ULTIMATE.start_main_~#t898~0.base_5| 4) |v_#length_5|)) InVars {#length=|v_#length_6|, #valid=|v_#valid_14|} OutVars{ULTIMATE.start_main_~#t898~0.base=|v_ULTIMATE.start_main_~#t898~0.base_5|, #length=|v_#length_5|, ULTIMATE.start_main_~#t898~0.offset=|v_ULTIMATE.start_main_~#t898~0.offset_5|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t898~0.base, ULTIMATE.start_main_~#t898~0.offset, #valid, #length] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [385] L810-1-->L811: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t898~0.base_1| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t898~0.base_1|) |v_ULTIMATE.start_main_~#t898~0.offset_1| 2))) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t898~0.base=|v_ULTIMATE.start_main_~#t898~0.base_1|, ULTIMATE.start_main_~#t898~0.offset=|v_ULTIMATE.start_main_~#t898~0.offset_1|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t898~0.base=|v_ULTIMATE.start_main_~#t898~0.base_1|, ULTIMATE.start_main_~#t898~0.offset=|v_ULTIMATE.start_main_~#t898~0.offset_1|} AuxVars[] AssignedVars[#memory_int] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [602] L811-->P2ENTRY: Formula: (and (= |v_Thread0_P2_#in~arg.offset_3| 0) (= 0 |v_Thread0_P2_#in~arg.base_3|) (= 2 v_Thread0_P2_thidvar0_2)) InVars {} OutVars{Thread0_P2_#in~arg.base=|v_Thread0_P2_#in~arg.base_3|, Thread0_P2_thidvar0=v_Thread0_P2_thidvar0_2, Thread0_P2_#in~arg.offset=|v_Thread0_P2_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P2_#in~arg.base, Thread0_P2_thidvar0, Thread0_P2_#in~arg.offset] VAL [Thread0_P2_thidvar0=2, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [575] P2ENTRY-->L4: Formula: (and (= v_Thread0_P2_~arg.offset_1 |v_Thread0_P2_#in~arg.offset_1|) (= |v_Thread0_P2___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= (mod v_~z$w_buff1_used~0_21 256) 0)) (not (= (mod v_~z$w_buff0_used~0_36 256) 0)))) 1 0)) (= v_Thread0_P2___VERIFIER_assert_~expression_1 |v_Thread0_P2___VERIFIER_assert_#in~expression_1|) (= v_~z$w_buff0_used~0_36 1) (= v_Thread0_P2_~arg.base_1 |v_Thread0_P2_#in~arg.base_1|) (= v_~z$w_buff0~0_7 1) (= v_~z$w_buff1_used~0_21 v_~z$w_buff0_used~0_37) (= v_~z$w_buff1~0_7 v_~z$w_buff0~0_8)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_37, ~z$w_buff0~0=v_~z$w_buff0~0_8, Thread0_P2_#in~arg.offset=|v_Thread0_P2_#in~arg.offset_1|, Thread0_P2_#in~arg.base=|v_Thread0_P2_#in~arg.base_1|} OutVars{Thread0_P2_~arg.offset=v_Thread0_P2_~arg.offset_1, Thread0_P2_~arg.base=v_Thread0_P2_~arg.base_1, Thread0_P2___VERIFIER_assert_~expression=v_Thread0_P2___VERIFIER_assert_~expression_1, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_36, ~z$w_buff0~0=v_~z$w_buff0~0_7, Thread0_P2___VERIFIER_assert_#in~expression=|v_Thread0_P2___VERIFIER_assert_#in~expression_1|, Thread0_P2_#in~arg.base=|v_Thread0_P2_#in~arg.base_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_21, ~z$w_buff1~0=v_~z$w_buff1~0_7, Thread0_P2_#in~arg.offset=|v_Thread0_P2_#in~arg.offset_1|} AuxVars[] AssignedVars[Thread0_P2_~arg.offset, Thread0_P2_~arg.base, Thread0_P2___VERIFIER_assert_~expression, ~z$w_buff0_used~0, ~z$w_buff0~0, Thread0_P2___VERIFIER_assert_#in~expression, ~z$w_buff1_used~0, ~z$w_buff1~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [577] L4-->L4-3: Formula: (not (= 0 v_Thread0_P2___VERIFIER_assert_~expression_3)) InVars {Thread0_P2___VERIFIER_assert_~expression=v_Thread0_P2___VERIFIER_assert_~expression_3} OutVars{Thread0_P2___VERIFIER_assert_~expression=v_Thread0_P2___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [580] L4-3-->L784: Formula: (and (= v_~z$r_buff1_thd2~0_17 v_~z$r_buff0_thd2~0_31) (= v_~a~0_1 1) (= v_~__unbuffered_p2_EAX~0_1 v_~a~0_1) (= v_~__unbuffered_p2_EBX~0_1 v_~b~0_2) (= v_~z$r_buff1_thd1~0_1 v_~z$r_buff0_thd1~0_1) (= v_~z$r_buff0_thd3~0_7 1) (= v_~z$r_buff1_thd0~0_1 v_~z$r_buff0_thd0~0_1) (= v_~z$r_buff1_thd3~0_5 v_~z$r_buff0_thd3~0_8)) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_8, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_1, ~b~0=v_~b~0_2, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_31} OutVars{~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_1, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_5, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_17, ~a~0=v_~a~0_1, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~b~0=v_~b~0_2, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_1, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_1, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_7, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_1, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_1, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_31} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p2_EBX~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~z$r_buff0_thd3~0, ~__unbuffered_p2_EAX~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [581] L784-->L784-5: Formula: (and (= |v_Thread0_P2_#t~ite29_1| v_~z$w_buff0~0_9) (not (= (mod v_~z$w_buff0_used~0_38 256) 0)) (not (= 0 (mod v_~z$r_buff0_thd3~0_9 256)))) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_9, ~z$w_buff0~0=v_~z$w_buff0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_38} OutVars{Thread0_P2_#t~ite29=|v_Thread0_P2_#t~ite29_1|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_9, ~z$w_buff0~0=v_~z$w_buff0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_38} AuxVars[] AssignedVars[Thread0_P2_#t~ite29] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [504] P0ENTRY-->L724: Formula: (and (= v_Thread1_P0_~arg.base_1 |v_Thread1_P0_#in~arg.base_1|) (= v_Thread1_P0_~arg.offset_1 |v_Thread1_P0_#in~arg.offset_1|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1)) (= v_~b~0_1 1) (= v_~x~0_1 1)) InVars {Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, Thread1_P0_~arg.offset=v_Thread1_P0_~arg.offset_1, ~b~0=v_~b~0_1, Thread1_P0_~arg.base=v_Thread1_P0_~arg.base_1, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x~0=v_~x~0_1} AuxVars[] AssignedVars[Thread1_P0_~arg.offset, ~b~0, Thread1_P0_~arg.base, ~__unbuffered_cnt~0, ~x~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [508] P1ENTRY-->L742: Formula: (and (= v_Thread2_P1_~arg.offset_1 |v_Thread2_P1_#in~arg.offset_1|) (= v_~z$mem_tmp~0_1 v_~z~0_1) (= v_~weak$$choice2~0_2 (ite (= (+ |v_Thread2_P1_#t~nondet5.base_1| |v_Thread2_P1_#t~nondet5.offset_1|) 0) 0 1)) (= v_Thread2_P1_~arg.base_1 |v_Thread2_P1_#in~arg.base_1|) (= v_~x~0_2 2) (= v_~weak$$choice0~0_1 (ite (= (+ |v_Thread2_P1_#t~nondet4.base_1| |v_Thread2_P1_#t~nondet4.offset_1|) 0) 0 1)) (= v_~z$flush_delayed~0_1 v_~weak$$choice2~0_2) (= v_~__unbuffered_p1_EAX~0_1 v_~y~0_1) (= v_~y~0_1 1)) InVars {Thread2_P1_#in~arg.base=|v_Thread2_P1_#in~arg.base_1|, Thread2_P1_#t~nondet5.base=|v_Thread2_P1_#t~nondet5.base_1|, Thread2_P1_#t~nondet5.offset=|v_Thread2_P1_#t~nondet5.offset_1|, Thread2_P1_#t~nondet4.base=|v_Thread2_P1_#t~nondet4.base_1|, ~z~0=v_~z~0_1, Thread2_P1_#t~nondet4.offset=|v_Thread2_P1_#t~nondet4.offset_1|, Thread2_P1_#in~arg.offset=|v_Thread2_P1_#in~arg.offset_1|} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_1, Thread2_P1_#in~arg.base=|v_Thread2_P1_#in~arg.base_1|, Thread2_P1_~arg.offset=v_Thread2_P1_~arg.offset_1, Thread2_P1_#t~nondet5.base=|v_Thread2_P1_#t~nondet5.base_2|, ~z$flush_delayed~0=v_~z$flush_delayed~0_1, Thread2_P1_#t~nondet4.offset=|v_Thread2_P1_#t~nondet4.offset_2|, Thread2_P1_#in~arg.offset=|v_Thread2_P1_#in~arg.offset_1|, ~weak$$choice0~0=v_~weak$$choice0~0_1, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, Thread2_P1_~arg.base=v_Thread2_P1_~arg.base_1, Thread2_P1_#t~nondet5.offset=|v_Thread2_P1_#t~nondet5.offset_2|, Thread2_P1_#t~nondet4.base=|v_Thread2_P1_#t~nondet4.base_2|, ~z~0=v_~z~0_1, ~weak$$choice2~0=v_~weak$$choice2~0_2, ~y~0=v_~y~0_1, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[~z$mem_tmp~0, Thread2_P1_~arg.offset, Thread2_P1_#t~nondet5.base, ~z$flush_delayed~0, Thread2_P1_#t~nondet4.offset, ~weak$$choice0~0, ~__unbuffered_p1_EAX~0, Thread2_P1_~arg.base, Thread2_P1_#t~nondet5.offset, Thread2_P1_#t~nondet4.base, ~weak$$choice2~0, ~y~0, ~x~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [509] L742-->L742-5: Formula: (and (let ((.cse0 (= (mod v_~z$r_buff0_thd2~0_3 256) 0))) (or (and .cse0 (= 0 (mod v_~z$r_buff1_thd2~0_3 256))) (= (mod v_~z$w_buff0_used~0_3 256) 0) (and (= 0 (mod v_~z$w_buff1_used~0_3 256)) .cse0))) (= |v_Thread2_P1_#t~ite7_1| v_~z~0_2)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_3, ~z~0=v_~z~0_2, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_3, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_3, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_3} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_3, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_3, Thread2_P1_#t~ite7=|v_Thread2_P1_#t~ite7_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_3, ~z~0=v_~z~0_2, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_3} AuxVars[] AssignedVars[Thread2_P1_#t~ite7] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [583] L784-5-->L785: Formula: (= v_~z~0_8 |v_Thread0_P2_#t~ite29_2|) InVars {Thread0_P2_#t~ite29=|v_Thread0_P2_#t~ite29_2|} OutVars{Thread0_P2_#t~ite29=|v_Thread0_P2_#t~ite29_3|, Thread0_P2_#t~ite28=|v_Thread0_P2_#t~ite28_1|, ~z~0=v_~z~0_8} AuxVars[] AssignedVars[Thread0_P2_#t~ite29, Thread0_P2_#t~ite28, ~z~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [586] L785-->L785-2: Formula: (and (not (= 0 (mod v_~z$w_buff0_used~0_40 256))) (= |v_Thread0_P2_#t~ite30_1| 0) (not (= 0 (mod v_~z$r_buff0_thd3~0_11 256)))) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_40, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_11} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_11, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_40, Thread0_P2_#t~ite30=|v_Thread0_P2_#t~ite30_1|} AuxVars[] AssignedVars[Thread0_P2_#t~ite30] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite30|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [589] L785-2-->L786: Formula: (= v_~z$w_buff0_used~0_42 |v_Thread0_P2_#t~ite30_3|) InVars {Thread0_P2_#t~ite30=|v_Thread0_P2_#t~ite30_3|} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_42, Thread0_P2_#t~ite30=|v_Thread0_P2_#t~ite30_4|} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread0_P2_#t~ite30] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [591] L786-->L786-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd3~0_1 256)) (= 0 (mod v_~z$w_buff0_used~0_31 256))) (or (= (mod v_~z$w_buff1_used~0_17 256) 0) (= 0 (mod v_~z$r_buff1_thd3~0_1 256))) (= |v_Thread0_P2_#t~ite31_2| v_~z$w_buff1_used~0_17)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_1, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_31, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_1} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_1, Thread0_P2_#t~ite31=|v_Thread0_P2_#t~ite31_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_31, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_1} AuxVars[] AssignedVars[Thread0_P2_#t~ite31] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite31|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [592] L786-2-->L787: Formula: (= v_~z$w_buff1_used~0_18 |v_Thread0_P2_#t~ite31_3|) InVars {Thread0_P2_#t~ite31=|v_Thread0_P2_#t~ite31_3|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_18, Thread0_P2_#t~ite31=|v_Thread0_P2_#t~ite31_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread0_P2_#t~ite31] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [594] L787-->L787-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd3~0_3 256)) (= (mod v_~z$w_buff0_used~0_33 256) 0)) (= |v_Thread0_P2_#t~ite32_2| v_~z$r_buff0_thd3~0_3)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_33, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_3} OutVars{Thread0_P2_#t~ite32=|v_Thread0_P2_#t~ite32_2|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_3, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_33} AuxVars[] AssignedVars[Thread0_P2_#t~ite32] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite32|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [595] L787-2-->L788: Formula: (= v_~z$r_buff0_thd3~0_4 |v_Thread0_P2_#t~ite32_3|) InVars {Thread0_P2_#t~ite32=|v_Thread0_P2_#t~ite32_3|} OutVars{Thread0_P2_#t~ite32=|v_Thread0_P2_#t~ite32_4|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_4} AuxVars[] AssignedVars[Thread0_P2_#t~ite32, ~z$r_buff0_thd3~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [597] L788-->L788-2: Formula: (and (= |v_Thread0_P2_#t~ite33_2| v_~z$r_buff1_thd3~0_3) (or (= 0 (mod v_~z$r_buff0_thd3~0_6 256)) (= (mod v_~z$w_buff0_used~0_35 256) 0)) (or (= (mod v_~z$r_buff1_thd3~0_3 256) 0) (= (mod v_~z$w_buff1_used~0_20 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_20, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_6, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_35, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_3} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_20, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_6, Thread0_P2_#t~ite33=|v_Thread0_P2_#t~ite33_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_35, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_3} AuxVars[] AssignedVars[Thread0_P2_#t~ite33] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite33|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [598] L788-2-->L793: Formula: (and (= v_~z$r_buff1_thd3~0_4 |v_Thread0_P2_#t~ite33_3|) (= v_~__unbuffered_cnt~0_5 (+ v_~__unbuffered_cnt~0_6 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6, Thread0_P2_#t~ite33=|v_Thread0_P2_#t~ite33_3|} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, Thread0_P2_#t~ite33=|v_Thread0_P2_#t~ite33_4|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_4} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, Thread0_P2_#t~ite33] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 [511] L742-5-->L743: Formula: (= v_~z~0_4 |v_Thread2_P1_#t~ite7_2|) InVars {Thread2_P1_#t~ite7=|v_Thread2_P1_#t~ite7_2|} OutVars{Thread2_P1_#t~ite7=|v_Thread2_P1_#t~ite7_3|, ~z~0=v_~z~0_4, Thread2_P1_#t~ite6=|v_Thread2_P1_#t~ite6_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite7, ~z~0, Thread2_P1_#t~ite6] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [514] L743-->L743-8: Formula: (and (= |v_Thread2_P1_#t~ite10_1| v_~z$w_buff0~0_2) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_2} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_2, Thread2_P1_#t~ite10=|v_Thread2_P1_#t~ite10_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite10] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite10|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [517] L743-8-->L744: Formula: (= v_~z$w_buff0~0_6 |v_Thread2_P1_#t~ite10_2|) InVars {Thread2_P1_#t~ite10=|v_Thread2_P1_#t~ite10_2|} OutVars{Thread2_P1_#t~ite8=|v_Thread2_P1_#t~ite8_1|, Thread2_P1_#t~ite9=|v_Thread2_P1_#t~ite9_1|, ~z$w_buff0~0=v_~z$w_buff0~0_6, Thread2_P1_#t~ite10=|v_Thread2_P1_#t~ite10_3|} AuxVars[] AssignedVars[~z$w_buff0~0, Thread2_P1_#t~ite10, Thread2_P1_#t~ite8, Thread2_P1_#t~ite9] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [520] L744-->L744-8: Formula: (and (= |v_Thread2_P1_#t~ite13_1| v_~z$w_buff1~0_2) (not (= 0 (mod v_~weak$$choice2~0_5 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~z$w_buff1~0=v_~z$w_buff1~0_2} OutVars{Thread2_P1_#t~ite13=|v_Thread2_P1_#t~ite13_1|, ~z$w_buff1~0=v_~z$w_buff1~0_2, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[Thread2_P1_#t~ite13] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite13|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [525] L744-8-->L745: Formula: (= v_~z$w_buff1~0_6 |v_Thread2_P1_#t~ite13_2|) InVars {Thread2_P1_#t~ite13=|v_Thread2_P1_#t~ite13_2|} OutVars{Thread2_P1_#t~ite13=|v_Thread2_P1_#t~ite13_3|, Thread2_P1_#t~ite12=|v_Thread2_P1_#t~ite12_1|, ~z$w_buff1~0=v_~z$w_buff1~0_6, Thread2_P1_#t~ite11=|v_Thread2_P1_#t~ite11_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite11, Thread2_P1_#t~ite13, Thread2_P1_#t~ite12, ~z$w_buff1~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [529] L745-->L745-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_7 256))) (= |v_Thread2_P1_#t~ite16_1| v_~z$w_buff0_used~0_17)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_17} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_17, Thread2_P1_#t~ite16=|v_Thread2_P1_#t~ite16_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite16] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite16|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [534] L745-8-->L746: Formula: (= v_~z$w_buff0_used~0_22 |v_Thread2_P1_#t~ite16_2|) InVars {Thread2_P1_#t~ite16=|v_Thread2_P1_#t~ite16_2|} OutVars{Thread2_P1_#t~ite15=|v_Thread2_P1_#t~ite15_1|, Thread2_P1_#t~ite14=|v_Thread2_P1_#t~ite14_1|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_22, Thread2_P1_#t~ite16=|v_Thread2_P1_#t~ite16_3|} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread2_P1_#t~ite15, Thread2_P1_#t~ite14, Thread2_P1_#t~ite16] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [538] L746-->L746-8: Formula: (and (= |v_Thread2_P1_#t~ite19_1| v_~z$w_buff1_used~0_11) (not (= (mod v_~weak$$choice2~0_9 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_11, ~weak$$choice2~0=v_~weak$$choice2~0_9} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_11, ~weak$$choice2~0=v_~weak$$choice2~0_9, Thread2_P1_#t~ite19=|v_Thread2_P1_#t~ite19_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite19] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite19|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [543] L746-8-->L747: Formula: (= v_~z$w_buff1_used~0_14 |v_Thread2_P1_#t~ite19_2|) InVars {Thread2_P1_#t~ite19=|v_Thread2_P1_#t~ite19_2|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_14, Thread2_P1_#t~ite17=|v_Thread2_P1_#t~ite17_1|, Thread2_P1_#t~ite19=|v_Thread2_P1_#t~ite19_3|, Thread2_P1_#t~ite18=|v_Thread2_P1_#t~ite18_1|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread2_P1_#t~ite17, Thread2_P1_#t~ite19, Thread2_P1_#t~ite18] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [547] L747-->L747-8: Formula: (and (not (= (mod v_~weak$$choice2~0_11 256) 0)) (= |v_Thread2_P1_#t~ite22_1| v_~z$r_buff0_thd2~0_25)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_11, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_11, Thread2_P1_#t~ite22=|v_Thread2_P1_#t~ite22_1|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} AuxVars[] AssignedVars[Thread2_P1_#t~ite22] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite22|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [552] L747-8-->L748: Formula: (= v_~z$r_buff0_thd2~0_30 |v_Thread2_P1_#t~ite22_2|) InVars {Thread2_P1_#t~ite22=|v_Thread2_P1_#t~ite22_2|} OutVars{Thread2_P1_#t~ite21=|v_Thread2_P1_#t~ite21_1|, Thread2_P1_#t~ite22=|v_Thread2_P1_#t~ite22_3|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_30, Thread2_P1_#t~ite20=|v_Thread2_P1_#t~ite20_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite21, Thread2_P1_#t~ite22, Thread2_P1_#t~ite20, ~z$r_buff0_thd2~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [556] L748-->L748-8: Formula: (and (not (= (mod v_~weak$$choice2~0_13 256) 0)) (= |v_Thread2_P1_#t~ite25_1| v_~z$r_buff1_thd2~0_16)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_13, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_16} OutVars{Thread2_P1_#t~ite25=|v_Thread2_P1_#t~ite25_1|, ~weak$$choice2~0=v_~weak$$choice2~0_13, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_16} AuxVars[] AssignedVars[Thread2_P1_#t~ite25] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite25|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [561] L748-8-->L750: Formula: (and (= v_~__unbuffered_p1_EBX~0_1 v_~z~0_3) (= v_~z$r_buff1_thd2~0_5 |v_Thread2_P1_#t~ite25_2|)) InVars {Thread2_P1_#t~ite25=|v_Thread2_P1_#t~ite25_2|, ~z~0=v_~z~0_3} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_1, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_5, Thread2_P1_#t~ite25=|v_Thread2_P1_#t~ite25_3|, Thread2_P1_#t~ite23=|v_Thread2_P1_#t~ite23_1|, Thread2_P1_#t~ite24=|v_Thread2_P1_#t~ite24_1|, ~z~0=v_~z~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0, ~z$r_buff1_thd2~0, Thread2_P1_#t~ite25, Thread2_P1_#t~ite23, Thread2_P1_#t~ite24] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [565] L750-->L750-2: Formula: (and (not (= (mod v_~z$flush_delayed~0_2 256) 0)) (= |v_Thread2_P1_#t~ite26_1| v_~z$mem_tmp~0_2)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_2, ~z$flush_delayed~0=v_~z$flush_delayed~0_2} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_2, Thread2_P1_#t~ite26=|v_Thread2_P1_#t~ite26_1|, ~z$flush_delayed~0=v_~z$flush_delayed~0_2} AuxVars[] AssignedVars[Thread2_P1_#t~ite26] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite26|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [570] L750-2-->L758: Formula: (and (= v_~z~0_6 |v_Thread2_P1_#t~ite26_3|) (= v_~z$flush_delayed~0_4 0) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {Thread2_P1_#t~ite26=|v_Thread2_P1_#t~ite26_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4} OutVars{Thread2_P1_#t~ite26=|v_Thread2_P1_#t~ite26_4|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, ~z$flush_delayed~0=v_~z$flush_delayed~0_4, ~z~0=v_~z~0_6} AuxVars[] AssignedVars[Thread2_P1_#t~ite26, ~__unbuffered_cnt~0, ~z$flush_delayed~0, ~z~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [336] L811-1-->L815: Formula: (= v_~main$tmp_guard0~0_1 (ite (= (ite (= v_~__unbuffered_cnt~0_7 3) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_7} OutVars{ULTIMATE.start_main_#t~nondet37=|v_ULTIMATE.start_main_#t~nondet37_1|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_7, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet37, ~main$tmp_guard0~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [444] L815-->L817: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_2 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [479] L817-->L817-2: Formula: (or (= 0 (mod v_~z$w_buff0_used~0_45 256)) (= (mod v_~z$r_buff0_thd0~0_3 256) 0)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_45, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_3} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_45, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [485] L817-2-->L817-4: Formula: (and (or (= 0 (mod v_~z$w_buff1_used~0_26 256)) (= (mod v_~z$r_buff1_thd0~0_3 256) 0)) (= |v_ULTIMATE.start_main_#t~ite38_2| v_~z~0_9)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_26, ~z~0=v_~z~0_9, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_3} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_26, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_2|, ~z~0=v_~z~0_9, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite38] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [475] L817-4-->L817-5: Formula: (= |v_ULTIMATE.start_main_#t~ite39_2| |v_ULTIMATE.start_main_#t~ite38_3|) InVars {ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_3|} OutVars{ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_2|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_#t~ite39|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [477] L817-5-->L818: Formula: (= v_~z~0_10 |v_ULTIMATE.start_main_#t~ite39_4|) InVars {ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_4|} OutVars{ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_4|, ~z~0=v_~z~0_10, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38, ~z~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [412] L818-->L818-2: Formula: (and (or (= (mod v_~z$r_buff0_thd0~0_5 256) 0) (= (mod v_~z$w_buff0_used~0_47 256) 0)) (= |v_ULTIMATE.start_main_#t~ite40_2| v_~z$w_buff0_used~0_47)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_47, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_5} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_5, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_47} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [419] L818-2-->L819: Formula: (= v_~z$w_buff0_used~0_48 |v_ULTIMATE.start_main_#t~ite40_4|) InVars {ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_4|} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_48, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ~z$w_buff0_used~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [341] L819-->L819-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite41_2| v_~z$w_buff1_used~0_28) (or (= 0 (mod v_~z$w_buff0_used~0_50 256)) (= 0 (mod v_~z$r_buff0_thd0~0_7 256))) (or (= (mod v_~z$r_buff1_thd0~0_5 256) 0) (= (mod v_~z$w_buff1_used~0_28 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_28, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_50, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_5} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_28, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_2|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_50, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_5} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite41|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [345] L819-2-->L820: Formula: (= v_~z$w_buff1_used~0_29 |v_ULTIMATE.start_main_#t~ite41_4|) InVars {ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_4|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_29, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$w_buff1_used~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [453] L820-->L820-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite42_2| v_~z$r_buff0_thd0~0_9) (or (= 0 (mod v_~z$r_buff0_thd0~0_9 256)) (= 0 (mod v_~z$w_buff0_used~0_52 256)))) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_52, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_9} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_52, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [459] L820-2-->L821: Formula: (= v_~z$r_buff0_thd0~0_10 |v_ULTIMATE.start_main_#t~ite42_4|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} OutVars{ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_3|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_10} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [407] L821-->L821-2: Formula: (and (or (= (mod v_~z$r_buff0_thd0~0_12 256) 0) (= 0 (mod v_~z$w_buff0_used~0_54 256))) (or (= (mod v_~z$r_buff1_thd0~0_7 256) 0) (= (mod v_~z$w_buff1_used~0_31 256) 0)) (= |v_ULTIMATE.start_main_#t~ite43_2| v_~z$r_buff1_thd0~0_7)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_31, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_12, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_54, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_7} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_31, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_12, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_54, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [388] L821-2-->L826: Formula: (and (= v_~z$r_buff1_thd0~0_8 |v_ULTIMATE.start_main_#t~ite43_4|) (= v_~main$tmp_guard1~0_1 (ite (= (ite (not (and (= 2 v_~x~0_3) (= v_~__unbuffered_p2_EBX~0_2 0) (= 0 v_~__unbuffered_p1_EBX~0_2) (= 1 v_~__unbuffered_p1_EAX~0_2) (= v_~__unbuffered_p2_EAX~0_2 1))) 1 0) 0) 0 1))) InVars {~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_2, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|, ~x~0=v_~x~0_3} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_8, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_1, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_2, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ~x~0=v_~x~0_3} AuxVars[] AssignedVars[~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite43] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [443] L826-->L826-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_2 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [421] L826-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [379] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [375] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [371] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 ~b~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t896~0.base, main_~#t896~0.offset, main_~#t897~0.base, main_~#t897~0.offset, main_~#t898~0.base, main_~#t898~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t896~0.base, main_~#t896~0.offset := #Ultimate.alloc(4); srcloc: L806 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t896~0.base, main_~#t896~0.offset, 4); srcloc: L806-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t897~0.base, main_~#t897~0.offset := #Ultimate.alloc(4); srcloc: L808 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t897~0.base, main_~#t897~0.offset, 4); srcloc: L808-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet36; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t898~0.base, main_~#t898~0.offset := #Ultimate.alloc(4); srcloc: L810 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(2, main_~#t898~0.base, main_~#t898~0.offset, 4); srcloc: L810-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 2 P2(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0;~z$r_buff0_thd3~0 := 1;~a~0 := 1;~__unbuffered_p2_EAX~0 := ~a~0;~__unbuffered_p2_EBX~0 := ~b~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite29 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~b~0 := 1;~x~0 := 1;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x~0 := 2;~y~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1);havoc #t~nondet4.base, #t~nondet4.offset;~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1);havoc #t~nondet5.base, #t~nondet5.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite7 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite29;havoc #t~ite29;havoc #t~ite28; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite30 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite30;havoc #t~ite30; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite31 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite31|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite31;havoc #t~ite31; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256);#t~ite32 := ~z$r_buff0_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite32|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd3~0 := #t~ite32;havoc #t~ite32; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite33 := ~z$r_buff1_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite33|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd3~0 := #t~ite33;havoc #t~ite33;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 ~z~0 := #t~ite7;havoc #t~ite7;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite10 := ~z$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite10|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0~0 := #t~ite10;havoc #t~ite9;havoc #t~ite10;havoc #t~ite8; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite13 := ~z$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12;havoc #t~ite11; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0_used~0 := #t~ite16;havoc #t~ite14;havoc #t~ite15;havoc #t~ite16; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1_used~0 := #t~ite19;havoc #t~ite19;havoc #t~ite18;havoc #t~ite17; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff0_thd2~0 := #t~ite22;havoc #t~ite22;havoc #t~ite21;havoc #t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff1_thd2~0 := #t~ite25;havoc #t~ite24;havoc #t~ite25;havoc #t~ite23;~__unbuffered_p1_EBX~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~z$flush_delayed~0 % 256;#t~ite26 := ~z$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z~0 := #t~ite26;havoc #t~ite26;~z$flush_delayed~0 := 0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet37;~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite38 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite39 := main_#t~ite38; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_#t~ite39|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite39;havoc main_#t~ite38;havoc main_#t~ite39; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite40 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite40;havoc main_#t~ite40; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite41 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite41|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite41;havoc main_#t~ite41; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite42;havoc main_#t~ite42; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite43;havoc main_#t~ite43;~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 ~b~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t896~0.base, main_~#t896~0.offset, main_~#t897~0.base, main_~#t897~0.offset, main_~#t898~0.base, main_~#t898~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t896~0.base, main_~#t896~0.offset := #Ultimate.alloc(4); srcloc: L806 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t896~0.base, main_~#t896~0.offset, 4); srcloc: L806-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t897~0.base, main_~#t897~0.offset := #Ultimate.alloc(4); srcloc: L808 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t897~0.base, main_~#t897~0.offset, 4); srcloc: L808-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet36; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t898~0.base, main_~#t898~0.offset := #Ultimate.alloc(4); srcloc: L810 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(2, main_~#t898~0.base, main_~#t898~0.offset, 4); srcloc: L810-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 2 P2(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0;~z$r_buff0_thd3~0 := 1;~a~0 := 1;~__unbuffered_p2_EAX~0 := ~a~0;~__unbuffered_p2_EBX~0 := ~b~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite29 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~b~0 := 1;~x~0 := 1;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x~0 := 2;~y~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1);havoc #t~nondet4.base, #t~nondet4.offset;~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1);havoc #t~nondet5.base, #t~nondet5.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite7 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite29;havoc #t~ite29;havoc #t~ite28; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite30 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite30;havoc #t~ite30; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite31 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite31|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite31;havoc #t~ite31; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256);#t~ite32 := ~z$r_buff0_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite32|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd3~0 := #t~ite32;havoc #t~ite32; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite33 := ~z$r_buff1_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite33|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd3~0 := #t~ite33;havoc #t~ite33;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 ~z~0 := #t~ite7;havoc #t~ite7;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite10 := ~z$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite10|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0~0 := #t~ite10;havoc #t~ite9;havoc #t~ite10;havoc #t~ite8; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite13 := ~z$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12;havoc #t~ite11; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0_used~0 := #t~ite16;havoc #t~ite14;havoc #t~ite15;havoc #t~ite16; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1_used~0 := #t~ite19;havoc #t~ite19;havoc #t~ite18;havoc #t~ite17; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff0_thd2~0 := #t~ite22;havoc #t~ite22;havoc #t~ite21;havoc #t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff1_thd2~0 := #t~ite25;havoc #t~ite24;havoc #t~ite25;havoc #t~ite23;~__unbuffered_p1_EBX~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~z$flush_delayed~0 % 256;#t~ite26 := ~z$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z~0 := #t~ite26;havoc #t~ite26;~z$flush_delayed~0 := 0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet37;~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite38 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite39 := main_#t~ite38; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_#t~ite39|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite39;havoc main_#t~ite38;havoc main_#t~ite39; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite40 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite40;havoc main_#t~ite40; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite41 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite41|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite41;havoc main_#t~ite41; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite42;havoc main_#t~ite42; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite43;havoc main_#t~ite43;~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t896~0.base|=6, |ULTIMATE.start_main_~#t896~0.offset|=0, |ULTIMATE.start_main_~#t897~0.base|=7, |ULTIMATE.start_main_~#t897~0.offset|=0, |ULTIMATE.start_main_~#t898~0.base|=5, |ULTIMATE.start_main_~#t898~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t896~0.base, main_~#t896~0.offset, main_~#t897~0.base, main_~#t897~0.offset, main_~#t898~0.base, main_~#t898~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] -1 call main_~#t896~0.base, main_~#t896~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 call write~int(0, main_~#t896~0.base, main_~#t896~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] -1 call main_~#t897~0.base, main_~#t897~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 call write~int(1, main_~#t897~0.base, main_~#t897~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] -1 call main_~#t898~0.base, main_~#t898~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 call write~int(2, main_~#t898~0.base, main_~#t898~0.offset, 4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1); [L738] 2 havoc #t~nondet4.base, #t~nondet4.offset; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1); [L739] 2 havoc #t~nondet5.base, #t~nondet5.offset; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L785] 0 #t~ite30 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256); [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 assume 0 != ~weak$$choice2~0 % 256; [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 assume 0 != ~weak$$choice2~0 % 256; [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 assume 0 != ~weak$$choice2~0 % 256; [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 assume 0 != ~weak$$choice2~0 % 256; [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 assume 0 != ~weak$$choice2~0 % 256; [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 assume 0 != ~weak$$choice2~0 % 256; [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 assume 0 != ~z$flush_delayed~0 % 256; [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t896~0.base, main_~#t896~0.offset, main_~#t897~0.base, main_~#t897~0.offset, main_~#t898~0.base, main_~#t898~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] -1 call main_~#t896~0.base, main_~#t896~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 call write~int(0, main_~#t896~0.base, main_~#t896~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] -1 call main_~#t897~0.base, main_~#t897~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 call write~int(1, main_~#t897~0.base, main_~#t897~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] -1 call main_~#t898~0.base, main_~#t898~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 call write~int(2, main_~#t898~0.base, main_~#t898~0.offset, 4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1); [L738] 2 havoc #t~nondet4.base, #t~nondet4.offset; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1); [L739] 2 havoc #t~nondet5.base, #t~nondet5.offset; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L785] 0 #t~ite30 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256); [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 assume 0 != ~weak$$choice2~0 % 256; [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 assume 0 != ~weak$$choice2~0 % 256; [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 assume 0 != ~weak$$choice2~0 % 256; [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 assume 0 != ~weak$$choice2~0 % 256; [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 assume 0 != ~weak$$choice2~0 % 256; [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 assume 0 != ~weak$$choice2~0 % 256; [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 assume 0 != ~z$flush_delayed~0 % 256; [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0.base=6, main_~#t896~0.offset=0, main_~#t897~0.base=7, main_~#t897~0.offset=0, main_~#t898~0.base=5, main_~#t898~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t896~0, main_~#t897~0, main_~#t898~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call main_~#t896~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, main_~#t896~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call main_~#t897~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, main_~#t897~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call main_~#t898~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, main_~#t898~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t896~0, main_~#t897~0, main_~#t898~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call main_~#t896~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, main_~#t896~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call main_~#t897~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, main_~#t897~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call main_~#t898~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, main_~#t898~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t896~0!base=6, main_~#t896~0!offset=0, main_~#t897~0!base=7, main_~#t897~0!offset=0, main_~#t898~0!base=5, main_~#t898~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call ~#t896~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, ~#t896~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call ~#t897~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, ~#t897~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc #t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call ~#t898~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, ~#t898~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc #t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 #t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 #t~ite39 := #t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := #t~ite39; [L817] -1 havoc #t~ite38; [L817] -1 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := #t~ite40; [L818] -1 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 #t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := #t~ite41; [L819] -1 havoc #t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 #t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := #t~ite42; [L820] -1 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 #t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := #t~ite43; [L821] -1 havoc #t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call ~#t896~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, ~#t896~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call ~#t897~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, ~#t897~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc #t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call ~#t898~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, ~#t898~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc #t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 #t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 #t~ite39 := #t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := #t~ite39; [L817] -1 havoc #t~ite38; [L817] -1 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := #t~ite40; [L818] -1 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 #t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := #t~ite41; [L819] -1 havoc #t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 #t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := #t~ite42; [L820] -1 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 #t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := #t~ite43; [L821] -1 havoc #t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L672] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L674] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L676] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L678] -1 int __unbuffered_p2_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0] [L680] -1 int __unbuffered_p2_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0] [L682] -1 int a = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0] [L684] -1 int b = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0] [L685] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0] [L686] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0] [L688] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L690] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L692] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L693] -1 _Bool z$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0] [L694] -1 int z$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0] [L695] -1 _Bool z$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0] [L696] -1 _Bool z$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0] [L697] -1 _Bool z$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0] [L698] -1 _Bool z$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0] [L699] -1 _Bool z$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0] [L700] -1 _Bool z$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0] [L701] -1 _Bool z$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0] [L702] -1 _Bool z$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0] [L703] -1 _Bool z$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0] [L704] -1 int *z$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}] [L705] -1 int z$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0] [L706] -1 _Bool z$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0] [L707] -1 int z$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0] [L708] -1 _Bool z$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L709] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L710] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L806] -1 pthread_t t896; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L807] FCALL, FORK -1 pthread_create(&t896, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L808] -1 pthread_t t897; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L809] FCALL, FORK -1 pthread_create(&t897, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L810] -1 pthread_t t898; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L811] FCALL, FORK -1 pthread_create(&t898, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L763] 0 z$w_buff1 = z$w_buff0 [L764] 0 z$w_buff0 = 1 [L765] 0 z$w_buff1_used = z$w_buff0_used [L766] 0 z$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] 0 z$r_buff1_thd0 = z$r_buff0_thd0 [L769] 0 z$r_buff1_thd1 = z$r_buff0_thd1 [L770] 0 z$r_buff1_thd2 = z$r_buff0_thd2 [L771] 0 z$r_buff1_thd3 = z$r_buff0_thd3 [L772] 0 z$r_buff0_thd3 = (_Bool)1 [L775] 0 a = 1 [L778] 0 __unbuffered_p2_EAX = a [L781] 0 __unbuffered_p2_EBX = b VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L714] 1 b = 1 [L717] 1 x = 1 [L722] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L729] 2 x = 2 [L732] 2 y = 1 [L735] 2 __unbuffered_p1_EAX = y [L738] 2 weak$$choice0 = __VERIFIER_nondet_pointer() [L739] 2 weak$$choice2 = __VERIFIER_nondet_pointer() [L740] 2 z$flush_delayed = weak$$choice2 [L741] 2 z$mem_tmp = z VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] EXPR 2 !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] 0 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L785] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L785] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L786] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L786] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L787] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L787] 0 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L788] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L788] 0 z$r_buff1_thd3 = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 [L791] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L742] 2 z = !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) [L743] EXPR 2 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0))=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L743] 2 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) [L744] EXPR 2 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L744] 2 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) [L745] EXPR 2 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L745] 2 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) [L746] EXPR 2 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L746] 2 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L747] EXPR 2 weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L747] 2 z$r_buff0_thd2 = weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) [L748] EXPR 2 weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L748] 2 z$r_buff1_thd2 = weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L749] 2 __unbuffered_p1_EBX = z VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L750] EXPR 2 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L750] 2 z = z$flush_delayed ? z$mem_tmp : z [L751] 2 z$flush_delayed = (_Bool)0 [L756] 2 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L813] -1 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] -1 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L818] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] -1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L819] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L819] -1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L820] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L820] -1 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L821] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L821] -1 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L824] -1 main$tmp_guard1 = !(x == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 0) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] ----- [2018-11-22 21:52:30,559 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_b74de183-1965-4aa2-920e-a39a059df344/bin-2019/uautomizer/witness.graphml [2018-11-22 21:52:30,559 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-22 21:52:30,560 INFO L168 Benchmark]: Toolchain (without parser) took 155557.90 ms. Allocated memory was 1.0 GB in the beginning and 8.8 GB in the end (delta: 7.8 GB). Free memory was 957.5 MB in the beginning and 6.5 GB in the end (delta: -5.5 GB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. [2018-11-22 21:52:30,561 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 21:52:30,561 INFO L168 Benchmark]: CACSL2BoogieTranslator took 416.46 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 144.2 MB). Free memory was 957.5 MB in the beginning and 1.1 GB in the end (delta: -162.9 MB). Peak memory consumption was 38.1 MB. Max. memory is 11.5 GB. [2018-11-22 21:52:30,561 INFO L168 Benchmark]: Boogie Procedure Inliner took 37.27 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. [2018-11-22 21:52:30,562 INFO L168 Benchmark]: Boogie Preprocessor took 22.64 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. [2018-11-22 21:52:30,562 INFO L168 Benchmark]: RCFGBuilder took 631.76 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 47.2 MB). Peak memory consumption was 47.2 MB. Max. memory is 11.5 GB. [2018-11-22 21:52:30,562 INFO L168 Benchmark]: TraceAbstraction took 149613.38 ms. Allocated memory was 1.2 GB in the beginning and 8.8 GB in the end (delta: 7.7 GB). Free memory was 1.1 GB in the beginning and 6.6 GB in the end (delta: -5.5 GB). Peak memory consumption was 2.1 GB. Max. memory is 11.5 GB. [2018-11-22 21:52:30,563 INFO L168 Benchmark]: Witness Printer took 4833.13 ms. Allocated memory is still 8.8 GB. Free memory was 6.6 GB in the beginning and 6.5 GB in the end (delta: 146.7 MB). Peak memory consumption was 146.7 MB. Max. memory is 11.5 GB. [2018-11-22 21:52:30,564 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 416.46 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 144.2 MB). Free memory was 957.5 MB in the beginning and 1.1 GB in the end (delta: -162.9 MB). Peak memory consumption was 38.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 37.27 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 22.64 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 631.76 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 47.2 MB). Peak memory consumption was 47.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 149613.38 ms. Allocated memory was 1.2 GB in the beginning and 8.8 GB in the end (delta: 7.7 GB). Free memory was 1.1 GB in the beginning and 6.6 GB in the end (delta: -5.5 GB). Peak memory consumption was 2.1 GB. Max. memory is 11.5 GB. * Witness Printer took 4833.13 ms. Allocated memory is still 8.8 GB. Free memory was 6.6 GB in the beginning and 6.5 GB in the end (delta: 146.7 MB). Peak memory consumption was 146.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L672] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L674] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L676] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L678] -1 int __unbuffered_p2_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0] [L680] -1 int __unbuffered_p2_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0] [L682] -1 int a = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0] [L684] -1 int b = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0] [L685] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0] [L686] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0] [L688] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L690] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L692] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L693] -1 _Bool z$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0] [L694] -1 int z$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0] [L695] -1 _Bool z$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0] [L696] -1 _Bool z$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0] [L697] -1 _Bool z$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0] [L698] -1 _Bool z$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0] [L699] -1 _Bool z$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0] [L700] -1 _Bool z$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0] [L701] -1 _Bool z$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0] [L702] -1 _Bool z$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0] [L703] -1 _Bool z$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0] [L704] -1 int *z$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}] [L705] -1 int z$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0] [L706] -1 _Bool z$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0] [L707] -1 int z$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0] [L708] -1 _Bool z$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L709] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L710] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L806] -1 pthread_t t896; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L807] FCALL, FORK -1 pthread_create(&t896, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L808] -1 pthread_t t897; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L809] FCALL, FORK -1 pthread_create(&t897, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L810] -1 pthread_t t898; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L811] FCALL, FORK -1 pthread_create(&t898, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L763] 0 z$w_buff1 = z$w_buff0 [L764] 0 z$w_buff0 = 1 [L765] 0 z$w_buff1_used = z$w_buff0_used [L766] 0 z$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] 0 z$r_buff1_thd0 = z$r_buff0_thd0 [L769] 0 z$r_buff1_thd1 = z$r_buff0_thd1 [L770] 0 z$r_buff1_thd2 = z$r_buff0_thd2 [L771] 0 z$r_buff1_thd3 = z$r_buff0_thd3 [L772] 0 z$r_buff0_thd3 = (_Bool)1 [L775] 0 a = 1 [L778] 0 __unbuffered_p2_EAX = a [L781] 0 __unbuffered_p2_EBX = b VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L714] 1 b = 1 [L717] 1 x = 1 [L722] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L729] 2 x = 2 [L732] 2 y = 1 [L735] 2 __unbuffered_p1_EAX = y [L738] 2 weak$$choice0 = __VERIFIER_nondet_pointer() [L739] 2 weak$$choice2 = __VERIFIER_nondet_pointer() [L740] 2 z$flush_delayed = weak$$choice2 [L741] 2 z$mem_tmp = z VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] EXPR 2 !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] 0 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L785] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L785] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L786] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L786] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L787] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L787] 0 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L788] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L788] 0 z$r_buff1_thd3 = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 [L791] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L742] 2 z = !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) [L743] EXPR 2 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0))=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L743] 2 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) [L744] EXPR 2 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L744] 2 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) [L745] EXPR 2 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L745] 2 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) [L746] EXPR 2 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L746] 2 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L747] EXPR 2 weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L747] 2 z$r_buff0_thd2 = weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) [L748] EXPR 2 weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L748] 2 z$r_buff1_thd2 = weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L749] 2 __unbuffered_p1_EBX = z VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L750] EXPR 2 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L750] 2 z = z$flush_delayed ? z$mem_tmp : z [L751] 2 z$flush_delayed = (_Bool)0 [L756] 2 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L813] -1 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] -1 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L818] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] -1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L819] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L819] -1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L820] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L820] -1 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L821] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L821] -1 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L824] -1 main$tmp_guard1 = !(x == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 0) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 7 procedures, 221 locations, 3 error locations. UNSAFE Result, 149.5s OverallTime, 27 OverallIterations, 1 TraceHistogramMax, 39.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 7640 SDtfs, 9538 SDslu, 18412 SDs, 0 SdLazy, 6724 SolverSat, 387 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 252 GetRequests, 67 SyntacticMatches, 16 SemanticMatches, 169 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 139 ImplicationChecksByTransitivity, 2.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=302982occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 82.2s AutomataMinimizationTime, 26 MinimizatonAttempts, 658487 StatesRemovedByMinimization, 22 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.1s SatisfiabilityAnalysisTime, 2.1s InterpolantComputationTime, 2036 NumberOfCodeBlocks, 2036 NumberOfCodeBlocksAsserted, 27 NumberOfCheckSat, 1915 ConstructedInterpolants, 0 QuantifiedInterpolants, 352332 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 26 InterpolantComputations, 26 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...