./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/ldv-races/race-2_5-container_of_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/ldv-races/race-2_5-container_of_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash f304bbeec274f04c648f2bacc19ae28d00889b1b ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 03:42:47,605 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 03:42:47,607 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 03:42:47,613 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 03:42:47,614 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 03:42:47,614 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 03:42:47,615 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 03:42:47,616 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 03:42:47,618 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 03:42:47,619 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 03:42:47,619 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 03:42:47,620 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 03:42:47,620 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 03:42:47,622 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 03:42:47,623 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 03:42:47,623 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 03:42:47,624 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 03:42:47,625 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 03:42:47,627 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 03:42:47,628 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 03:42:47,629 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 03:42:47,630 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 03:42:47,631 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 03:42:47,631 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 03:42:47,631 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 03:42:47,632 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 03:42:47,633 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 03:42:47,634 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 03:42:47,635 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 03:42:47,636 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 03:42:47,636 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 03:42:47,636 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 03:42:47,636 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 03:42:47,637 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 03:42:47,638 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 03:42:47,638 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 03:42:47,639 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-23 03:42:47,649 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 03:42:47,649 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 03:42:47,650 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 03:42:47,650 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 03:42:47,651 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 03:42:47,651 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 03:42:47,651 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 03:42:47,651 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 03:42:47,651 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 03:42:47,651 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 03:42:47,651 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 03:42:47,652 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 03:42:47,652 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 03:42:47,652 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 03:42:47,652 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 03:42:47,652 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 03:42:47,652 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 03:42:47,652 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 03:42:47,653 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 03:42:47,653 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 03:42:47,655 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 03:42:47,655 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 03:42:47,655 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 03:42:47,655 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 03:42:47,655 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 03:42:47,656 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 03:42:47,656 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 03:42:47,656 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 03:42:47,656 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 03:42:47,656 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 03:42:47,656 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> f304bbeec274f04c648f2bacc19ae28d00889b1b [2018-11-23 03:42:47,682 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 03:42:47,692 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 03:42:47,695 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 03:42:47,696 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 03:42:47,697 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 03:42:47,697 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-races/race-2_5-container_of_false-unreach-call.i [2018-11-23 03:42:47,748 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer/data/e54965d25/edf22e8f998c4273bdfd9e88b5530b2c/FLAG225a937f6 [2018-11-23 03:42:48,172 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 03:42:48,172 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/sv-benchmarks/c/ldv-races/race-2_5-container_of_false-unreach-call.i [2018-11-23 03:42:48,188 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer/data/e54965d25/edf22e8f998c4273bdfd9e88b5530b2c/FLAG225a937f6 [2018-11-23 03:42:48,200 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer/data/e54965d25/edf22e8f998c4273bdfd9e88b5530b2c [2018-11-23 03:42:48,203 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 03:42:48,204 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 03:42:48,205 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 03:42:48,205 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 03:42:48,209 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 03:42:48,210 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 03:42:48" (1/1) ... [2018-11-23 03:42:48,212 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@23e010b6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:48, skipping insertion in model container [2018-11-23 03:42:48,212 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 03:42:48" (1/1) ... [2018-11-23 03:42:48,221 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 03:42:48,274 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 03:42:48,805 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 03:42:48,884 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 03:42:48,938 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 03:42:49,077 INFO L195 MainTranslator]: Completed translation [2018-11-23 03:42:49,077 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:49 WrapperNode [2018-11-23 03:42:49,077 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 03:42:49,078 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 03:42:49,078 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 03:42:49,078 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 03:42:49,086 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:49" (1/1) ... [2018-11-23 03:42:49,108 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:49" (1/1) ... [2018-11-23 03:42:49,130 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 03:42:49,131 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 03:42:49,131 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 03:42:49,131 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 03:42:49,138 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:49" (1/1) ... [2018-11-23 03:42:49,138 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:49" (1/1) ... [2018-11-23 03:42:49,142 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:49" (1/1) ... [2018-11-23 03:42:49,142 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:49" (1/1) ... [2018-11-23 03:42:49,154 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:49" (1/1) ... [2018-11-23 03:42:49,157 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:49" (1/1) ... [2018-11-23 03:42:49,161 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:49" (1/1) ... [2018-11-23 03:42:49,166 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 03:42:49,166 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 03:42:49,167 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 03:42:49,167 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 03:42:49,167 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:49" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 03:42:49,219 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 03:42:49,220 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 03:42:49,220 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-23 03:42:49,220 INFO L130 BoogieDeclarations]: Found specification of procedure #PthreadsMutexLock [2018-11-23 03:42:49,220 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-11-23 03:42:49,220 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 03:42:49,220 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 03:42:49,220 INFO L130 BoogieDeclarations]: Found specification of procedure my_callback [2018-11-23 03:42:49,221 INFO L138 BoogieDeclarations]: Found implementation of procedure my_callback [2018-11-23 03:42:49,221 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 03:42:49,221 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-11-23 03:42:49,222 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-23 03:42:49,711 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 03:42:49,711 INFO L280 CfgBuilder]: Removed 24 assue(true) statements. [2018-11-23 03:42:49,711 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 03:42:49 BoogieIcfgContainer [2018-11-23 03:42:49,711 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 03:42:49,712 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 03:42:49,713 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 03:42:49,715 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 03:42:49,716 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 03:42:48" (1/3) ... [2018-11-23 03:42:49,716 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@273e7f3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 03:42:49, skipping insertion in model container [2018-11-23 03:42:49,716 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 03:42:49" (2/3) ... [2018-11-23 03:42:49,717 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@273e7f3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 03:42:49, skipping insertion in model container [2018-11-23 03:42:49,717 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 03:42:49" (3/3) ... [2018-11-23 03:42:49,718 INFO L112 eAbstractionObserver]: Analyzing ICFG race-2_5-container_of_false-unreach-call.i [2018-11-23 03:42:49,745 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,745 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,746 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,746 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,746 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,746 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,746 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~dev~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,747 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~dev~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,747 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,747 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,747 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~dev~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,747 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~dev~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,747 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~__mptr~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,748 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~__mptr~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,748 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~__mptr~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,748 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~__mptr~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,748 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,748 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,749 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,749 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,749 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#t~nondet30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,749 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#t~nondet30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,749 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,750 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,750 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,750 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,750 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#t~mem31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,750 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,751 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#t~mem31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,751 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,751 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#t~mem31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,752 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,752 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,752 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,752 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,752 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,753 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,753 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,753 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,753 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,753 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,753 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~dev~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,754 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~dev~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,754 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,754 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,754 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~dev~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,754 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~dev~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,754 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~__mptr~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,755 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~__mptr~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,755 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~__mptr~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,755 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~__mptr~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,755 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,755 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,756 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,756 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,756 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#t~nondet30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,756 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#t~nondet30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,757 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,757 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,757 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,757 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,757 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#t~mem31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,758 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,758 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#t~mem31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,758 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,758 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#t~mem31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,758 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,759 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,759 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,759 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 03:42:49,779 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-23 03:42:49,780 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 03:42:49,787 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2018-11-23 03:42:49,801 INFO L257 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2018-11-23 03:42:49,825 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 03:42:49,826 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 03:42:49,826 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 03:42:49,826 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 03:42:49,827 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 03:42:49,827 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 03:42:49,827 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 03:42:49,827 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 03:42:49,827 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 03:42:49,838 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 146places, 154 transitions [2018-11-23 03:42:50,093 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 9148 states. [2018-11-23 03:42:50,095 INFO L276 IsEmpty]: Start isEmpty. Operand 9148 states. [2018-11-23 03:42:50,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-11-23 03:42:50,104 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:42:50,104 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:42:50,106 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:42:50,110 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:42:50,110 INFO L82 PathProgramCache]: Analyzing trace with hash 1070418997, now seen corresponding path program 1 times [2018-11-23 03:42:50,112 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:42:50,113 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:42:50,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:50,208 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:42:50,209 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:50,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:42:50,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:42:50,482 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:42:50,483 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:42:50,486 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:42:50,500 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:42:50,501 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:42:50,503 INFO L87 Difference]: Start difference. First operand 9148 states. Second operand 6 states. [2018-11-23 03:42:51,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:42:51,184 INFO L93 Difference]: Finished difference Result 13043 states and 36091 transitions. [2018-11-23 03:42:51,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 03:42:51,185 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 43 [2018-11-23 03:42:51,186 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:42:51,230 INFO L225 Difference]: With dead ends: 13043 [2018-11-23 03:42:51,230 INFO L226 Difference]: Without dead ends: 10972 [2018-11-23 03:42:51,232 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=59, Invalid=123, Unknown=0, NotChecked=0, Total=182 [2018-11-23 03:42:51,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10972 states. [2018-11-23 03:42:51,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10972 to 8396. [2018-11-23 03:42:51,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8396 states. [2018-11-23 03:42:51,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8396 states to 8396 states and 22955 transitions. [2018-11-23 03:42:51,471 INFO L78 Accepts]: Start accepts. Automaton has 8396 states and 22955 transitions. Word has length 43 [2018-11-23 03:42:51,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:42:51,471 INFO L480 AbstractCegarLoop]: Abstraction has 8396 states and 22955 transitions. [2018-11-23 03:42:51,471 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:42:51,472 INFO L276 IsEmpty]: Start isEmpty. Operand 8396 states and 22955 transitions. [2018-11-23 03:42:51,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-23 03:42:51,477 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:42:51,481 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:42:51,482 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:42:51,482 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:42:51,482 INFO L82 PathProgramCache]: Analyzing trace with hash -31792251, now seen corresponding path program 1 times [2018-11-23 03:42:51,482 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:42:51,482 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:42:51,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:51,494 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:42:51,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:51,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:42:51,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:42:51,673 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:42:51,673 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 03:42:51,674 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 03:42:51,674 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 03:42:51,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:42:51,675 INFO L87 Difference]: Start difference. First operand 8396 states and 22955 transitions. Second operand 8 states. [2018-11-23 03:42:52,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:42:52,322 INFO L93 Difference]: Finished difference Result 11652 states and 31765 transitions. [2018-11-23 03:42:52,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 03:42:52,323 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 49 [2018-11-23 03:42:52,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:42:52,350 INFO L225 Difference]: With dead ends: 11652 [2018-11-23 03:42:52,351 INFO L226 Difference]: Without dead ends: 9858 [2018-11-23 03:42:52,351 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 56 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=90, Invalid=216, Unknown=0, NotChecked=0, Total=306 [2018-11-23 03:42:52,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9858 states. [2018-11-23 03:42:52,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9858 to 9536. [2018-11-23 03:42:52,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9536 states. [2018-11-23 03:42:52,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9536 states to 9536 states and 26143 transitions. [2018-11-23 03:42:52,509 INFO L78 Accepts]: Start accepts. Automaton has 9536 states and 26143 transitions. Word has length 49 [2018-11-23 03:42:52,509 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:42:52,509 INFO L480 AbstractCegarLoop]: Abstraction has 9536 states and 26143 transitions. [2018-11-23 03:42:52,509 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 03:42:52,510 INFO L276 IsEmpty]: Start isEmpty. Operand 9536 states and 26143 transitions. [2018-11-23 03:42:52,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-23 03:42:52,515 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:42:52,516 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:42:52,516 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:42:52,516 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:42:52,516 INFO L82 PathProgramCache]: Analyzing trace with hash -1087713938, now seen corresponding path program 1 times [2018-11-23 03:42:52,517 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:42:52,517 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:42:52,525 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:52,525 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:42:52,525 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:52,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:42:52,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:42:52,619 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:42:52,620 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 03:42:52,620 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 03:42:52,620 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 03:42:52,620 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 03:42:52,621 INFO L87 Difference]: Start difference. First operand 9536 states and 26143 transitions. Second operand 5 states. [2018-11-23 03:42:52,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:42:52,689 INFO L93 Difference]: Finished difference Result 3711 states and 9633 transitions. [2018-11-23 03:42:52,690 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 03:42:52,690 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 57 [2018-11-23 03:42:52,690 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:42:52,699 INFO L225 Difference]: With dead ends: 3711 [2018-11-23 03:42:52,699 INFO L226 Difference]: Without dead ends: 3711 [2018-11-23 03:42:52,699 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:42:52,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3711 states. [2018-11-23 03:42:52,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3711 to 3711. [2018-11-23 03:42:52,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3711 states. [2018-11-23 03:42:52,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3711 states to 3711 states and 9633 transitions. [2018-11-23 03:42:52,816 INFO L78 Accepts]: Start accepts. Automaton has 3711 states and 9633 transitions. Word has length 57 [2018-11-23 03:42:52,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:42:52,816 INFO L480 AbstractCegarLoop]: Abstraction has 3711 states and 9633 transitions. [2018-11-23 03:42:52,817 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 03:42:52,817 INFO L276 IsEmpty]: Start isEmpty. Operand 3711 states and 9633 transitions. [2018-11-23 03:42:52,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-23 03:42:52,823 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:42:52,824 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:42:52,824 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:42:52,824 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:42:52,824 INFO L82 PathProgramCache]: Analyzing trace with hash 527323425, now seen corresponding path program 1 times [2018-11-23 03:42:52,824 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:42:52,824 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:42:52,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:52,835 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:42:52,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:52,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:42:52,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:42:52,978 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:42:52,979 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 03:42:52,979 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 03:42:52,979 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 03:42:52,979 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 03:42:52,979 INFO L87 Difference]: Start difference. First operand 3711 states and 9633 transitions. Second operand 6 states. [2018-11-23 03:42:53,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:42:53,331 INFO L93 Difference]: Finished difference Result 4030 states and 10208 transitions. [2018-11-23 03:42:53,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 03:42:53,332 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2018-11-23 03:42:53,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:42:53,339 INFO L225 Difference]: With dead ends: 4030 [2018-11-23 03:42:53,339 INFO L226 Difference]: Without dead ends: 4030 [2018-11-23 03:42:53,339 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 10 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=59, Invalid=123, Unknown=0, NotChecked=0, Total=182 [2018-11-23 03:42:53,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4030 states. [2018-11-23 03:42:53,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4030 to 3763. [2018-11-23 03:42:53,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3763 states. [2018-11-23 03:42:53,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3763 states to 3763 states and 9725 transitions. [2018-11-23 03:42:53,406 INFO L78 Accepts]: Start accepts. Automaton has 3763 states and 9725 transitions. Word has length 72 [2018-11-23 03:42:53,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:42:53,406 INFO L480 AbstractCegarLoop]: Abstraction has 3763 states and 9725 transitions. [2018-11-23 03:42:53,406 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 03:42:53,407 INFO L276 IsEmpty]: Start isEmpty. Operand 3763 states and 9725 transitions. [2018-11-23 03:42:53,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-23 03:42:53,413 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:42:53,413 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:42:53,413 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:42:53,413 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:42:53,414 INFO L82 PathProgramCache]: Analyzing trace with hash -326132827, now seen corresponding path program 1 times [2018-11-23 03:42:53,414 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:42:53,414 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:42:53,423 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:53,423 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:42:53,423 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:53,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:42:53,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:42:53,593 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:42:53,593 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 03:42:53,593 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 03:42:53,593 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 03:42:53,593 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:42:53,593 INFO L87 Difference]: Start difference. First operand 3763 states and 9725 transitions. Second operand 8 states. [2018-11-23 03:42:54,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:42:54,284 INFO L93 Difference]: Finished difference Result 4117 states and 10347 transitions. [2018-11-23 03:42:54,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 03:42:54,284 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 78 [2018-11-23 03:42:54,284 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:42:54,288 INFO L225 Difference]: With dead ends: 4117 [2018-11-23 03:42:54,288 INFO L226 Difference]: Without dead ends: 4117 [2018-11-23 03:42:54,288 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 12 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=91, Invalid=215, Unknown=0, NotChecked=0, Total=306 [2018-11-23 03:42:54,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4117 states. [2018-11-23 03:42:54,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4117 to 3941. [2018-11-23 03:42:54,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3941 states. [2018-11-23 03:42:54,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3941 states to 3941 states and 10065 transitions. [2018-11-23 03:42:54,340 INFO L78 Accepts]: Start accepts. Automaton has 3941 states and 10065 transitions. Word has length 78 [2018-11-23 03:42:54,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:42:54,340 INFO L480 AbstractCegarLoop]: Abstraction has 3941 states and 10065 transitions. [2018-11-23 03:42:54,340 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 03:42:54,340 INFO L276 IsEmpty]: Start isEmpty. Operand 3941 states and 10065 transitions. [2018-11-23 03:42:54,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-23 03:42:54,345 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:42:54,345 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:42:54,345 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:42:54,345 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:42:54,346 INFO L82 PathProgramCache]: Analyzing trace with hash 496767872, now seen corresponding path program 1 times [2018-11-23 03:42:54,346 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:42:54,346 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:42:54,352 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:54,352 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:42:54,352 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:54,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:42:55,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:42:55,130 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:42:55,130 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2018-11-23 03:42:55,130 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-23 03:42:55,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-23 03:42:55,131 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=339, Unknown=0, NotChecked=0, Total=380 [2018-11-23 03:42:55,131 INFO L87 Difference]: Start difference. First operand 3941 states and 10065 transitions. Second operand 20 states. [2018-11-23 03:42:55,914 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 43 [2018-11-23 03:42:56,084 WARN L180 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 48 [2018-11-23 03:42:56,260 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 53 [2018-11-23 03:42:56,485 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 58 [2018-11-23 03:42:56,683 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 63 [2018-11-23 03:42:56,914 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 70 [2018-11-23 03:42:57,611 WARN L180 SmtUtils]: Spent 127.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 56 [2018-11-23 03:42:57,728 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 46 [2018-11-23 03:42:57,961 WARN L180 SmtUtils]: Spent 186.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 61 [2018-11-23 03:42:58,104 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 51 [2018-11-23 03:42:58,322 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 66 [2018-11-23 03:42:58,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:42:58,471 INFO L93 Difference]: Finished difference Result 13224 states and 33348 transitions. [2018-11-23 03:42:58,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-23 03:42:58,472 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 80 [2018-11-23 03:42:58,472 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:42:58,484 INFO L225 Difference]: With dead ends: 13224 [2018-11-23 03:42:58,485 INFO L226 Difference]: Without dead ends: 13224 [2018-11-23 03:42:58,485 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 130 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=534, Invalid=1272, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 03:42:58,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13224 states. [2018-11-23 03:42:58,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13224 to 4240. [2018-11-23 03:42:58,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4240 states. [2018-11-23 03:42:58,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4240 states to 4240 states and 10861 transitions. [2018-11-23 03:42:58,585 INFO L78 Accepts]: Start accepts. Automaton has 4240 states and 10861 transitions. Word has length 80 [2018-11-23 03:42:58,586 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:42:58,586 INFO L480 AbstractCegarLoop]: Abstraction has 4240 states and 10861 transitions. [2018-11-23 03:42:58,586 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-23 03:42:58,586 INFO L276 IsEmpty]: Start isEmpty. Operand 4240 states and 10861 transitions. [2018-11-23 03:42:58,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-23 03:42:58,592 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:42:58,592 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:42:58,592 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:42:58,593 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:42:58,593 INFO L82 PathProgramCache]: Analyzing trace with hash -1984776381, now seen corresponding path program 1 times [2018-11-23 03:42:58,593 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:42:58,593 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:42:58,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:58,600 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:42:58,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:58,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:42:58,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:42:58,745 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:42:58,746 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 03:42:58,746 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 03:42:58,746 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 03:42:58,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-23 03:42:58,746 INFO L87 Difference]: Start difference. First operand 4240 states and 10861 transitions. Second operand 8 states. [2018-11-23 03:42:59,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:42:59,018 INFO L93 Difference]: Finished difference Result 4454 states and 11267 transitions. [2018-11-23 03:42:59,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-23 03:42:59,018 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 80 [2018-11-23 03:42:59,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:42:59,023 INFO L225 Difference]: With dead ends: 4454 [2018-11-23 03:42:59,023 INFO L226 Difference]: Without dead ends: 4454 [2018-11-23 03:42:59,024 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=122, Unknown=0, NotChecked=0, Total=182 [2018-11-23 03:42:59,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4454 states. [2018-11-23 03:42:59,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4454 to 4409. [2018-11-23 03:42:59,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4409 states. [2018-11-23 03:42:59,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4409 states to 4409 states and 11180 transitions. [2018-11-23 03:42:59,092 INFO L78 Accepts]: Start accepts. Automaton has 4409 states and 11180 transitions. Word has length 80 [2018-11-23 03:42:59,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:42:59,092 INFO L480 AbstractCegarLoop]: Abstraction has 4409 states and 11180 transitions. [2018-11-23 03:42:59,092 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 03:42:59,092 INFO L276 IsEmpty]: Start isEmpty. Operand 4409 states and 11180 transitions. [2018-11-23 03:42:59,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-23 03:42:59,098 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:42:59,098 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:42:59,098 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:42:59,099 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:42:59,099 INFO L82 PathProgramCache]: Analyzing trace with hash 1184086607, now seen corresponding path program 2 times [2018-11-23 03:42:59,099 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:42:59,099 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:42:59,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:59,110 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 03:42:59,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:42:59,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:42:59,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:42:59,640 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:42:59,640 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2018-11-23 03:42:59,640 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-23 03:42:59,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-23 03:42:59,641 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=229, Unknown=0, NotChecked=0, Total=272 [2018-11-23 03:42:59,641 INFO L87 Difference]: Start difference. First operand 4409 states and 11180 transitions. Second operand 17 states. [2018-11-23 03:43:00,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:43:00,746 INFO L93 Difference]: Finished difference Result 4301 states and 10952 transitions. [2018-11-23 03:43:00,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-23 03:43:00,746 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 80 [2018-11-23 03:43:00,746 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:43:00,750 INFO L225 Difference]: With dead ends: 4301 [2018-11-23 03:43:00,750 INFO L226 Difference]: Without dead ends: 4301 [2018-11-23 03:43:00,750 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 122 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=356, Invalid=766, Unknown=0, NotChecked=0, Total=1122 [2018-11-23 03:43:00,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4301 states. [2018-11-23 03:43:00,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4301 to 4143. [2018-11-23 03:43:00,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4143 states. [2018-11-23 03:43:00,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4143 states to 4143 states and 10658 transitions. [2018-11-23 03:43:00,805 INFO L78 Accepts]: Start accepts. Automaton has 4143 states and 10658 transitions. Word has length 80 [2018-11-23 03:43:00,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:43:00,805 INFO L480 AbstractCegarLoop]: Abstraction has 4143 states and 10658 transitions. [2018-11-23 03:43:00,805 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-23 03:43:00,805 INFO L276 IsEmpty]: Start isEmpty. Operand 4143 states and 10658 transitions. [2018-11-23 03:43:00,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-23 03:43:00,810 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:43:00,810 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:43:00,811 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:43:00,811 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:43:00,811 INFO L82 PathProgramCache]: Analyzing trace with hash -379378452, now seen corresponding path program 2 times [2018-11-23 03:43:00,811 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:43:00,811 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:43:00,863 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:43:00,863 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 03:43:00,864 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:43:00,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 03:43:01,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:43:01,608 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 03:43:01,608 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2018-11-23 03:43:01,608 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-23 03:43:01,609 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-23 03:43:01,609 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=339, Unknown=0, NotChecked=0, Total=380 [2018-11-23 03:43:01,609 INFO L87 Difference]: Start difference. First operand 4143 states and 10658 transitions. Second operand 20 states. [2018-11-23 03:43:02,577 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 48 [2018-11-23 03:43:02,760 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 53 [2018-11-23 03:43:03,001 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 58 [2018-11-23 03:43:03,217 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 62 [2018-11-23 03:43:03,458 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 67 [2018-11-23 03:43:03,990 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 46 [2018-11-23 03:43:04,276 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 51 [2018-11-23 03:43:04,490 WARN L180 SmtUtils]: Spent 181.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 65 [2018-11-23 03:43:04,663 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 56 [2018-11-23 03:43:04,869 WARN L180 SmtUtils]: Spent 174.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 70 [2018-11-23 03:43:05,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:43:05,016 INFO L93 Difference]: Finished difference Result 12814 states and 32036 transitions. [2018-11-23 03:43:05,016 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 03:43:05,016 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 80 [2018-11-23 03:43:05,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:43:05,023 INFO L225 Difference]: With dead ends: 12814 [2018-11-23 03:43:05,023 INFO L226 Difference]: Without dead ends: 12814 [2018-11-23 03:43:05,024 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 106 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=509, Invalid=1213, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 03:43:05,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12814 states. [2018-11-23 03:43:05,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12814 to 4238. [2018-11-23 03:43:05,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4238 states. [2018-11-23 03:43:05,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4238 states to 4238 states and 10850 transitions. [2018-11-23 03:43:05,099 INFO L78 Accepts]: Start accepts. Automaton has 4238 states and 10850 transitions. Word has length 80 [2018-11-23 03:43:05,099 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:43:05,100 INFO L480 AbstractCegarLoop]: Abstraction has 4238 states and 10850 transitions. [2018-11-23 03:43:05,100 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-23 03:43:05,100 INFO L276 IsEmpty]: Start isEmpty. Operand 4238 states and 10850 transitions. [2018-11-23 03:43:05,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-23 03:43:05,104 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 03:43:05,104 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 03:43:05,104 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 03:43:05,105 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 03:43:05,105 INFO L82 PathProgramCache]: Analyzing trace with hash -970443804, now seen corresponding path program 3 times [2018-11-23 03:43:05,105 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 03:43:05,105 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 03:43:05,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:43:05,110 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 03:43:05,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 03:43:05,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 03:43:05,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 03:43:05,164 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [295] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [205] L-1-->L3774: Formula: (= |v_#valid_1| (store |v_#valid_2| 0 0)) InVars {#valid=|v_#valid_2|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [282] L3774-->L3774-1: Formula: (and (= (select |v_#valid_4| |v_~#t1~0.base_1|) 0) (not (= |v_~#t1~0.base_1| 0)) (= 0 |v_~#t1~0.offset_1|) (= |v_#length_1| (store |v_#length_2| |v_~#t1~0.base_1| 4)) (= (store |v_#valid_4| |v_~#t1~0.base_1| 1) |v_#valid_3|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_4|} OutVars{~#t1~0.offset=|v_~#t1~0.offset_1|, #length=|v_#length_1|, ~#t1~0.base=|v_~#t1~0.base_1|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[~#t1~0.base, #valid, ~#t1~0.offset, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 [276] L3774-1-->L3774-2: Formula: (= 0 (select (select |v_#memory_int_1| |v_~#t1~0.base_2|) |v_~#t1~0.offset_2|)) InVars {#memory_int=|v_#memory_int_1|, ~#t1~0.offset=|v_~#t1~0.offset_2|, ~#t1~0.base=|v_~#t1~0.base_2|} OutVars{#memory_int=|v_#memory_int_1|, ~#t1~0.offset=|v_~#t1~0.offset_2|, ~#t1~0.base=|v_~#t1~0.base_2|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 [284] L3774-2-->L3774-3: Formula: (and (= 0 (select |v_#valid_6| |v_~#t2~0.base_1|)) (= (store |v_#length_4| |v_~#t2~0.base_1| 4) |v_#length_3|) (not (= 0 |v_~#t2~0.base_1|)) (= 0 |v_~#t2~0.offset_1|) (= |v_#valid_5| (store |v_#valid_6| |v_~#t2~0.base_1| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_6|} OutVars{#length=|v_#length_3|, ~#t2~0.base=|v_~#t2~0.base_1|, ~#t2~0.offset=|v_~#t2~0.offset_1|, #valid=|v_#valid_5|} AuxVars[] AssignedVars[~#t2~0.offset, #valid, #length, ~#t2~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [286] L3774-3-->L3774-4: Formula: (= (select (select |v_#memory_int_2| |v_~#t2~0.base_2|) |v_~#t2~0.offset_2|) 0) InVars {#memory_int=|v_#memory_int_2|, ~#t2~0.base=|v_~#t2~0.base_2|, ~#t2~0.offset=|v_~#t2~0.offset_2|} OutVars{#memory_int=|v_#memory_int_2|, ~#t2~0.base=|v_~#t2~0.base_2|, ~#t2~0.offset=|v_~#t2~0.offset_2|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [283] L3774-4-->L-1-1: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [315] L-1-1-->L3847: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~mem45=|v_ULTIMATE.start_main_#t~mem45_1|, ULTIMATE.start_main_#t~mem46=|v_ULTIMATE.start_main_#t~mem46_1|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_1|, ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_1, ULTIMATE.start_main_#t~mem44=|v_ULTIMATE.start_main_#t~mem44_1|, ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_1|, ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_1|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_1|, ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_1, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem45, ULTIMATE.start_main_#t~mem46, ULTIMATE.start_main_#t~mem43, ULTIMATE.start_main_~ret~0, ULTIMATE.start_main_#t~mem44, ULTIMATE.start_main_#t~ret41, ULTIMATE.start_main_#t~ret42, ULTIMATE.start_main_~#data~1.offset, ULTIMATE.start_main_~probe_ret~0, ULTIMATE.start_main_~#data~1.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [207] L3847-->L3839: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_init_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [198] L3839-->L3839-1: Formula: (= |v_ULTIMATE.start_my_drv_init_#res_2| 0) InVars {} OutVars{ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_init_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [328] L3839-1-->L3847-1: Formula: (= |v_ULTIMATE.start_main_#t~ret41_2| |v_ULTIMATE.start_my_drv_init_#res_3|) InVars {ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_3|} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_2|, ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret41] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [218] L3847-1-->L3847-2: Formula: (and (<= |v_ULTIMATE.start_main_#t~ret41_3| 2147483647) (<= 0 (+ |v_ULTIMATE.start_main_#t~ret41_3| 2147483648))) InVars {ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_3|} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_3|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [212] L3847-2-->L3847-3: Formula: (= v_ULTIMATE.start_main_~ret~0_2 |v_ULTIMATE.start_main_#t~ret41_4|) InVars {ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_4|} OutVars{ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_2, ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_~ret~0] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [195] L3847-3-->L3848: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret41] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [292] L3848-->L3849: Formula: (= v_ULTIMATE.start_main_~ret~0_3 0) InVars {ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_3} OutVars{ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_3} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [254] L3849-->L3850: Formula: true InVars {} OutVars{ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_~probe_ret~0] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [199] L3850-->L3850-1: Formula: (and (= 0 |v_ULTIMATE.start_main_~#data~1.offset_2|) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#data~1.base_2|) 0) (not (= |v_ULTIMATE.start_main_~#data~1.base_2| 0)) (= (store |v_#length_6| |v_ULTIMATE.start_main_~#data~1.base_2| 48) |v_#length_5|) (= (store |v_#valid_8| |v_ULTIMATE.start_main_~#data~1.base_2| 1) |v_#valid_7|)) InVars {#length=|v_#length_6|, #valid=|v_#valid_8|} OutVars{ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_2|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[#valid, ULTIMATE.start_main_~#data~1.offset, #length, ULTIMATE.start_main_~#data~1.base] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [324] L3850-1-->L3851: Formula: (and (= |v_ULTIMATE.start_my_drv_probe_#in~data.base_1| |v_ULTIMATE.start_main_~#data~1.base_3|) (= |v_ULTIMATE.start_my_drv_probe_#in~data.offset_1| |v_ULTIMATE.start_main_~#data~1.offset_3|)) InVars {ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_3|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_3|} OutVars{ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_1|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_3|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_3|, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#in~data.base, ULTIMATE.start_my_drv_probe_#in~data.offset] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [291] L3851-->L3851-1: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#res] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [290] L3851-1-->L3803: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_~d~0.offset=v_ULTIMATE.start_my_drv_probe_~d~0.offset_1, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_1, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_1, ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_1|, ULTIMATE.start_my_drv_probe_#t~nondet32=|v_ULTIMATE.start_my_drv_probe_#t~nondet32_1|, ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_1, ULTIMATE.start_my_drv_probe_#t~nondet34=|v_ULTIMATE.start_my_drv_probe_#t~nondet34_1|, ULTIMATE.start_my_drv_probe_~d~0.base=v_ULTIMATE.start_my_drv_probe_~d~0.base_1} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~d~0.offset, ULTIMATE.start_my_drv_probe_~data.base, ULTIMATE.start_my_drv_probe_~data.offset, ULTIMATE.start_my_drv_probe_#t~nondet33, ULTIMATE.start_my_drv_probe_#t~nondet32, ULTIMATE.start_my_drv_probe_~res~0, ULTIMATE.start_my_drv_probe_#t~nondet34, ULTIMATE.start_my_drv_probe_~d~0.base] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [219] L3803-->L3804: Formula: (and (= v_ULTIMATE.start_my_drv_probe_~data.offset_2 |v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|) (= v_ULTIMATE.start_my_drv_probe_~data.base_2 |v_ULTIMATE.start_my_drv_probe_#in~data.base_2|)) InVars {ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_2|, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|} OutVars{ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_2, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_2, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~data.base, ULTIMATE.start_my_drv_probe_~data.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [299] L3804-->L3808: Formula: (and (= v_ULTIMATE.start_my_drv_probe_~d~0.base_2 v_ULTIMATE.start_my_drv_probe_~data.base_3) (= v_ULTIMATE.start_my_drv_probe_~d~0.offset_2 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_3 40))) InVars {ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_3, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_3} OutVars{ULTIMATE.start_my_drv_probe_~d~0.offset=v_ULTIMATE.start_my_drv_probe_~d~0.offset_2, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_3, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_3, ULTIMATE.start_my_drv_probe_~d~0.base=v_ULTIMATE.start_my_drv_probe_~d~0.base_2} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~d~0.offset, ULTIMATE.start_my_drv_probe_~d~0.base] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [242] L3808-->L3809: Formula: (= |v_#pthreadsMutex_1| (store |v_#pthreadsMutex_2| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#pthreadsMutex_2| v_ULTIMATE.start_my_drv_probe_~data.base_4) v_ULTIMATE.start_my_drv_probe_~data.offset_4 0))) InVars {#pthreadsMutex=|v_#pthreadsMutex_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_4, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_4} OutVars{#pthreadsMutex=|v_#pthreadsMutex_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_4, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_4} AuxVars[] AssignedVars[#pthreadsMutex] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [316] L3809-->L3809-1: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_5 40))) (and (= (store |v_#memory_int_4| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_int_4| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 0)) |v_#memory_int_3|) (= |v_#memory_$Pointer$.base_1| (store |v_#memory_$Pointer$.base_2| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_$Pointer$.base_2| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_1| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0)))) (= |v_#memory_$Pointer$.offset_1| (store |v_#memory_$Pointer$.offset_2| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_$Pointer$.offset_2| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_1| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0)))))) InVars {#memory_int=|v_#memory_int_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_5, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_2|} OutVars{#memory_int=|v_#memory_int_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_5, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_1|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [314] L3809-1-->L3810: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_6 44))) (and (= (store |v_#memory_$Pointer$.base_4| v_ULTIMATE.start_my_drv_probe_~data.base_6 (store (select |v_#memory_$Pointer$.base_4| v_ULTIMATE.start_my_drv_probe_~data.base_6) .cse0 (select (select |v_#memory_$Pointer$.base_3| v_ULTIMATE.start_my_drv_probe_~data.base_6) .cse0))) |v_#memory_$Pointer$.base_3|) (= |v_#memory_$Pointer$.offset_3| (store |v_#memory_$Pointer$.offset_4| v_ULTIMATE.start_my_drv_probe_~data.base_6 (store (select |v_#memory_$Pointer$.offset_4| v_ULTIMATE.start_my_drv_probe_~data.base_6) .cse0 (select (select |v_#memory_$Pointer$.offset_3| v_ULTIMATE.start_my_drv_probe_~data.base_6) .cse0)))) (= (store |v_#memory_int_6| v_ULTIMATE.start_my_drv_probe_~data.base_6 (store (select |v_#memory_int_6| v_ULTIMATE.start_my_drv_probe_~data.base_6) .cse0 0)) |v_#memory_int_5|))) InVars {#memory_int=|v_#memory_int_6|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_4|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_6, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_6, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_4|} OutVars{#memory_int=|v_#memory_int_5|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_3|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_6, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_6, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_3|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [271] L3810-->L3812: Formula: (and (<= |v_ULTIMATE.start_my_drv_probe_#t~nondet32_2| 2147483647) (<= 0 (+ |v_ULTIMATE.start_my_drv_probe_#t~nondet32_2| 2147483648))) InVars {ULTIMATE.start_my_drv_probe_#t~nondet32=|v_ULTIMATE.start_my_drv_probe_#t~nondet32_2|} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet32=|v_ULTIMATE.start_my_drv_probe_#t~nondet32_2|} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [305] L3812-->L3812-1: Formula: (= v_ULTIMATE.start_my_drv_probe_~res~0_2 |v_ULTIMATE.start_my_drv_probe_#t~nondet32_3|) InVars {ULTIMATE.start_my_drv_probe_#t~nondet32=|v_ULTIMATE.start_my_drv_probe_#t~nondet32_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet32=|v_ULTIMATE.start_my_drv_probe_#t~nondet32_3|, ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_2} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~res~0] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [307] L3812-1-->L3813: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet32=|v_ULTIMATE.start_my_drv_probe_#t~nondet32_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet32] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [268] L3813-->L3816: Formula: (= v_ULTIMATE.start_my_drv_probe_~res~0_4 0) InVars {ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_4} OutVars{ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_4} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [251] L3816-->L3816-1: Formula: (and (= |v_#memory_$Pointer$.offset_5| (store |v_#memory_$Pointer$.offset_6| |v_~#t1~0.base_3| (store (select |v_#memory_$Pointer$.offset_6| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| (select (select |v_#memory_$Pointer$.offset_5| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3|)))) (= |v_#memory_int_7| (store |v_#memory_int_8| |v_~#t1~0.base_3| (store (select |v_#memory_int_8| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| 0))) (= (store |v_#memory_$Pointer$.base_6| |v_~#t1~0.base_3| (store (select |v_#memory_$Pointer$.base_6| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| (select (select |v_#memory_$Pointer$.base_5| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3|))) |v_#memory_$Pointer$.base_5|)) InVars {#memory_int=|v_#memory_int_8|, ~#t1~0.offset=|v_~#t1~0.offset_3|, ~#t1~0.base=|v_~#t1~0.base_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_6|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_6|} OutVars{#memory_int=|v_#memory_int_7|, ~#t1~0.offset=|v_~#t1~0.offset_3|, ~#t1~0.base=|v_~#t1~0.base_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_5|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_5|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] FORK -1 [358] L3816-1-->my_callbackENTRY: Formula: (and (= v_ULTIMATE.start_my_drv_probe_~d~0.base_4 |v_Thread0_my_callback_#in~arg.base_3|) (= v_ULTIMATE.start_my_drv_probe_~d~0.offset_4 |v_Thread0_my_callback_#in~arg.offset_3|) (= v_Thread0_my_callback_thidvar0_2 0)) InVars {ULTIMATE.start_my_drv_probe_~d~0.offset=v_ULTIMATE.start_my_drv_probe_~d~0.offset_4, ULTIMATE.start_my_drv_probe_~d~0.base=v_ULTIMATE.start_my_drv_probe_~d~0.base_4} OutVars{ULTIMATE.start_my_drv_probe_~d~0.offset=v_ULTIMATE.start_my_drv_probe_~d~0.offset_4, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_3|, Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_2, Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_3|, ULTIMATE.start_my_drv_probe_~d~0.base=v_ULTIMATE.start_my_drv_probe_~d~0.base_4} AuxVars[] AssignedVars[Thread0_my_callback_#in~arg.base, Thread0_my_callback_thidvar0, Thread0_my_callback_#in~arg.offset] VAL [Thread0_my_callback_thidvar0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [263] L3816-2-->L3817: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet33] VAL [Thread0_my_callback_thidvar0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [325] L3817-->L3817-1: Formula: (and (= (store |v_#memory_$Pointer$.base_8| |v_~#t2~0.base_3| (store (select |v_#memory_$Pointer$.base_8| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| (select (select |v_#memory_$Pointer$.base_7| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3|))) |v_#memory_$Pointer$.base_7|) (= (store |v_#memory_$Pointer$.offset_8| |v_~#t2~0.base_3| (store (select |v_#memory_$Pointer$.offset_8| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| (select (select |v_#memory_$Pointer$.offset_7| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3|))) |v_#memory_$Pointer$.offset_7|) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_~#t2~0.base_3| (store (select |v_#memory_int_10| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| 1)))) InVars {#memory_int=|v_#memory_int_10|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_8|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_8|, ~#t2~0.base=|v_~#t2~0.base_3|, ~#t2~0.offset=|v_~#t2~0.offset_3|} OutVars{#memory_int=|v_#memory_int_9|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_7|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_7|, ~#t2~0.base=|v_~#t2~0.base_3|, ~#t2~0.offset=|v_~#t2~0.offset_3|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] FORK -1 [359] L3817-1-->my_callbackENTRY: Formula: (and (= v_ULTIMATE.start_my_drv_probe_~d~0.base_6 |v_Thread1_my_callback_#in~arg.base_3|) (= v_ULTIMATE.start_my_drv_probe_~d~0.offset_6 |v_Thread1_my_callback_#in~arg.offset_3|) (= v_Thread1_my_callback_thidvar0_2 1)) InVars {ULTIMATE.start_my_drv_probe_~d~0.offset=v_ULTIMATE.start_my_drv_probe_~d~0.offset_6, ULTIMATE.start_my_drv_probe_~d~0.base=v_ULTIMATE.start_my_drv_probe_~d~0.base_6} OutVars{ULTIMATE.start_my_drv_probe_~d~0.offset=v_ULTIMATE.start_my_drv_probe_~d~0.offset_6, Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_2, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_3|, Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_3|, ULTIMATE.start_my_drv_probe_~d~0.base=v_ULTIMATE.start_my_drv_probe_~d~0.base_6} AuxVars[] AssignedVars[Thread1_my_callback_thidvar0, Thread1_my_callback_#in~arg.base, Thread1_my_callback_#in~arg.offset] VAL [Thread0_my_callback_thidvar0=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [322] L3817-2-->L3818: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet34=|v_ULTIMATE.start_my_drv_probe_#t~nondet34_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet34] VAL [Thread0_my_callback_thidvar0=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [289] L3818-->L3822: Formula: (= |v_ULTIMATE.start_my_drv_probe_#res_2| 0) InVars {} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#res] VAL [Thread0_my_callback_thidvar0=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [344] my_callbackENTRY-->L3792: Formula: (and (= v_Thread1_my_callback_~arg.offset_1 |v_Thread1_my_callback_#in~arg.offset_1|) (= v_Thread1_my_callback_~arg.base_1 |v_Thread1_my_callback_#in~arg.base_1|)) InVars {Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_1|, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_1|} OutVars{Thread1_my_callback_~arg.base=v_Thread1_my_callback_~arg.base_1, Thread1_my_callback_~arg.offset=v_Thread1_my_callback_~arg.offset_1, Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_1|, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_1|} AuxVars[] AssignedVars[Thread1_my_callback_~arg.base, Thread1_my_callback_~arg.offset] VAL [Thread0_my_callback_thidvar0=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [345] L3792-->L3793: Formula: (and (= v_Thread1_my_callback_~dev~0.base_1 v_Thread1_my_callback_~arg.base_2) (= v_Thread1_my_callback_~dev~0.offset_1 v_Thread1_my_callback_~arg.offset_2)) InVars {Thread1_my_callback_~arg.base=v_Thread1_my_callback_~arg.base_2, Thread1_my_callback_~arg.offset=v_Thread1_my_callback_~arg.offset_2} OutVars{Thread1_my_callback_~dev~0.base=v_Thread1_my_callback_~dev~0.base_1, Thread1_my_callback_~arg.base=v_Thread1_my_callback_~arg.base_2, Thread1_my_callback_~dev~0.offset=v_Thread1_my_callback_~dev~0.offset_1, Thread1_my_callback_~arg.offset=v_Thread1_my_callback_~arg.offset_2} AuxVars[] AssignedVars[Thread1_my_callback_~dev~0.base, Thread1_my_callback_~dev~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [346] L3793-->L3794: Formula: true InVars {} OutVars{Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_1, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_1} AuxVars[] AssignedVars[Thread1_my_callback_~data~0.offset, Thread1_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [330] my_callbackENTRY-->L3792: Formula: (and (= v_Thread0_my_callback_~arg.offset_1 |v_Thread0_my_callback_#in~arg.offset_1|) (= v_Thread0_my_callback_~arg.base_1 |v_Thread0_my_callback_#in~arg.base_1|)) InVars {Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_1|, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_1|} OutVars{Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_1|, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_1|, Thread0_my_callback_~arg.offset=v_Thread0_my_callback_~arg.offset_1, Thread0_my_callback_~arg.base=v_Thread0_my_callback_~arg.base_1} AuxVars[] AssignedVars[Thread0_my_callback_~arg.offset, Thread0_my_callback_~arg.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [331] L3792-->L3793: Formula: (and (= v_Thread0_my_callback_~dev~0.base_1 v_Thread0_my_callback_~arg.base_2) (= v_Thread0_my_callback_~dev~0.offset_1 v_Thread0_my_callback_~arg.offset_2)) InVars {Thread0_my_callback_~arg.offset=v_Thread0_my_callback_~arg.offset_2, Thread0_my_callback_~arg.base=v_Thread0_my_callback_~arg.base_2} OutVars{Thread0_my_callback_~dev~0.offset=v_Thread0_my_callback_~dev~0.offset_1, Thread0_my_callback_~dev~0.base=v_Thread0_my_callback_~dev~0.base_1, Thread0_my_callback_~arg.offset=v_Thread0_my_callback_~arg.offset_2, Thread0_my_callback_~arg.base=v_Thread0_my_callback_~arg.base_2} AuxVars[] AssignedVars[Thread0_my_callback_~dev~0.offset, Thread0_my_callback_~dev~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [347] L3794-->L3794-1: Formula: (and (= v_Thread1_my_callback_~__mptr~0.base_1 v_Thread1_my_callback_~dev~0.base_2) (= v_Thread1_my_callback_~__mptr~0.offset_1 v_Thread1_my_callback_~dev~0.offset_2)) InVars {Thread1_my_callback_~dev~0.base=v_Thread1_my_callback_~dev~0.base_2, Thread1_my_callback_~dev~0.offset=v_Thread1_my_callback_~dev~0.offset_2} OutVars{Thread1_my_callback_~dev~0.base=v_Thread1_my_callback_~dev~0.base_2, Thread1_my_callback_~dev~0.offset=v_Thread1_my_callback_~dev~0.offset_2, Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_1, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_1} AuxVars[] AssignedVars[Thread1_my_callback_~__mptr~0.base, Thread1_my_callback_~__mptr~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [332] L3793-->L3794: Formula: true InVars {} OutVars{Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_1, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_1} AuxVars[] AssignedVars[Thread0_my_callback_~data~0.offset, Thread0_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [348] L3794-1-->L3796: Formula: (and (= v_Thread1_my_callback_~data~0.base_2 v_Thread1_my_callback_~__mptr~0.base_2) (= v_Thread1_my_callback_~data~0.offset_2 (+ v_Thread1_my_callback_~__mptr~0.offset_2 (- 40)))) InVars {Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_2, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_2} OutVars{Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_2, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_2, Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_2, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_2} AuxVars[] AssignedVars[Thread1_my_callback_~data~0.offset, Thread1_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [333] L3794-->L3794-1: Formula: (and (= v_Thread0_my_callback_~__mptr~0.base_1 v_Thread0_my_callback_~dev~0.base_2) (= v_Thread0_my_callback_~__mptr~0.offset_1 v_Thread0_my_callback_~dev~0.offset_2)) InVars {Thread0_my_callback_~dev~0.offset=v_Thread0_my_callback_~dev~0.offset_2, Thread0_my_callback_~dev~0.base=v_Thread0_my_callback_~dev~0.base_2} OutVars{Thread0_my_callback_~dev~0.offset=v_Thread0_my_callback_~dev~0.offset_2, Thread0_my_callback_~dev~0.base=v_Thread0_my_callback_~dev~0.base_2, Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_1, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_1} AuxVars[] AssignedVars[Thread0_my_callback_~__mptr~0.base, Thread0_my_callback_~__mptr~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [222] L3822-->L3851-2: Formula: (= |v_ULTIMATE.start_main_#t~ret42_2| |v_ULTIMATE.start_my_drv_probe_#res_4|) InVars {ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_4|} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_4|, ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret42] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [280] L3851-2-->L3851-3: Formula: (and (<= 0 (+ |v_ULTIMATE.start_main_#t~ret42_3| 2147483648)) (<= |v_ULTIMATE.start_main_#t~ret42_3| 2147483647)) InVars {ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_3|} OutVars{ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_3|} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [277] L3851-3-->L3851-4: Formula: (= v_ULTIMATE.start_main_~probe_ret~0_3 |v_ULTIMATE.start_main_#t~ret42_4|) InVars {ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_4|} OutVars{ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_4|, ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_~probe_ret~0] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [278] L3851-4-->L3852: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret42] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [246] L3852-->L3853: Formula: (= v_ULTIMATE.start_main_~probe_ret~0_4 0) InVars {ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_4} OutVars{ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_4} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [311] L3853-->L3853-1: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#in~data.base_1| |v_ULTIMATE.start_main_~#data~1.base_4|) (= |v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_1| |v_ULTIMATE.start_main_~#data~1.offset_4|)) InVars {ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_4|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_4|} OutVars{ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_4|, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_1|, ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_1|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#in~data.offset, ULTIMATE.start_my_drv_disconnect_#in~data.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [317] L3853-1-->L3825: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_1|, ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_1, ULTIMATE.start_my_drv_disconnect_#t~mem37=|v_ULTIMATE.start_my_drv_disconnect_#t~mem37_1|, ULTIMATE.start_my_drv_disconnect_#t~mem39=|v_ULTIMATE.start_my_drv_disconnect_#t~mem39_1|, ULTIMATE.start_my_drv_disconnect_#t~mem35=|v_ULTIMATE.start_my_drv_disconnect_#t~mem35_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet40.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet40.base_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet40.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet40.offset_1|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_1|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_1, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38, ULTIMATE.start_my_drv_disconnect_~data.offset, ULTIMATE.start_my_drv_disconnect_#t~mem37, ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_#t~mem39, ULTIMATE.start_my_drv_disconnect_~data.base, ULTIMATE.start_my_drv_disconnect_~#status~0.base, ULTIMATE.start_my_drv_disconnect_#t~mem35, ULTIMATE.start_my_drv_disconnect_#t~nondet36.base, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet40.base, ULTIMATE.start_my_drv_disconnect_#t~nondet40.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [214] L3825-->L3826: Formula: (and (= v_ULTIMATE.start_my_drv_disconnect_~data.base_2 |v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|) (= v_ULTIMATE.start_my_drv_disconnect_~data.offset_2 |v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|)) InVars {ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|} OutVars{ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_2, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_2, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|, ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~data.offset, ULTIMATE.start_my_drv_disconnect_~data.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [294] L3826-->L3826-1: Formula: (and (= |v_#length_7| (store |v_#length_8| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2| 4)) (= (store |v_#valid_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2| 1) |v_#valid_9|) (= 0 (select |v_#valid_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|)) (= |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|))) InVars {#length=|v_#length_8|, #valid=|v_#valid_10|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_2|, #length=|v_#length_7|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.base, #valid, #length] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [300] L3826-1-->L3827: Formula: (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem35_2| (select (select |v_#memory_int_11| |v_~#t1~0.base_4|) |v_~#t1~0.offset_4|)) InVars {#memory_int=|v_#memory_int_11|, ~#t1~0.offset=|v_~#t1~0.offset_4|, ~#t1~0.base=|v_~#t1~0.base_4|} OutVars{#memory_int=|v_#memory_int_11|, ~#t1~0.offset=|v_~#t1~0.offset_4|, ~#t1~0.base=|v_~#t1~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~mem35=|v_ULTIMATE.start_my_drv_disconnect_#t~mem35_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem35] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [334] L3794-1-->L3796: Formula: (and (= v_Thread0_my_callback_~data~0.base_2 v_Thread0_my_callback_~__mptr~0.base_2) (= v_Thread0_my_callback_~data~0.offset_2 (+ v_Thread0_my_callback_~__mptr~0.offset_2 (- 40)))) InVars {Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_2, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_2} OutVars{Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_2, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_2, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_2, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_2} AuxVars[] AssignedVars[Thread0_my_callback_~data~0.offset, Thread0_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [335] L3796-->L3796-1: Formula: (let ((.cse0 (select |v_#pthreadsMutex_4| v_Thread0_my_callback_~data~0.base_3))) (and (= (store |v_#pthreadsMutex_4| v_Thread0_my_callback_~data~0.base_3 (store .cse0 v_Thread0_my_callback_~data~0.offset_3 1)) |v_#pthreadsMutex_3|) (= 0 |v_Thread0_my_callback_#t~nondet30_1|) (= (select .cse0 v_Thread0_my_callback_~data~0.offset_3) 0))) InVars {#pthreadsMutex=|v_#pthreadsMutex_4|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_3, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_3} OutVars{Thread0_my_callback_#t~nondet30=|v_Thread0_my_callback_#t~nondet30_1|, #pthreadsMutex=|v_#pthreadsMutex_3|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_3, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_3} AuxVars[] AssignedVars[#pthreadsMutex, Thread0_my_callback_#t~nondet30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#t~nondet30|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [336] L3796-1-->L3797: Formula: true InVars {} OutVars{Thread0_my_callback_#t~nondet30=|v_Thread0_my_callback_#t~nondet30_2|} AuxVars[] AssignedVars[Thread0_my_callback_#t~nondet30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [337] L3797-->L3797-1: Formula: (let ((.cse0 (+ v_Thread0_my_callback_~data~0.offset_4 40))) (and (= |v_#memory_$Pointer$.offset_21| (store |v_#memory_$Pointer$.offset_22| v_Thread0_my_callback_~data~0.base_4 (store (select |v_#memory_$Pointer$.offset_22| v_Thread0_my_callback_~data~0.base_4) .cse0 (select (select |v_#memory_$Pointer$.offset_21| v_Thread0_my_callback_~data~0.base_4) .cse0)))) (= |v_#memory_$Pointer$.base_21| (store |v_#memory_$Pointer$.base_22| v_Thread0_my_callback_~data~0.base_4 (store (select |v_#memory_$Pointer$.base_22| v_Thread0_my_callback_~data~0.base_4) .cse0 (select (select |v_#memory_$Pointer$.base_21| v_Thread0_my_callback_~data~0.base_4) .cse0)))) (= (store |v_#memory_int_32| v_Thread0_my_callback_~data~0.base_4 (store (select |v_#memory_int_32| v_Thread0_my_callback_~data~0.base_4) .cse0 1)) |v_#memory_int_31|))) InVars {#memory_int=|v_#memory_int_32|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_4, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_22|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_22|} OutVars{#memory_int=|v_#memory_int_31|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_4, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_21|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_21|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [338] L3797-1-->L3798: Formula: (= |v_Thread0_my_callback_#t~mem31_1| (select (select |v_#memory_int_33| v_Thread0_my_callback_~data~0.base_5) (+ v_Thread0_my_callback_~data~0.offset_5 44))) InVars {#memory_int=|v_#memory_int_33|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_5, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_5} OutVars{#memory_int=|v_#memory_int_33|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_5, Thread0_my_callback_#t~mem31=|v_Thread0_my_callback_#t~mem31_1|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_5} AuxVars[] AssignedVars[Thread0_my_callback_#t~mem31] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#t~mem31|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [339] L3798-->L3798-1: Formula: (let ((.cse0 (+ v_Thread0_my_callback_~data~0.offset_6 44))) (and (= |v_#memory_$Pointer$.base_23| (store |v_#memory_$Pointer$.base_24| v_Thread0_my_callback_~data~0.base_6 (store (select |v_#memory_$Pointer$.base_24| v_Thread0_my_callback_~data~0.base_6) .cse0 (select (select |v_#memory_$Pointer$.base_23| v_Thread0_my_callback_~data~0.base_6) .cse0)))) (= |v_#memory_$Pointer$.offset_23| (store |v_#memory_$Pointer$.offset_24| v_Thread0_my_callback_~data~0.base_6 (store (select |v_#memory_$Pointer$.offset_24| v_Thread0_my_callback_~data~0.base_6) .cse0 (select (select |v_#memory_$Pointer$.offset_23| v_Thread0_my_callback_~data~0.base_6) .cse0)))) (= (store |v_#memory_int_35| v_Thread0_my_callback_~data~0.base_6 (store (select |v_#memory_int_35| v_Thread0_my_callback_~data~0.base_6) .cse0 (+ |v_Thread0_my_callback_#t~mem31_2| 1))) |v_#memory_int_34|))) InVars {#memory_$Pointer$.base=|v_#memory_$Pointer$.base_24|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_6, #memory_int=|v_#memory_int_35|, Thread0_my_callback_#t~mem31=|v_Thread0_my_callback_#t~mem31_2|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_6, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_24|} OutVars{#memory_$Pointer$.base=|v_#memory_$Pointer$.base_23|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_6, #memory_int=|v_#memory_int_34|, Thread0_my_callback_#t~mem31=|v_Thread0_my_callback_#t~mem31_2|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_6, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_23|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#t~mem31|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [340] L3798-1-->L3799: Formula: true InVars {} OutVars{Thread0_my_callback_#t~mem31=|v_Thread0_my_callback_#t~mem31_3|} AuxVars[] AssignedVars[Thread0_my_callback_#t~mem31] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [341] L3799-->L3800: Formula: (= |v_#pthreadsMutex_5| (store |v_#pthreadsMutex_6| v_Thread0_my_callback_~data~0.base_7 (store (select |v_#pthreadsMutex_6| v_Thread0_my_callback_~data~0.base_7) v_Thread0_my_callback_~data~0.offset_7 0))) InVars {#pthreadsMutex=|v_#pthreadsMutex_6|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_7, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_7} OutVars{#pthreadsMutex=|v_#pthreadsMutex_5|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_7, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_7} AuxVars[] AssignedVars[#pthreadsMutex] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [342] L3800-->my_callbackFINAL: Formula: (and (= |v_Thread0_my_callback_#res.offset_1| 0) (= |v_Thread0_my_callback_#res.base_1| 0)) InVars {} OutVars{Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_1|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_1|} AuxVars[] AssignedVars[Thread0_my_callback_#res.base, Thread0_my_callback_#res.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [343] my_callbackFINAL-->my_callbackEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] JOIN 1 [360] my_callbackEXIT-->L3827-1: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem35_5| v_Thread0_my_callback_thidvar0_4) (= |v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_5| |v_Thread0_my_callback_#res.base_3|) (= |v_Thread0_my_callback_#res.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_5|)) InVars {Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_4, Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_3|, ULTIMATE.start_my_drv_disconnect_#t~mem35=|v_ULTIMATE.start_my_drv_disconnect_#t~mem35_5|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_3|} OutVars{Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_4, Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_3|, ULTIMATE.start_my_drv_disconnect_#t~mem35=|v_ULTIMATE.start_my_drv_disconnect_#t~mem35_5|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_5|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_5|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet36.base, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [349] L3796-->L3796-1: Formula: (let ((.cse0 (select |v_#pthreadsMutex_4| v_Thread1_my_callback_~data~0.base_3))) (and (= (store |v_#pthreadsMutex_4| v_Thread1_my_callback_~data~0.base_3 (store .cse0 v_Thread1_my_callback_~data~0.offset_3 1)) |v_#pthreadsMutex_3|) (= 0 |v_Thread1_my_callback_#t~nondet30_1|) (= (select .cse0 v_Thread1_my_callback_~data~0.offset_3) 0))) InVars {#pthreadsMutex=|v_#pthreadsMutex_4|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_3, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_3} OutVars{#pthreadsMutex=|v_#pthreadsMutex_3|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_3, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_3, Thread1_my_callback_#t~nondet30=|v_Thread1_my_callback_#t~nondet30_1|} AuxVars[] AssignedVars[#pthreadsMutex, Thread1_my_callback_#t~nondet30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [253] L3827-1-->L3827-2: Formula: (and (= (store |v_#memory_int_13| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_int_13| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| (select (select |v_#memory_int_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|))) |v_#memory_int_12|) (= |v_#memory_$Pointer$.offset_9| (store |v_#memory_$Pointer$.offset_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_$Pointer$.offset_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_2|))) (= (store |v_#memory_$Pointer$.base_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_$Pointer$.base_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_2|)) |v_#memory_$Pointer$.base_9|)) InVars {ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_10|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_2|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_2|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_10|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_9|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_2|, #memory_int=|v_#memory_int_12|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_2|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_9|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [261] L3827-2-->L3827-3: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet36.base, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [258] L3827-3-->L3829: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem35=|v_ULTIMATE.start_my_drv_disconnect_#t~mem35_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem35] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [350] L3796-1-->L3797: Formula: true InVars {} OutVars{Thread1_my_callback_#t~nondet30=|v_Thread1_my_callback_#t~nondet30_2|} AuxVars[] AssignedVars[Thread1_my_callback_#t~nondet30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [287] L3829-->L3829-1: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_disconnect_~data.offset_3 40))) (and (= (store |v_#memory_int_15| v_ULTIMATE.start_my_drv_disconnect_~data.base_3 (store (select |v_#memory_int_15| v_ULTIMATE.start_my_drv_disconnect_~data.base_3) .cse0 3)) |v_#memory_int_14|) (= (store |v_#memory_$Pointer$.base_12| v_ULTIMATE.start_my_drv_disconnect_~data.base_3 (store (select |v_#memory_$Pointer$.base_12| v_ULTIMATE.start_my_drv_disconnect_~data.base_3) .cse0 (select (select |v_#memory_$Pointer$.base_11| v_ULTIMATE.start_my_drv_disconnect_~data.base_3) .cse0))) |v_#memory_$Pointer$.base_11|) (= |v_#memory_$Pointer$.offset_11| (store |v_#memory_$Pointer$.offset_12| v_ULTIMATE.start_my_drv_disconnect_~data.base_3 (store (select |v_#memory_$Pointer$.offset_12| v_ULTIMATE.start_my_drv_disconnect_~data.base_3) .cse0 (select (select |v_#memory_$Pointer$.offset_11| v_ULTIMATE.start_my_drv_disconnect_~data.base_3) .cse0)))))) InVars {ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_3, #memory_int=|v_#memory_int_15|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_12|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_12|} OutVars{ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_3, #memory_int=|v_#memory_int_14|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_11|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_11|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [281] L3829-1-->L3830: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_disconnect_~data.offset_4 44))) (and (= (store |v_#memory_$Pointer$.offset_14| v_ULTIMATE.start_my_drv_disconnect_~data.base_4 (store (select |v_#memory_$Pointer$.offset_14| v_ULTIMATE.start_my_drv_disconnect_~data.base_4) .cse0 (select (select |v_#memory_$Pointer$.offset_13| v_ULTIMATE.start_my_drv_disconnect_~data.base_4) .cse0))) |v_#memory_$Pointer$.offset_13|) (= (store |v_#memory_int_17| v_ULTIMATE.start_my_drv_disconnect_~data.base_4 (store (select |v_#memory_int_17| v_ULTIMATE.start_my_drv_disconnect_~data.base_4) .cse0 3)) |v_#memory_int_16|) (= |v_#memory_$Pointer$.base_13| (store |v_#memory_$Pointer$.base_14| v_ULTIMATE.start_my_drv_disconnect_~data.base_4 (store (select |v_#memory_$Pointer$.base_14| v_ULTIMATE.start_my_drv_disconnect_~data.base_4) .cse0 (select (select |v_#memory_$Pointer$.base_13| v_ULTIMATE.start_my_drv_disconnect_~data.base_4) .cse0)))))) InVars {ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_4, #memory_int=|v_#memory_int_17|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_4, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_14|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_14|} OutVars{ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_4, #memory_int=|v_#memory_int_16|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_4, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_13|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_13|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [351] L3797-->L3797-1: Formula: (let ((.cse0 (+ v_Thread1_my_callback_~data~0.offset_4 40))) (and (= |v_#memory_$Pointer$.offset_21| (store |v_#memory_$Pointer$.offset_22| v_Thread1_my_callback_~data~0.base_4 (store (select |v_#memory_$Pointer$.offset_22| v_Thread1_my_callback_~data~0.base_4) .cse0 (select (select |v_#memory_$Pointer$.offset_21| v_Thread1_my_callback_~data~0.base_4) .cse0)))) (= |v_#memory_$Pointer$.base_21| (store |v_#memory_$Pointer$.base_22| v_Thread1_my_callback_~data~0.base_4 (store (select |v_#memory_$Pointer$.base_22| v_Thread1_my_callback_~data~0.base_4) .cse0 (select (select |v_#memory_$Pointer$.base_21| v_Thread1_my_callback_~data~0.base_4) .cse0)))) (= (store |v_#memory_int_32| v_Thread1_my_callback_~data~0.base_4 (store (select |v_#memory_int_32| v_Thread1_my_callback_~data~0.base_4) .cse0 1)) |v_#memory_int_31|))) InVars {#memory_int=|v_#memory_int_32|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_4, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_22|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_22|} OutVars{#memory_int=|v_#memory_int_31|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_4, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_21|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_21|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [250] L3830-->L3831: Formula: (= (select (select |v_#memory_int_18| v_ULTIMATE.start_my_drv_disconnect_~data.base_5) (+ v_ULTIMATE.start_my_drv_disconnect_~data.offset_5 40)) |v_ULTIMATE.start_my_drv_disconnect_#t~mem37_2|) InVars {ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_5, #memory_int=|v_#memory_int_18|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_5} OutVars{ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_5, #memory_int=|v_#memory_int_18|, ULTIMATE.start_my_drv_disconnect_#t~mem37=|v_ULTIMATE.start_my_drv_disconnect_#t~mem37_2|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_5} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem37] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [312] L3831-->L3831-1: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_1| (ite (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem37_3| 3) 1 0)) InVars {ULTIMATE.start_my_drv_disconnect_#t~mem37=|v_ULTIMATE.start_my_drv_disconnect_#t~mem37_3|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem37=|v_ULTIMATE.start_my_drv_disconnect_#t~mem37_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [318] L3831-1-->L3772: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [262] L3772-->L3772-1: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_2 |v_ULTIMATE.start_ldv_assert_#in~expression_2|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_2|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_2|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_2} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [264] L3772-1-->L3772-2: Formula: (= 0 v_ULTIMATE.start_ldv_assert_~expression_3) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_3} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [259] L3772-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 SUMMARY for call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); srcloc: L3774 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3774-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); srcloc: L3774-2 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3774-3 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#t~ret41, main_#t~ret42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_#t~mem46, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_init_#res := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_#t~ret41 := my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_~ret~0 := main_#t~ret41; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#t~ret41; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume 0 == main_~ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_~probe_ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); srcloc: L3850 VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#res; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset, my_drv_probe_~res~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3809 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3809-1 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume -2147483648 <= my_drv_probe_#t~nondet32 && my_drv_probe_#t~nondet32 <= 2147483647; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet32; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet32; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume !(0 != my_drv_probe_~res~0); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3816 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] FORK -1 fork 0 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3817 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] FORK -1 fork 1 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet34; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_#res := 0; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_#t~ret42 := my_drv_probe_#res; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume -2147483648 <= main_#t~ret42 && main_#t~ret42 <= 2147483647; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_~probe_ret~0 := main_#t~ret42; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#t~ret42; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume 0 == main_~probe_ret~0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_disconnect_#t~mem35, my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_#t~mem37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~mem39, my_drv_disconnect_#t~nondet40.base, my_drv_disconnect_#t~nondet40.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); srcloc: L3826 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem35 := read~int(~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3826-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); srcloc: L3796 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 havoc #t~nondet30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3797 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call #t~mem31 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3797-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#t~mem31|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call write~int(1 + #t~mem31, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3798 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#t~mem31|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 havoc #t~mem31; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 #pthreadsMutex := #pthreadsMutex[~data~0.base,~data~0.offset := 0]; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 assume true; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] JOIN 1 join my_drv_disconnect_#t~mem35 assign my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 SUMMARY for call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); srcloc: L3796 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3827-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_disconnect_#t~mem35; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 havoc #t~nondet30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(3, my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); srcloc: L3829 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(3, my_drv_disconnect_~data.base, 44 + my_drv_disconnect_~data.offset, 4); srcloc: L3829-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3797 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem37 := read~int(my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); srcloc: L3830 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 ldv_assert_#in~expression := (if 3 == my_drv_disconnect_#t~mem37 then 1 else 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume 0 == ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume !false; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 SUMMARY for call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); srcloc: L3774 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3774-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); srcloc: L3774-2 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3774-3 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#t~ret41, main_#t~ret42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_#t~mem46, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_init_#res := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_#t~ret41 := my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_~ret~0 := main_#t~ret41; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#t~ret41; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume 0 == main_~ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_~probe_ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); srcloc: L3850 VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#res; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset, my_drv_probe_~res~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3809 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3809-1 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume -2147483648 <= my_drv_probe_#t~nondet32 && my_drv_probe_#t~nondet32 <= 2147483647; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet32; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet32; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume !(0 != my_drv_probe_~res~0); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3816 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] FORK -1 fork 0 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3817 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] FORK -1 fork 1 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet34; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_#res := 0; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_#t~ret42 := my_drv_probe_#res; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume -2147483648 <= main_#t~ret42 && main_#t~ret42 <= 2147483647; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_~probe_ret~0 := main_#t~ret42; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#t~ret42; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume 0 == main_~probe_ret~0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_disconnect_#t~mem35, my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_#t~mem37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~mem39, my_drv_disconnect_#t~nondet40.base, my_drv_disconnect_#t~nondet40.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); srcloc: L3826 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem35 := read~int(~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3826-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); srcloc: L3796 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 havoc #t~nondet30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3797 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call #t~mem31 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3797-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#t~mem31|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call write~int(1 + #t~mem31, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3798 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#t~mem31|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 havoc #t~mem31; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 #pthreadsMutex := #pthreadsMutex[~data~0.base,~data~0.offset := 0]; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 assume true; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] JOIN 1 join my_drv_disconnect_#t~mem35 assign my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 SUMMARY for call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); srcloc: L3796 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3827-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_disconnect_#t~mem35; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 havoc #t~nondet30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(3, my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); srcloc: L3829 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(3, my_drv_disconnect_~data.base, 44 + my_drv_disconnect_~data.offset, 4); srcloc: L3829-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3797 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem37 := read~int(my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); srcloc: L3830 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 ldv_assert_#in~expression := (if 3 == my_drv_disconnect_#t~mem37 then 1 else 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume 0 == ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume !false; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L3774] -1 call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3774] -1 call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [?] -1 havoc main_#t~ret41, main_#t~ret42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_#t~mem46, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL.base=0, #NULL.offset=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 main_#t~ret41 := my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 main_~ret~0 := main_#t~ret41; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret41=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 havoc main_#t~ret41; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3848-L3862] -1 assume 0 == main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3850] -1 call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3851] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3851] -1 havoc my_drv_probe_#t~nondet32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset, my_drv_probe_~res~0; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3803-L3823] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3804] -1 my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3808] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3809] -1 call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3810] -1 call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3812] -1 assume -2147483648 <= my_drv_probe_#t~nondet32 && my_drv_probe_#t~nondet32 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3812] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet32; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3812] -1 havoc my_drv_probe_#t~nondet32; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3813-L3814] -1 assume !(0 != my_drv_probe_~res~0); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3816] -1 call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3816] FORK -1 fork 0 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3816] -1 havoc my_drv_probe_#t~nondet33; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3817] -1 call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3817] FORK -1 fork 1 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3817] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3818] -1 my_drv_probe_#res := 0; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3791-L3801] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40] [L3792] 0 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3793] 0 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3791-L3801] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3792] 1 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 0 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3793] 1 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 1 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 main_#t~ret42 := my_drv_probe_#res; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_#t~ret42=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret42 && main_#t~ret42 <= 2147483647; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_#t~ret42=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret42; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_#t~ret42=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 havoc main_#t~ret42; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3852-L3856] -1 assume 0 == main_~probe_ret~0; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3853] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem35, my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_#t~mem37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~mem39, my_drv_disconnect_#t~nondet40.base, my_drv_disconnect_#t~nondet40.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3825-L3836] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3826] -1 call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 call my_drv_disconnect_#t~mem35 := read~int(~#t1~0.base, ~#t1~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 1 call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 1 havoc #t~nondet30; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3797] 1 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3798] 1 call #t~mem31 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #t~mem31=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3798] 1 call write~int(1 + #t~mem31, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #t~mem31=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3798] 1 havoc #t~mem31; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3799] 1 #pthreadsMutex := #pthreadsMutex[~data~0.base,~data~0.offset := 0]; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3800] 1 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3791-L3801] 1 ensures true; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] JOIN 1 join my_drv_disconnect_#t~mem35 assign my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36.base=0, my_drv_disconnect_#t~nondet36.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 0 call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36.base=0, my_drv_disconnect_#t~nondet36.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36.base=0, my_drv_disconnect_#t~nondet36.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 havoc my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 havoc my_drv_disconnect_#t~mem35; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 0 havoc #t~nondet30; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3829] -1 call write~int(3, my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3830] -1 call write~int(3, my_drv_disconnect_~data.base, 44 + my_drv_disconnect_~data.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3797] 0 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3831] -1 call my_drv_disconnect_#t~mem37 := read~int(my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3831] -1 ldv_assert_#in~expression := (if 3 == my_drv_disconnect_#t~mem37 then 1 else 0); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3831] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3772] -1 assume 0 == ldv_assert_~expression; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3772] -1 assert false; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L3774] -1 call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3774] -1 call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [?] -1 havoc main_#t~ret41, main_#t~ret42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_#t~mem46, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL.base=0, #NULL.offset=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 main_#t~ret41 := my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 main_~ret~0 := main_#t~ret41; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret41=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 havoc main_#t~ret41; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3848-L3862] -1 assume 0 == main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3850] -1 call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3851] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3851] -1 havoc my_drv_probe_#t~nondet32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset, my_drv_probe_~res~0; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3803-L3823] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3804] -1 my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3808] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3809] -1 call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3810] -1 call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3812] -1 assume -2147483648 <= my_drv_probe_#t~nondet32 && my_drv_probe_#t~nondet32 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3812] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet32; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3812] -1 havoc my_drv_probe_#t~nondet32; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3813-L3814] -1 assume !(0 != my_drv_probe_~res~0); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3816] -1 call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3816] FORK -1 fork 0 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3816] -1 havoc my_drv_probe_#t~nondet33; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3817] -1 call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3817] FORK -1 fork 1 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3817] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3818] -1 my_drv_probe_#res := 0; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3791-L3801] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40] [L3792] 0 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3793] 0 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3791-L3801] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3792] 1 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 0 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3793] 1 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 1 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 main_#t~ret42 := my_drv_probe_#res; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_#t~ret42=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret42 && main_#t~ret42 <= 2147483647; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_#t~ret42=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret42; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_#t~ret42=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 havoc main_#t~ret42; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3852-L3856] -1 assume 0 == main_~probe_ret~0; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3853] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem35, my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_#t~mem37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~mem39, my_drv_disconnect_#t~nondet40.base, my_drv_disconnect_#t~nondet40.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3825-L3836] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3826] -1 call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 call my_drv_disconnect_#t~mem35 := read~int(~#t1~0.base, ~#t1~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 1 call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 1 havoc #t~nondet30; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3797] 1 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3798] 1 call #t~mem31 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #t~mem31=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3798] 1 call write~int(1 + #t~mem31, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #t~mem31=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3798] 1 havoc #t~mem31; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3799] 1 #pthreadsMutex := #pthreadsMutex[~data~0.base,~data~0.offset := 0]; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3800] 1 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3791-L3801] 1 ensures true; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] JOIN 1 join my_drv_disconnect_#t~mem35 assign my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36.base=0, my_drv_disconnect_#t~nondet36.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 0 call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36.base=0, my_drv_disconnect_#t~nondet36.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36.base=0, my_drv_disconnect_#t~nondet36.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 havoc my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 havoc my_drv_disconnect_#t~mem35; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 0 havoc #t~nondet30; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3829] -1 call write~int(3, my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3830] -1 call write~int(3, my_drv_disconnect_~data.base, 44 + my_drv_disconnect_~data.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3797] 0 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3831] -1 call my_drv_disconnect_#t~mem37 := read~int(my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3831] -1 ldv_assert_#in~expression := (if 3 == my_drv_disconnect_#t~mem37 then 1 else 0); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3831] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3772] -1 assume 0 == ldv_assert_~expression; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3772] -1 assert false; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [?] -1 havoc main_#t~ret41, main_#t~ret42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_#t~mem46, main_~probe_ret~0, main_~#data~1, main_~ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL!base=0, #NULL!offset=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 main_#t~ret41 := my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 main_~ret~0 := main_#t~ret41; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret41=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 havoc main_#t~ret41; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3848] COND TRUE -1 0 == main_~ret~0 VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3850] FCALL -1 call main_~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3851] -1 my_drv_probe_#in~data := main_~#data~1; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3851] -1 havoc my_drv_probe_#t~nondet32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_~data, my_drv_probe_~d~0, my_drv_probe_~res~0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3803-L3823] -1 my_drv_probe_~data := my_drv_probe_#in~data; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3804] -1 my_drv_probe_~d~0 := { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: my_drv_probe_~data!base, offset: my_drv_probe_~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 assume -2147483648 <= my_drv_probe_#t~nondet32 && my_drv_probe_#t~nondet32 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 havoc my_drv_probe_#t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3813-L3814] COND FALSE -1 !(0 != my_drv_probe_~res~0) VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FORK -1 fork 0 my_callback(my_drv_probe_~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] -1 havoc my_drv_probe_#t~nondet33; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FORK -1 fork 1 my_callback(my_drv_probe_~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3818] -1 my_drv_probe_#res := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3791-L3801] 0 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40] [L3792] 0 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 0 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3791-L3801] 1 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3792] 1 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 1 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 main_#t~ret42 := my_drv_probe_#res; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_#t~ret42=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret42 && main_#t~ret42 <= 2147483647; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_#t~ret42=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_#t~ret42=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 havoc main_#t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3852] COND TRUE -1 0 == main_~probe_ret~0 VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3853] -1 my_drv_disconnect_#in~data := main_~#data~1; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem35, my_drv_disconnect_#t~nondet36, my_drv_disconnect_#t~mem37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~mem39, my_drv_disconnect_#t~nondet40, my_drv_disconnect_~data, my_drv_disconnect_~#status~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3825-L3836] -1 my_drv_disconnect_~data := my_drv_disconnect_#in~data; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3826] FCALL -1 call my_drv_disconnect_~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call my_drv_disconnect_#t~mem35 := read~int(~#t1~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 1 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 1 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call #t~mem31 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call write~int(1 + #t~mem31, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] 1 havoc #t~mem31; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3799] 1 #pthreadsMutex[{ base: ~data~0!base, offset: ~data~0!offset }] := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3800] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] JOIN 1 join my_drv_disconnect_#t~mem35 assign my_drv_disconnect_#t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36!base=0, my_drv_disconnect_#t~nondet36!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 0 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36!base=0, my_drv_disconnect_#t~nondet36!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet36, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36!base=0, my_drv_disconnect_#t~nondet36!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc my_drv_disconnect_#t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc my_drv_disconnect_#t~mem35; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 0 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3829] FCALL -1 call write~int(3, { base: my_drv_disconnect_~data!base, offset: 40 + my_drv_disconnect_~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3830] FCALL -1 call write~int(3, { base: my_drv_disconnect_~data!base, offset: 44 + my_drv_disconnect_~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] FCALL -1 call my_drv_disconnect_#t~mem37 := read~int({ base: my_drv_disconnect_~data!base, offset: 40 + my_drv_disconnect_~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] -1 ldv_assert_#in~expression := (if 3 == my_drv_disconnect_#t~mem37 then 1 else 0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] COND TRUE -1 0 == ldv_assert_~expression VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [?] -1 havoc main_#t~ret41, main_#t~ret42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_#t~mem46, main_~probe_ret~0, main_~#data~1, main_~ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL!base=0, #NULL!offset=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 main_#t~ret41 := my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 main_~ret~0 := main_#t~ret41; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret41=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 havoc main_#t~ret41; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3848] COND TRUE -1 0 == main_~ret~0 VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3850] FCALL -1 call main_~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3851] -1 my_drv_probe_#in~data := main_~#data~1; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3851] -1 havoc my_drv_probe_#t~nondet32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_~data, my_drv_probe_~d~0, my_drv_probe_~res~0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3803-L3823] -1 my_drv_probe_~data := my_drv_probe_#in~data; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3804] -1 my_drv_probe_~d~0 := { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: my_drv_probe_~data!base, offset: my_drv_probe_~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 assume -2147483648 <= my_drv_probe_#t~nondet32 && my_drv_probe_#t~nondet32 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 havoc my_drv_probe_#t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3813-L3814] COND FALSE -1 !(0 != my_drv_probe_~res~0) VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FORK -1 fork 0 my_callback(my_drv_probe_~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] -1 havoc my_drv_probe_#t~nondet33; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FORK -1 fork 1 my_callback(my_drv_probe_~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3818] -1 my_drv_probe_#res := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3791-L3801] 0 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40] [L3792] 0 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 0 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3791-L3801] 1 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3792] 1 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 1 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 main_#t~ret42 := my_drv_probe_#res; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_#t~ret42=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret42 && main_#t~ret42 <= 2147483647; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_#t~ret42=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_#t~ret42=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 havoc main_#t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3852] COND TRUE -1 0 == main_~probe_ret~0 VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3853] -1 my_drv_disconnect_#in~data := main_~#data~1; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem35, my_drv_disconnect_#t~nondet36, my_drv_disconnect_#t~mem37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~mem39, my_drv_disconnect_#t~nondet40, my_drv_disconnect_~data, my_drv_disconnect_~#status~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3825-L3836] -1 my_drv_disconnect_~data := my_drv_disconnect_#in~data; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3826] FCALL -1 call my_drv_disconnect_~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call my_drv_disconnect_#t~mem35 := read~int(~#t1~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 1 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 1 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call #t~mem31 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call write~int(1 + #t~mem31, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] 1 havoc #t~mem31; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3799] 1 #pthreadsMutex[{ base: ~data~0!base, offset: ~data~0!offset }] := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3800] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] JOIN 1 join my_drv_disconnect_#t~mem35 assign my_drv_disconnect_#t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36!base=0, my_drv_disconnect_#t~nondet36!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 0 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36!base=0, my_drv_disconnect_#t~nondet36!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet36, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36!base=0, my_drv_disconnect_#t~nondet36!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc my_drv_disconnect_#t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc my_drv_disconnect_#t~mem35; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 0 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3829] FCALL -1 call write~int(3, { base: my_drv_disconnect_~data!base, offset: 40 + my_drv_disconnect_~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3830] FCALL -1 call write~int(3, { base: my_drv_disconnect_~data!base, offset: 44 + my_drv_disconnect_~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] FCALL -1 call my_drv_disconnect_#t~mem37 := read~int({ base: my_drv_disconnect_~data!base, offset: 40 + my_drv_disconnect_~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] -1 ldv_assert_#in~expression := (if 3 == my_drv_disconnect_#t~mem37 then 1 else 0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] COND TRUE -1 0 == ldv_assert_~expression VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3839] -1 #res := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 assume -2147483648 <= #t~ret41 && #t~ret41 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 ~ret~0 := #t~ret41; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 havoc #t~ret41; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3848] COND TRUE -1 0 == ~ret~0 VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3849] -1 havoc ~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3850] FCALL -1 call ~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3803-L3823] -1 ~data := #in~data; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3804] -1 ~d~0 := { base: ~data!base, offset: 40 + ~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: ~data!base, offset: ~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 assume -2147483648 <= #t~nondet32 && #t~nondet32 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 ~res~0 := #t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 havoc #t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3813-L3814] COND FALSE -1 !(0 != ~res~0) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FORK -1 fork 0 my_callback(~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] -1 havoc #t~nondet33; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FORK -1 fork 1 my_callback(~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] -1 havoc #t~nondet34; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3818] -1 #res := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3791-L3801] 0 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40] [L3792] 0 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 0 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3791-L3801] 1 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3792] 1 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 1 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 assume -2147483648 <= #t~ret42 && #t~ret42 <= 2147483647; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 ~probe_ret~0 := #t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 havoc #t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3852] COND TRUE -1 0 == ~probe_ret~0 VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3825-L3836] -1 ~data := #in~data; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3826] FCALL -1 call ~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call #t~mem35 := read~int(~#t1~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 1 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 1 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call #t~mem31 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call write~int(1 + #t~mem31, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] 1 havoc #t~mem31; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3799] 1 #pthreadsMutex[{ base: ~data~0!base, offset: ~data~0!offset }] := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3800] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] JOIN 1 join #t~mem35 assign #t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 0 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call write~$Pointer$(#t~nondet36, ~#status~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc #t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc #t~mem35; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 0 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3829] FCALL -1 call write~int(3, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3830] FCALL -1 call write~int(3, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] FCALL -1 call #t~mem37 := read~int({ base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] COND TRUE -1 0 == ~expression VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3839] -1 #res := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 assume -2147483648 <= #t~ret41 && #t~ret41 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 ~ret~0 := #t~ret41; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 havoc #t~ret41; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3848] COND TRUE -1 0 == ~ret~0 VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3849] -1 havoc ~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3850] FCALL -1 call ~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3803-L3823] -1 ~data := #in~data; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3804] -1 ~d~0 := { base: ~data!base, offset: 40 + ~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: ~data!base, offset: ~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 assume -2147483648 <= #t~nondet32 && #t~nondet32 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 ~res~0 := #t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 havoc #t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3813-L3814] COND FALSE -1 !(0 != ~res~0) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FORK -1 fork 0 my_callback(~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] -1 havoc #t~nondet33; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FORK -1 fork 1 my_callback(~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] -1 havoc #t~nondet34; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3818] -1 #res := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3791-L3801] 0 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40] [L3792] 0 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 0 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3791-L3801] 1 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3792] 1 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 1 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 assume -2147483648 <= #t~ret42 && #t~ret42 <= 2147483647; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 ~probe_ret~0 := #t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 havoc #t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3852] COND TRUE -1 0 == ~probe_ret~0 VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3825-L3836] -1 ~data := #in~data; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3826] FCALL -1 call ~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call #t~mem35 := read~int(~#t1~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 1 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 1 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call #t~mem31 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call write~int(1 + #t~mem31, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] 1 havoc #t~mem31; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3799] 1 #pthreadsMutex[{ base: ~data~0!base, offset: ~data~0!offset }] := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3800] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] JOIN 1 join #t~mem35 assign #t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 0 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call write~$Pointer$(#t~nondet36, ~#status~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc #t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc #t~mem35; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 0 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3829] FCALL -1 call write~int(3, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3830] FCALL -1 call write~int(3, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] FCALL -1 call #t~mem37 := read~int({ base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] COND TRUE -1 0 == ~expression VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3774] -1 pthread_t t1,t2; VAL [t1={69:0}, t2={58:0}] [L3839] -1 return 0; VAL [t1={69:0}, t2={58:0}] [L3847] -1 int ret = my_drv_init(); VAL [t1={69:0}, t2={58:0}] [L3848] COND TRUE -1 ret==0 VAL [t1={69:0}, t2={58:0}] [L3849] -1 int probe_ret; VAL [t1={69:0}, t2={58:0}] [L3850] -1 struct my_data data; VAL [t1={69:0}, t2={58:0}] [L3804] -1 struct device *d = &data->dev; VAL [t1={69:0}, t2={58:0}] [L3809] -1 data->shared.a = 0 VAL [t1={69:0}, t2={58:0}] [L3810] -1 data->shared.b = 0 VAL [t1={69:0}, t2={58:0}] [L3812] -1 int res = __VERIFIER_nondet_int(); VAL [t1={69:0}, t2={58:0}] [L3813] COND FALSE -1 !(\read(res)) VAL [t1={69:0}, t2={58:0}] [L3816] FCALL, FORK -1 pthread_create(&t1, ((void *)0), my_callback, (void *)d) VAL [arg={63:40}, t1={69:0}, t2={58:0}] [L3817] FCALL, FORK -1 pthread_create(&t2, ((void *)0), my_callback, (void *)d) VAL [arg={63:40}, t1={69:0}, t2={58:0}] [L3818] -1 return 0; VAL [arg={63:40}, t1={69:0}, t2={58:0}] [L3792] 0 struct device *dev = (struct device*)arg; VAL [arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3793] 0 struct my_data *data; VAL [arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3792] 1 struct device *dev = (struct device*)arg; VAL [arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3794] 0 const typeof( ((struct my_data *)0)->dev ) *__mptr = (dev); VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3793] 1 struct my_data *data; VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3794] 0 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3794] 1 const typeof( ((struct my_data *)0)->dev ) *__mptr = (dev); VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3851] -1 probe_ret = my_drv_probe(&data) VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3852] COND TRUE -1 probe_ret==0 VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3826] -1 void *status; VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3827] -1 \read(t1) VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3794] 1 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3797] 1 data->shared.a = 1 VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3798] EXPR 1 data->shared.b VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, data->shared.b=0, dev={63:40}, t1={69:0}, t2={58:0}] [L3798] 1 data->shared.b = data->shared.b + 1 VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, data->shared.b=0, dev={63:40}, t1={69:0}, t2={58:0}] [L3800] 1 return 0; VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3827] FCALL, JOIN 1 pthread_join(t1, &status) VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3829] -1 data->shared.a = 3 VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3830] -1 data->shared.b = 3 VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3797] 0 data->shared.a = 1 VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3831] -1 data->shared.a VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3772] COND TRUE -1 !expression VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3772] -1 __VERIFIER_error() VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] ----- [2018-11-23 03:43:06,046 INFO L305 ceAbstractionStarter]: Did not count any witness invariants because Icfg is not BoogieIcfg [2018-11-23 03:43:06,048 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 03:43:06 BasicIcfg [2018-11-23 03:43:06,048 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 03:43:06,048 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 03:43:06,048 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 03:43:06,049 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 03:43:06,049 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 03:42:49" (3/4) ... [2018-11-23 03:43:06,052 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [295] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [205] L-1-->L3774: Formula: (= |v_#valid_1| (store |v_#valid_2| 0 0)) InVars {#valid=|v_#valid_2|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [282] L3774-->L3774-1: Formula: (and (= (select |v_#valid_4| |v_~#t1~0.base_1|) 0) (not (= |v_~#t1~0.base_1| 0)) (= 0 |v_~#t1~0.offset_1|) (= |v_#length_1| (store |v_#length_2| |v_~#t1~0.base_1| 4)) (= (store |v_#valid_4| |v_~#t1~0.base_1| 1) |v_#valid_3|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_4|} OutVars{~#t1~0.offset=|v_~#t1~0.offset_1|, #length=|v_#length_1|, ~#t1~0.base=|v_~#t1~0.base_1|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[~#t1~0.base, #valid, ~#t1~0.offset, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 [276] L3774-1-->L3774-2: Formula: (= 0 (select (select |v_#memory_int_1| |v_~#t1~0.base_2|) |v_~#t1~0.offset_2|)) InVars {#memory_int=|v_#memory_int_1|, ~#t1~0.offset=|v_~#t1~0.offset_2|, ~#t1~0.base=|v_~#t1~0.base_2|} OutVars{#memory_int=|v_#memory_int_1|, ~#t1~0.offset=|v_~#t1~0.offset_2|, ~#t1~0.base=|v_~#t1~0.base_2|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 [284] L3774-2-->L3774-3: Formula: (and (= 0 (select |v_#valid_6| |v_~#t2~0.base_1|)) (= (store |v_#length_4| |v_~#t2~0.base_1| 4) |v_#length_3|) (not (= 0 |v_~#t2~0.base_1|)) (= 0 |v_~#t2~0.offset_1|) (= |v_#valid_5| (store |v_#valid_6| |v_~#t2~0.base_1| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_6|} OutVars{#length=|v_#length_3|, ~#t2~0.base=|v_~#t2~0.base_1|, ~#t2~0.offset=|v_~#t2~0.offset_1|, #valid=|v_#valid_5|} AuxVars[] AssignedVars[~#t2~0.offset, #valid, #length, ~#t2~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [286] L3774-3-->L3774-4: Formula: (= (select (select |v_#memory_int_2| |v_~#t2~0.base_2|) |v_~#t2~0.offset_2|) 0) InVars {#memory_int=|v_#memory_int_2|, ~#t2~0.base=|v_~#t2~0.base_2|, ~#t2~0.offset=|v_~#t2~0.offset_2|} OutVars{#memory_int=|v_#memory_int_2|, ~#t2~0.base=|v_~#t2~0.base_2|, ~#t2~0.offset=|v_~#t2~0.offset_2|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [283] L3774-4-->L-1-1: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [315] L-1-1-->L3847: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~mem45=|v_ULTIMATE.start_main_#t~mem45_1|, ULTIMATE.start_main_#t~mem46=|v_ULTIMATE.start_main_#t~mem46_1|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_1|, ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_1, ULTIMATE.start_main_#t~mem44=|v_ULTIMATE.start_main_#t~mem44_1|, ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_1|, ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_1|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_1|, ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_1, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem45, ULTIMATE.start_main_#t~mem46, ULTIMATE.start_main_#t~mem43, ULTIMATE.start_main_~ret~0, ULTIMATE.start_main_#t~mem44, ULTIMATE.start_main_#t~ret41, ULTIMATE.start_main_#t~ret42, ULTIMATE.start_main_~#data~1.offset, ULTIMATE.start_main_~probe_ret~0, ULTIMATE.start_main_~#data~1.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [207] L3847-->L3839: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_init_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [198] L3839-->L3839-1: Formula: (= |v_ULTIMATE.start_my_drv_init_#res_2| 0) InVars {} OutVars{ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_init_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [328] L3839-1-->L3847-1: Formula: (= |v_ULTIMATE.start_main_#t~ret41_2| |v_ULTIMATE.start_my_drv_init_#res_3|) InVars {ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_3|} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_2|, ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret41] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [218] L3847-1-->L3847-2: Formula: (and (<= |v_ULTIMATE.start_main_#t~ret41_3| 2147483647) (<= 0 (+ |v_ULTIMATE.start_main_#t~ret41_3| 2147483648))) InVars {ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_3|} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_3|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [212] L3847-2-->L3847-3: Formula: (= v_ULTIMATE.start_main_~ret~0_2 |v_ULTIMATE.start_main_#t~ret41_4|) InVars {ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_4|} OutVars{ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_2, ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_~ret~0] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [195] L3847-3-->L3848: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret41] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [292] L3848-->L3849: Formula: (= v_ULTIMATE.start_main_~ret~0_3 0) InVars {ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_3} OutVars{ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_3} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [254] L3849-->L3850: Formula: true InVars {} OutVars{ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_~probe_ret~0] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [199] L3850-->L3850-1: Formula: (and (= 0 |v_ULTIMATE.start_main_~#data~1.offset_2|) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#data~1.base_2|) 0) (not (= |v_ULTIMATE.start_main_~#data~1.base_2| 0)) (= (store |v_#length_6| |v_ULTIMATE.start_main_~#data~1.base_2| 48) |v_#length_5|) (= (store |v_#valid_8| |v_ULTIMATE.start_main_~#data~1.base_2| 1) |v_#valid_7|)) InVars {#length=|v_#length_6|, #valid=|v_#valid_8|} OutVars{ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_2|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[#valid, ULTIMATE.start_main_~#data~1.offset, #length, ULTIMATE.start_main_~#data~1.base] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [324] L3850-1-->L3851: Formula: (and (= |v_ULTIMATE.start_my_drv_probe_#in~data.base_1| |v_ULTIMATE.start_main_~#data~1.base_3|) (= |v_ULTIMATE.start_my_drv_probe_#in~data.offset_1| |v_ULTIMATE.start_main_~#data~1.offset_3|)) InVars {ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_3|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_3|} OutVars{ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_1|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_3|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_3|, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#in~data.base, ULTIMATE.start_my_drv_probe_#in~data.offset] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [291] L3851-->L3851-1: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#res] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [290] L3851-1-->L3803: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_~d~0.offset=v_ULTIMATE.start_my_drv_probe_~d~0.offset_1, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_1, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_1, ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_1|, ULTIMATE.start_my_drv_probe_#t~nondet32=|v_ULTIMATE.start_my_drv_probe_#t~nondet32_1|, ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_1, ULTIMATE.start_my_drv_probe_#t~nondet34=|v_ULTIMATE.start_my_drv_probe_#t~nondet34_1|, ULTIMATE.start_my_drv_probe_~d~0.base=v_ULTIMATE.start_my_drv_probe_~d~0.base_1} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~d~0.offset, ULTIMATE.start_my_drv_probe_~data.base, ULTIMATE.start_my_drv_probe_~data.offset, ULTIMATE.start_my_drv_probe_#t~nondet33, ULTIMATE.start_my_drv_probe_#t~nondet32, ULTIMATE.start_my_drv_probe_~res~0, ULTIMATE.start_my_drv_probe_#t~nondet34, ULTIMATE.start_my_drv_probe_~d~0.base] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [219] L3803-->L3804: Formula: (and (= v_ULTIMATE.start_my_drv_probe_~data.offset_2 |v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|) (= v_ULTIMATE.start_my_drv_probe_~data.base_2 |v_ULTIMATE.start_my_drv_probe_#in~data.base_2|)) InVars {ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_2|, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|} OutVars{ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_2, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_2, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~data.base, ULTIMATE.start_my_drv_probe_~data.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [299] L3804-->L3808: Formula: (and (= v_ULTIMATE.start_my_drv_probe_~d~0.base_2 v_ULTIMATE.start_my_drv_probe_~data.base_3) (= v_ULTIMATE.start_my_drv_probe_~d~0.offset_2 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_3 40))) InVars {ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_3, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_3} OutVars{ULTIMATE.start_my_drv_probe_~d~0.offset=v_ULTIMATE.start_my_drv_probe_~d~0.offset_2, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_3, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_3, ULTIMATE.start_my_drv_probe_~d~0.base=v_ULTIMATE.start_my_drv_probe_~d~0.base_2} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~d~0.offset, ULTIMATE.start_my_drv_probe_~d~0.base] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [242] L3808-->L3809: Formula: (= |v_#pthreadsMutex_1| (store |v_#pthreadsMutex_2| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#pthreadsMutex_2| v_ULTIMATE.start_my_drv_probe_~data.base_4) v_ULTIMATE.start_my_drv_probe_~data.offset_4 0))) InVars {#pthreadsMutex=|v_#pthreadsMutex_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_4, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_4} OutVars{#pthreadsMutex=|v_#pthreadsMutex_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_4, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_4} AuxVars[] AssignedVars[#pthreadsMutex] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [316] L3809-->L3809-1: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_5 40))) (and (= (store |v_#memory_int_4| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_int_4| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 0)) |v_#memory_int_3|) (= |v_#memory_$Pointer$.base_1| (store |v_#memory_$Pointer$.base_2| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_$Pointer$.base_2| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_1| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0)))) (= |v_#memory_$Pointer$.offset_1| (store |v_#memory_$Pointer$.offset_2| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_$Pointer$.offset_2| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_1| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0)))))) InVars {#memory_int=|v_#memory_int_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_5, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_2|} OutVars{#memory_int=|v_#memory_int_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_5, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_1|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [314] L3809-1-->L3810: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_6 44))) (and (= (store |v_#memory_$Pointer$.base_4| v_ULTIMATE.start_my_drv_probe_~data.base_6 (store (select |v_#memory_$Pointer$.base_4| v_ULTIMATE.start_my_drv_probe_~data.base_6) .cse0 (select (select |v_#memory_$Pointer$.base_3| v_ULTIMATE.start_my_drv_probe_~data.base_6) .cse0))) |v_#memory_$Pointer$.base_3|) (= |v_#memory_$Pointer$.offset_3| (store |v_#memory_$Pointer$.offset_4| v_ULTIMATE.start_my_drv_probe_~data.base_6 (store (select |v_#memory_$Pointer$.offset_4| v_ULTIMATE.start_my_drv_probe_~data.base_6) .cse0 (select (select |v_#memory_$Pointer$.offset_3| v_ULTIMATE.start_my_drv_probe_~data.base_6) .cse0)))) (= (store |v_#memory_int_6| v_ULTIMATE.start_my_drv_probe_~data.base_6 (store (select |v_#memory_int_6| v_ULTIMATE.start_my_drv_probe_~data.base_6) .cse0 0)) |v_#memory_int_5|))) InVars {#memory_int=|v_#memory_int_6|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_4|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_6, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_6, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_4|} OutVars{#memory_int=|v_#memory_int_5|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_3|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_6, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_6, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_3|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [271] L3810-->L3812: Formula: (and (<= |v_ULTIMATE.start_my_drv_probe_#t~nondet32_2| 2147483647) (<= 0 (+ |v_ULTIMATE.start_my_drv_probe_#t~nondet32_2| 2147483648))) InVars {ULTIMATE.start_my_drv_probe_#t~nondet32=|v_ULTIMATE.start_my_drv_probe_#t~nondet32_2|} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet32=|v_ULTIMATE.start_my_drv_probe_#t~nondet32_2|} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [305] L3812-->L3812-1: Formula: (= v_ULTIMATE.start_my_drv_probe_~res~0_2 |v_ULTIMATE.start_my_drv_probe_#t~nondet32_3|) InVars {ULTIMATE.start_my_drv_probe_#t~nondet32=|v_ULTIMATE.start_my_drv_probe_#t~nondet32_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet32=|v_ULTIMATE.start_my_drv_probe_#t~nondet32_3|, ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_2} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~res~0] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [307] L3812-1-->L3813: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet32=|v_ULTIMATE.start_my_drv_probe_#t~nondet32_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet32] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [268] L3813-->L3816: Formula: (= v_ULTIMATE.start_my_drv_probe_~res~0_4 0) InVars {ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_4} OutVars{ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_4} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [251] L3816-->L3816-1: Formula: (and (= |v_#memory_$Pointer$.offset_5| (store |v_#memory_$Pointer$.offset_6| |v_~#t1~0.base_3| (store (select |v_#memory_$Pointer$.offset_6| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| (select (select |v_#memory_$Pointer$.offset_5| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3|)))) (= |v_#memory_int_7| (store |v_#memory_int_8| |v_~#t1~0.base_3| (store (select |v_#memory_int_8| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| 0))) (= (store |v_#memory_$Pointer$.base_6| |v_~#t1~0.base_3| (store (select |v_#memory_$Pointer$.base_6| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| (select (select |v_#memory_$Pointer$.base_5| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3|))) |v_#memory_$Pointer$.base_5|)) InVars {#memory_int=|v_#memory_int_8|, ~#t1~0.offset=|v_~#t1~0.offset_3|, ~#t1~0.base=|v_~#t1~0.base_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_6|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_6|} OutVars{#memory_int=|v_#memory_int_7|, ~#t1~0.offset=|v_~#t1~0.offset_3|, ~#t1~0.base=|v_~#t1~0.base_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_5|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_5|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] FORK -1 [358] L3816-1-->my_callbackENTRY: Formula: (and (= v_ULTIMATE.start_my_drv_probe_~d~0.base_4 |v_Thread0_my_callback_#in~arg.base_3|) (= v_ULTIMATE.start_my_drv_probe_~d~0.offset_4 |v_Thread0_my_callback_#in~arg.offset_3|) (= v_Thread0_my_callback_thidvar0_2 0)) InVars {ULTIMATE.start_my_drv_probe_~d~0.offset=v_ULTIMATE.start_my_drv_probe_~d~0.offset_4, ULTIMATE.start_my_drv_probe_~d~0.base=v_ULTIMATE.start_my_drv_probe_~d~0.base_4} OutVars{ULTIMATE.start_my_drv_probe_~d~0.offset=v_ULTIMATE.start_my_drv_probe_~d~0.offset_4, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_3|, Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_2, Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_3|, ULTIMATE.start_my_drv_probe_~d~0.base=v_ULTIMATE.start_my_drv_probe_~d~0.base_4} AuxVars[] AssignedVars[Thread0_my_callback_#in~arg.base, Thread0_my_callback_thidvar0, Thread0_my_callback_#in~arg.offset] VAL [Thread0_my_callback_thidvar0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [263] L3816-2-->L3817: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet33] VAL [Thread0_my_callback_thidvar0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [325] L3817-->L3817-1: Formula: (and (= (store |v_#memory_$Pointer$.base_8| |v_~#t2~0.base_3| (store (select |v_#memory_$Pointer$.base_8| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| (select (select |v_#memory_$Pointer$.base_7| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3|))) |v_#memory_$Pointer$.base_7|) (= (store |v_#memory_$Pointer$.offset_8| |v_~#t2~0.base_3| (store (select |v_#memory_$Pointer$.offset_8| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| (select (select |v_#memory_$Pointer$.offset_7| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3|))) |v_#memory_$Pointer$.offset_7|) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_~#t2~0.base_3| (store (select |v_#memory_int_10| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| 1)))) InVars {#memory_int=|v_#memory_int_10|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_8|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_8|, ~#t2~0.base=|v_~#t2~0.base_3|, ~#t2~0.offset=|v_~#t2~0.offset_3|} OutVars{#memory_int=|v_#memory_int_9|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_7|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_7|, ~#t2~0.base=|v_~#t2~0.base_3|, ~#t2~0.offset=|v_~#t2~0.offset_3|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] FORK -1 [359] L3817-1-->my_callbackENTRY: Formula: (and (= v_ULTIMATE.start_my_drv_probe_~d~0.base_6 |v_Thread1_my_callback_#in~arg.base_3|) (= v_ULTIMATE.start_my_drv_probe_~d~0.offset_6 |v_Thread1_my_callback_#in~arg.offset_3|) (= v_Thread1_my_callback_thidvar0_2 1)) InVars {ULTIMATE.start_my_drv_probe_~d~0.offset=v_ULTIMATE.start_my_drv_probe_~d~0.offset_6, ULTIMATE.start_my_drv_probe_~d~0.base=v_ULTIMATE.start_my_drv_probe_~d~0.base_6} OutVars{ULTIMATE.start_my_drv_probe_~d~0.offset=v_ULTIMATE.start_my_drv_probe_~d~0.offset_6, Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_2, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_3|, Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_3|, ULTIMATE.start_my_drv_probe_~d~0.base=v_ULTIMATE.start_my_drv_probe_~d~0.base_6} AuxVars[] AssignedVars[Thread1_my_callback_thidvar0, Thread1_my_callback_#in~arg.base, Thread1_my_callback_#in~arg.offset] VAL [Thread0_my_callback_thidvar0=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [322] L3817-2-->L3818: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet34=|v_ULTIMATE.start_my_drv_probe_#t~nondet34_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet34] VAL [Thread0_my_callback_thidvar0=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [289] L3818-->L3822: Formula: (= |v_ULTIMATE.start_my_drv_probe_#res_2| 0) InVars {} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#res] VAL [Thread0_my_callback_thidvar0=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [344] my_callbackENTRY-->L3792: Formula: (and (= v_Thread1_my_callback_~arg.offset_1 |v_Thread1_my_callback_#in~arg.offset_1|) (= v_Thread1_my_callback_~arg.base_1 |v_Thread1_my_callback_#in~arg.base_1|)) InVars {Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_1|, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_1|} OutVars{Thread1_my_callback_~arg.base=v_Thread1_my_callback_~arg.base_1, Thread1_my_callback_~arg.offset=v_Thread1_my_callback_~arg.offset_1, Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_1|, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_1|} AuxVars[] AssignedVars[Thread1_my_callback_~arg.base, Thread1_my_callback_~arg.offset] VAL [Thread0_my_callback_thidvar0=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [345] L3792-->L3793: Formula: (and (= v_Thread1_my_callback_~dev~0.base_1 v_Thread1_my_callback_~arg.base_2) (= v_Thread1_my_callback_~dev~0.offset_1 v_Thread1_my_callback_~arg.offset_2)) InVars {Thread1_my_callback_~arg.base=v_Thread1_my_callback_~arg.base_2, Thread1_my_callback_~arg.offset=v_Thread1_my_callback_~arg.offset_2} OutVars{Thread1_my_callback_~dev~0.base=v_Thread1_my_callback_~dev~0.base_1, Thread1_my_callback_~arg.base=v_Thread1_my_callback_~arg.base_2, Thread1_my_callback_~dev~0.offset=v_Thread1_my_callback_~dev~0.offset_1, Thread1_my_callback_~arg.offset=v_Thread1_my_callback_~arg.offset_2} AuxVars[] AssignedVars[Thread1_my_callback_~dev~0.base, Thread1_my_callback_~dev~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [346] L3793-->L3794: Formula: true InVars {} OutVars{Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_1, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_1} AuxVars[] AssignedVars[Thread1_my_callback_~data~0.offset, Thread1_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [330] my_callbackENTRY-->L3792: Formula: (and (= v_Thread0_my_callback_~arg.offset_1 |v_Thread0_my_callback_#in~arg.offset_1|) (= v_Thread0_my_callback_~arg.base_1 |v_Thread0_my_callback_#in~arg.base_1|)) InVars {Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_1|, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_1|} OutVars{Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_1|, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_1|, Thread0_my_callback_~arg.offset=v_Thread0_my_callback_~arg.offset_1, Thread0_my_callback_~arg.base=v_Thread0_my_callback_~arg.base_1} AuxVars[] AssignedVars[Thread0_my_callback_~arg.offset, Thread0_my_callback_~arg.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [331] L3792-->L3793: Formula: (and (= v_Thread0_my_callback_~dev~0.base_1 v_Thread0_my_callback_~arg.base_2) (= v_Thread0_my_callback_~dev~0.offset_1 v_Thread0_my_callback_~arg.offset_2)) InVars {Thread0_my_callback_~arg.offset=v_Thread0_my_callback_~arg.offset_2, Thread0_my_callback_~arg.base=v_Thread0_my_callback_~arg.base_2} OutVars{Thread0_my_callback_~dev~0.offset=v_Thread0_my_callback_~dev~0.offset_1, Thread0_my_callback_~dev~0.base=v_Thread0_my_callback_~dev~0.base_1, Thread0_my_callback_~arg.offset=v_Thread0_my_callback_~arg.offset_2, Thread0_my_callback_~arg.base=v_Thread0_my_callback_~arg.base_2} AuxVars[] AssignedVars[Thread0_my_callback_~dev~0.offset, Thread0_my_callback_~dev~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [347] L3794-->L3794-1: Formula: (and (= v_Thread1_my_callback_~__mptr~0.base_1 v_Thread1_my_callback_~dev~0.base_2) (= v_Thread1_my_callback_~__mptr~0.offset_1 v_Thread1_my_callback_~dev~0.offset_2)) InVars {Thread1_my_callback_~dev~0.base=v_Thread1_my_callback_~dev~0.base_2, Thread1_my_callback_~dev~0.offset=v_Thread1_my_callback_~dev~0.offset_2} OutVars{Thread1_my_callback_~dev~0.base=v_Thread1_my_callback_~dev~0.base_2, Thread1_my_callback_~dev~0.offset=v_Thread1_my_callback_~dev~0.offset_2, Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_1, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_1} AuxVars[] AssignedVars[Thread1_my_callback_~__mptr~0.base, Thread1_my_callback_~__mptr~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [332] L3793-->L3794: Formula: true InVars {} OutVars{Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_1, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_1} AuxVars[] AssignedVars[Thread0_my_callback_~data~0.offset, Thread0_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [348] L3794-1-->L3796: Formula: (and (= v_Thread1_my_callback_~data~0.base_2 v_Thread1_my_callback_~__mptr~0.base_2) (= v_Thread1_my_callback_~data~0.offset_2 (+ v_Thread1_my_callback_~__mptr~0.offset_2 (- 40)))) InVars {Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_2, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_2} OutVars{Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_2, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_2, Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_2, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_2} AuxVars[] AssignedVars[Thread1_my_callback_~data~0.offset, Thread1_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [333] L3794-->L3794-1: Formula: (and (= v_Thread0_my_callback_~__mptr~0.base_1 v_Thread0_my_callback_~dev~0.base_2) (= v_Thread0_my_callback_~__mptr~0.offset_1 v_Thread0_my_callback_~dev~0.offset_2)) InVars {Thread0_my_callback_~dev~0.offset=v_Thread0_my_callback_~dev~0.offset_2, Thread0_my_callback_~dev~0.base=v_Thread0_my_callback_~dev~0.base_2} OutVars{Thread0_my_callback_~dev~0.offset=v_Thread0_my_callback_~dev~0.offset_2, Thread0_my_callback_~dev~0.base=v_Thread0_my_callback_~dev~0.base_2, Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_1, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_1} AuxVars[] AssignedVars[Thread0_my_callback_~__mptr~0.base, Thread0_my_callback_~__mptr~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [222] L3822-->L3851-2: Formula: (= |v_ULTIMATE.start_main_#t~ret42_2| |v_ULTIMATE.start_my_drv_probe_#res_4|) InVars {ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_4|} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_4|, ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret42] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [280] L3851-2-->L3851-3: Formula: (and (<= 0 (+ |v_ULTIMATE.start_main_#t~ret42_3| 2147483648)) (<= |v_ULTIMATE.start_main_#t~ret42_3| 2147483647)) InVars {ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_3|} OutVars{ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_3|} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [277] L3851-3-->L3851-4: Formula: (= v_ULTIMATE.start_main_~probe_ret~0_3 |v_ULTIMATE.start_main_#t~ret42_4|) InVars {ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_4|} OutVars{ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_4|, ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_~probe_ret~0] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [278] L3851-4-->L3852: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ret42=|v_ULTIMATE.start_main_#t~ret42_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret42] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [246] L3852-->L3853: Formula: (= v_ULTIMATE.start_main_~probe_ret~0_4 0) InVars {ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_4} OutVars{ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_4} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [311] L3853-->L3853-1: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#in~data.base_1| |v_ULTIMATE.start_main_~#data~1.base_4|) (= |v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_1| |v_ULTIMATE.start_main_~#data~1.offset_4|)) InVars {ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_4|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_4|} OutVars{ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_4|, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_1|, ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_1|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#in~data.offset, ULTIMATE.start_my_drv_disconnect_#in~data.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [317] L3853-1-->L3825: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_1|, ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_1, ULTIMATE.start_my_drv_disconnect_#t~mem37=|v_ULTIMATE.start_my_drv_disconnect_#t~mem37_1|, ULTIMATE.start_my_drv_disconnect_#t~mem39=|v_ULTIMATE.start_my_drv_disconnect_#t~mem39_1|, ULTIMATE.start_my_drv_disconnect_#t~mem35=|v_ULTIMATE.start_my_drv_disconnect_#t~mem35_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet40.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet40.base_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet40.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet40.offset_1|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_1|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_1, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38, ULTIMATE.start_my_drv_disconnect_~data.offset, ULTIMATE.start_my_drv_disconnect_#t~mem37, ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_#t~mem39, ULTIMATE.start_my_drv_disconnect_~data.base, ULTIMATE.start_my_drv_disconnect_~#status~0.base, ULTIMATE.start_my_drv_disconnect_#t~mem35, ULTIMATE.start_my_drv_disconnect_#t~nondet36.base, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet40.base, ULTIMATE.start_my_drv_disconnect_#t~nondet40.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [214] L3825-->L3826: Formula: (and (= v_ULTIMATE.start_my_drv_disconnect_~data.base_2 |v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|) (= v_ULTIMATE.start_my_drv_disconnect_~data.offset_2 |v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|)) InVars {ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|} OutVars{ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_2, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_2, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|, ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~data.offset, ULTIMATE.start_my_drv_disconnect_~data.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [294] L3826-->L3826-1: Formula: (and (= |v_#length_7| (store |v_#length_8| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2| 4)) (= (store |v_#valid_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2| 1) |v_#valid_9|) (= 0 (select |v_#valid_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|)) (= |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|))) InVars {#length=|v_#length_8|, #valid=|v_#valid_10|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_2|, #length=|v_#length_7|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.base, #valid, #length] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [300] L3826-1-->L3827: Formula: (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem35_2| (select (select |v_#memory_int_11| |v_~#t1~0.base_4|) |v_~#t1~0.offset_4|)) InVars {#memory_int=|v_#memory_int_11|, ~#t1~0.offset=|v_~#t1~0.offset_4|, ~#t1~0.base=|v_~#t1~0.base_4|} OutVars{#memory_int=|v_#memory_int_11|, ~#t1~0.offset=|v_~#t1~0.offset_4|, ~#t1~0.base=|v_~#t1~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~mem35=|v_ULTIMATE.start_my_drv_disconnect_#t~mem35_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem35] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [334] L3794-1-->L3796: Formula: (and (= v_Thread0_my_callback_~data~0.base_2 v_Thread0_my_callback_~__mptr~0.base_2) (= v_Thread0_my_callback_~data~0.offset_2 (+ v_Thread0_my_callback_~__mptr~0.offset_2 (- 40)))) InVars {Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_2, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_2} OutVars{Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_2, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_2, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_2, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_2} AuxVars[] AssignedVars[Thread0_my_callback_~data~0.offset, Thread0_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [335] L3796-->L3796-1: Formula: (let ((.cse0 (select |v_#pthreadsMutex_4| v_Thread0_my_callback_~data~0.base_3))) (and (= (store |v_#pthreadsMutex_4| v_Thread0_my_callback_~data~0.base_3 (store .cse0 v_Thread0_my_callback_~data~0.offset_3 1)) |v_#pthreadsMutex_3|) (= 0 |v_Thread0_my_callback_#t~nondet30_1|) (= (select .cse0 v_Thread0_my_callback_~data~0.offset_3) 0))) InVars {#pthreadsMutex=|v_#pthreadsMutex_4|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_3, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_3} OutVars{Thread0_my_callback_#t~nondet30=|v_Thread0_my_callback_#t~nondet30_1|, #pthreadsMutex=|v_#pthreadsMutex_3|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_3, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_3} AuxVars[] AssignedVars[#pthreadsMutex, Thread0_my_callback_#t~nondet30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#t~nondet30|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [336] L3796-1-->L3797: Formula: true InVars {} OutVars{Thread0_my_callback_#t~nondet30=|v_Thread0_my_callback_#t~nondet30_2|} AuxVars[] AssignedVars[Thread0_my_callback_#t~nondet30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [337] L3797-->L3797-1: Formula: (let ((.cse0 (+ v_Thread0_my_callback_~data~0.offset_4 40))) (and (= |v_#memory_$Pointer$.offset_21| (store |v_#memory_$Pointer$.offset_22| v_Thread0_my_callback_~data~0.base_4 (store (select |v_#memory_$Pointer$.offset_22| v_Thread0_my_callback_~data~0.base_4) .cse0 (select (select |v_#memory_$Pointer$.offset_21| v_Thread0_my_callback_~data~0.base_4) .cse0)))) (= |v_#memory_$Pointer$.base_21| (store |v_#memory_$Pointer$.base_22| v_Thread0_my_callback_~data~0.base_4 (store (select |v_#memory_$Pointer$.base_22| v_Thread0_my_callback_~data~0.base_4) .cse0 (select (select |v_#memory_$Pointer$.base_21| v_Thread0_my_callback_~data~0.base_4) .cse0)))) (= (store |v_#memory_int_32| v_Thread0_my_callback_~data~0.base_4 (store (select |v_#memory_int_32| v_Thread0_my_callback_~data~0.base_4) .cse0 1)) |v_#memory_int_31|))) InVars {#memory_int=|v_#memory_int_32|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_4, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_22|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_22|} OutVars{#memory_int=|v_#memory_int_31|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_4, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_21|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_21|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [338] L3797-1-->L3798: Formula: (= |v_Thread0_my_callback_#t~mem31_1| (select (select |v_#memory_int_33| v_Thread0_my_callback_~data~0.base_5) (+ v_Thread0_my_callback_~data~0.offset_5 44))) InVars {#memory_int=|v_#memory_int_33|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_5, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_5} OutVars{#memory_int=|v_#memory_int_33|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_5, Thread0_my_callback_#t~mem31=|v_Thread0_my_callback_#t~mem31_1|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_5} AuxVars[] AssignedVars[Thread0_my_callback_#t~mem31] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#t~mem31|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [339] L3798-->L3798-1: Formula: (let ((.cse0 (+ v_Thread0_my_callback_~data~0.offset_6 44))) (and (= |v_#memory_$Pointer$.base_23| (store |v_#memory_$Pointer$.base_24| v_Thread0_my_callback_~data~0.base_6 (store (select |v_#memory_$Pointer$.base_24| v_Thread0_my_callback_~data~0.base_6) .cse0 (select (select |v_#memory_$Pointer$.base_23| v_Thread0_my_callback_~data~0.base_6) .cse0)))) (= |v_#memory_$Pointer$.offset_23| (store |v_#memory_$Pointer$.offset_24| v_Thread0_my_callback_~data~0.base_6 (store (select |v_#memory_$Pointer$.offset_24| v_Thread0_my_callback_~data~0.base_6) .cse0 (select (select |v_#memory_$Pointer$.offset_23| v_Thread0_my_callback_~data~0.base_6) .cse0)))) (= (store |v_#memory_int_35| v_Thread0_my_callback_~data~0.base_6 (store (select |v_#memory_int_35| v_Thread0_my_callback_~data~0.base_6) .cse0 (+ |v_Thread0_my_callback_#t~mem31_2| 1))) |v_#memory_int_34|))) InVars {#memory_$Pointer$.base=|v_#memory_$Pointer$.base_24|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_6, #memory_int=|v_#memory_int_35|, Thread0_my_callback_#t~mem31=|v_Thread0_my_callback_#t~mem31_2|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_6, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_24|} OutVars{#memory_$Pointer$.base=|v_#memory_$Pointer$.base_23|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_6, #memory_int=|v_#memory_int_34|, Thread0_my_callback_#t~mem31=|v_Thread0_my_callback_#t~mem31_2|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_6, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_23|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#t~mem31|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [340] L3798-1-->L3799: Formula: true InVars {} OutVars{Thread0_my_callback_#t~mem31=|v_Thread0_my_callback_#t~mem31_3|} AuxVars[] AssignedVars[Thread0_my_callback_#t~mem31] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [341] L3799-->L3800: Formula: (= |v_#pthreadsMutex_5| (store |v_#pthreadsMutex_6| v_Thread0_my_callback_~data~0.base_7 (store (select |v_#pthreadsMutex_6| v_Thread0_my_callback_~data~0.base_7) v_Thread0_my_callback_~data~0.offset_7 0))) InVars {#pthreadsMutex=|v_#pthreadsMutex_6|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_7, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_7} OutVars{#pthreadsMutex=|v_#pthreadsMutex_5|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_7, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_7} AuxVars[] AssignedVars[#pthreadsMutex] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [342] L3800-->my_callbackFINAL: Formula: (and (= |v_Thread0_my_callback_#res.offset_1| 0) (= |v_Thread0_my_callback_#res.base_1| 0)) InVars {} OutVars{Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_1|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_1|} AuxVars[] AssignedVars[Thread0_my_callback_#res.base, Thread0_my_callback_#res.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 [343] my_callbackFINAL-->my_callbackEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] JOIN 1 [360] my_callbackEXIT-->L3827-1: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem35_5| v_Thread0_my_callback_thidvar0_4) (= |v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_5| |v_Thread0_my_callback_#res.base_3|) (= |v_Thread0_my_callback_#res.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_5|)) InVars {Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_4, Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_3|, ULTIMATE.start_my_drv_disconnect_#t~mem35=|v_ULTIMATE.start_my_drv_disconnect_#t~mem35_5|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_3|} OutVars{Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_4, Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_3|, ULTIMATE.start_my_drv_disconnect_#t~mem35=|v_ULTIMATE.start_my_drv_disconnect_#t~mem35_5|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_5|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_5|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet36.base, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [349] L3796-->L3796-1: Formula: (let ((.cse0 (select |v_#pthreadsMutex_4| v_Thread1_my_callback_~data~0.base_3))) (and (= (store |v_#pthreadsMutex_4| v_Thread1_my_callback_~data~0.base_3 (store .cse0 v_Thread1_my_callback_~data~0.offset_3 1)) |v_#pthreadsMutex_3|) (= 0 |v_Thread1_my_callback_#t~nondet30_1|) (= (select .cse0 v_Thread1_my_callback_~data~0.offset_3) 0))) InVars {#pthreadsMutex=|v_#pthreadsMutex_4|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_3, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_3} OutVars{#pthreadsMutex=|v_#pthreadsMutex_3|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_3, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_3, Thread1_my_callback_#t~nondet30=|v_Thread1_my_callback_#t~nondet30_1|} AuxVars[] AssignedVars[#pthreadsMutex, Thread1_my_callback_#t~nondet30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [253] L3827-1-->L3827-2: Formula: (and (= (store |v_#memory_int_13| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_int_13| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| (select (select |v_#memory_int_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|))) |v_#memory_int_12|) (= |v_#memory_$Pointer$.offset_9| (store |v_#memory_$Pointer$.offset_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_$Pointer$.offset_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_2|))) (= (store |v_#memory_$Pointer$.base_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_$Pointer$.base_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_2|)) |v_#memory_$Pointer$.base_9|)) InVars {ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_10|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_2|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_2|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_10|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_9|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_2|, #memory_int=|v_#memory_int_12|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_2|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_9|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [261] L3827-2-->L3827-3: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet36.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet36.base_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet36.base, ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [258] L3827-3-->L3829: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem35=|v_ULTIMATE.start_my_drv_disconnect_#t~mem35_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem35] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |Thread1_my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [350] L3796-1-->L3797: Formula: true InVars {} OutVars{Thread1_my_callback_#t~nondet30=|v_Thread1_my_callback_#t~nondet30_2|} AuxVars[] AssignedVars[Thread1_my_callback_#t~nondet30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [287] L3829-->L3829-1: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_disconnect_~data.offset_3 40))) (and (= (store |v_#memory_int_15| v_ULTIMATE.start_my_drv_disconnect_~data.base_3 (store (select |v_#memory_int_15| v_ULTIMATE.start_my_drv_disconnect_~data.base_3) .cse0 3)) |v_#memory_int_14|) (= (store |v_#memory_$Pointer$.base_12| v_ULTIMATE.start_my_drv_disconnect_~data.base_3 (store (select |v_#memory_$Pointer$.base_12| v_ULTIMATE.start_my_drv_disconnect_~data.base_3) .cse0 (select (select |v_#memory_$Pointer$.base_11| v_ULTIMATE.start_my_drv_disconnect_~data.base_3) .cse0))) |v_#memory_$Pointer$.base_11|) (= |v_#memory_$Pointer$.offset_11| (store |v_#memory_$Pointer$.offset_12| v_ULTIMATE.start_my_drv_disconnect_~data.base_3 (store (select |v_#memory_$Pointer$.offset_12| v_ULTIMATE.start_my_drv_disconnect_~data.base_3) .cse0 (select (select |v_#memory_$Pointer$.offset_11| v_ULTIMATE.start_my_drv_disconnect_~data.base_3) .cse0)))))) InVars {ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_3, #memory_int=|v_#memory_int_15|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_12|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_12|} OutVars{ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_3, #memory_int=|v_#memory_int_14|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_11|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_11|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [281] L3829-1-->L3830: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_disconnect_~data.offset_4 44))) (and (= (store |v_#memory_$Pointer$.offset_14| v_ULTIMATE.start_my_drv_disconnect_~data.base_4 (store (select |v_#memory_$Pointer$.offset_14| v_ULTIMATE.start_my_drv_disconnect_~data.base_4) .cse0 (select (select |v_#memory_$Pointer$.offset_13| v_ULTIMATE.start_my_drv_disconnect_~data.base_4) .cse0))) |v_#memory_$Pointer$.offset_13|) (= (store |v_#memory_int_17| v_ULTIMATE.start_my_drv_disconnect_~data.base_4 (store (select |v_#memory_int_17| v_ULTIMATE.start_my_drv_disconnect_~data.base_4) .cse0 3)) |v_#memory_int_16|) (= |v_#memory_$Pointer$.base_13| (store |v_#memory_$Pointer$.base_14| v_ULTIMATE.start_my_drv_disconnect_~data.base_4 (store (select |v_#memory_$Pointer$.base_14| v_ULTIMATE.start_my_drv_disconnect_~data.base_4) .cse0 (select (select |v_#memory_$Pointer$.base_13| v_ULTIMATE.start_my_drv_disconnect_~data.base_4) .cse0)))))) InVars {ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_4, #memory_int=|v_#memory_int_17|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_4, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_14|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_14|} OutVars{ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_4, #memory_int=|v_#memory_int_16|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_4, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_13|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_13|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 [351] L3797-->L3797-1: Formula: (let ((.cse0 (+ v_Thread1_my_callback_~data~0.offset_4 40))) (and (= |v_#memory_$Pointer$.offset_21| (store |v_#memory_$Pointer$.offset_22| v_Thread1_my_callback_~data~0.base_4 (store (select |v_#memory_$Pointer$.offset_22| v_Thread1_my_callback_~data~0.base_4) .cse0 (select (select |v_#memory_$Pointer$.offset_21| v_Thread1_my_callback_~data~0.base_4) .cse0)))) (= |v_#memory_$Pointer$.base_21| (store |v_#memory_$Pointer$.base_22| v_Thread1_my_callback_~data~0.base_4 (store (select |v_#memory_$Pointer$.base_22| v_Thread1_my_callback_~data~0.base_4) .cse0 (select (select |v_#memory_$Pointer$.base_21| v_Thread1_my_callback_~data~0.base_4) .cse0)))) (= (store |v_#memory_int_32| v_Thread1_my_callback_~data~0.base_4 (store (select |v_#memory_int_32| v_Thread1_my_callback_~data~0.base_4) .cse0 1)) |v_#memory_int_31|))) InVars {#memory_int=|v_#memory_int_32|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_4, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_22|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_22|} OutVars{#memory_int=|v_#memory_int_31|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_4, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_21|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_21|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [250] L3830-->L3831: Formula: (= (select (select |v_#memory_int_18| v_ULTIMATE.start_my_drv_disconnect_~data.base_5) (+ v_ULTIMATE.start_my_drv_disconnect_~data.offset_5 40)) |v_ULTIMATE.start_my_drv_disconnect_#t~mem37_2|) InVars {ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_5, #memory_int=|v_#memory_int_18|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_5} OutVars{ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_5, #memory_int=|v_#memory_int_18|, ULTIMATE.start_my_drv_disconnect_#t~mem37=|v_ULTIMATE.start_my_drv_disconnect_#t~mem37_2|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_5} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem37] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [312] L3831-->L3831-1: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_1| (ite (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem37_3| 3) 1 0)) InVars {ULTIMATE.start_my_drv_disconnect_#t~mem37=|v_ULTIMATE.start_my_drv_disconnect_#t~mem37_3|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem37=|v_ULTIMATE.start_my_drv_disconnect_#t~mem37_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [318] L3831-1-->L3772: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [262] L3772-->L3772-1: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_2 |v_ULTIMATE.start_ldv_assert_#in~expression_2|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_2|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_2|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_2} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [264] L3772-1-->L3772-2: Formula: (= 0 v_ULTIMATE.start_ldv_assert_~expression_3) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_3} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 [259] L3772-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=63, Thread0_my_callback_~arg.offset=40, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread0_my_callback_~dev~0.base=63, Thread0_my_callback_~dev~0.offset=40, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=63, Thread1_my_callback_~arg.offset=40, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, Thread1_my_callback_~dev~0.base=63, Thread1_my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=63, |Thread0_my_callback_#in~arg.offset|=40, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=63, |Thread1_my_callback_#in~arg.offset|=40, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 SUMMARY for call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); srcloc: L3774 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3774-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); srcloc: L3774-2 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3774-3 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#t~ret41, main_#t~ret42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_#t~mem46, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_init_#res := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_#t~ret41 := my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_~ret~0 := main_#t~ret41; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#t~ret41; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume 0 == main_~ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_~probe_ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); srcloc: L3850 VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#res; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset, my_drv_probe_~res~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3809 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3809-1 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume -2147483648 <= my_drv_probe_#t~nondet32 && my_drv_probe_#t~nondet32 <= 2147483647; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet32; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet32; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume !(0 != my_drv_probe_~res~0); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3816 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] FORK -1 fork 0 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3817 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] FORK -1 fork 1 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet34; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_#res := 0; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_#t~ret42 := my_drv_probe_#res; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume -2147483648 <= main_#t~ret42 && main_#t~ret42 <= 2147483647; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_~probe_ret~0 := main_#t~ret42; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#t~ret42; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume 0 == main_~probe_ret~0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_disconnect_#t~mem35, my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_#t~mem37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~mem39, my_drv_disconnect_#t~nondet40.base, my_drv_disconnect_#t~nondet40.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); srcloc: L3826 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem35 := read~int(~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3826-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); srcloc: L3796 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 havoc #t~nondet30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3797 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call #t~mem31 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3797-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#t~mem31|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call write~int(1 + #t~mem31, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3798 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#t~mem31|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 havoc #t~mem31; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 #pthreadsMutex := #pthreadsMutex[~data~0.base,~data~0.offset := 0]; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 assume true; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] JOIN 1 join my_drv_disconnect_#t~mem35 assign my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 SUMMARY for call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); srcloc: L3796 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3827-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_disconnect_#t~mem35; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 havoc #t~nondet30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(3, my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); srcloc: L3829 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(3, my_drv_disconnect_~data.base, 44 + my_drv_disconnect_~data.offset, 4); srcloc: L3829-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3797 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem37 := read~int(my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); srcloc: L3830 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 ldv_assert_#in~expression := (if 3 == my_drv_disconnect_#t~mem37 then 1 else 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume 0 == ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume !false; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 SUMMARY for call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); srcloc: L3774 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3774-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); srcloc: L3774-2 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3774-3 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#t~ret41, main_#t~ret42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_#t~mem46, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_init_#res := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_#t~ret41 := my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_~ret~0 := main_#t~ret41; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#t~ret41; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume 0 == main_~ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_~probe_ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); srcloc: L3850 VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#res; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset, my_drv_probe_~res~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3809 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3809-1 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume -2147483648 <= my_drv_probe_#t~nondet32 && my_drv_probe_#t~nondet32 <= 2147483647; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet32; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet32; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume !(0 != my_drv_probe_~res~0); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3816 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] FORK -1 fork 0 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3817 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] FORK -1 fork 1 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_probe_#t~nondet34; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_probe_#res := 0; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_#t~ret42 := my_drv_probe_#res; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume -2147483648 <= main_#t~ret42 && main_#t~ret42 <= 2147483647; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 main_~probe_ret~0 := main_#t~ret42; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_#t~ret42|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc main_#t~ret42; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume 0 == main_~probe_ret~0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_disconnect_#t~mem35, my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_#t~mem37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~mem39, my_drv_disconnect_#t~nondet40.base, my_drv_disconnect_#t~nondet40.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); srcloc: L3826 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem35 := read~int(~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3826-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); srcloc: L3796 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 havoc #t~nondet30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3797 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call #t~mem31 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3797-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#t~mem31|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 SUMMARY for call write~int(1 + #t~mem31, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3798 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#t~mem31|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 havoc #t~mem31; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 #pthreadsMutex := #pthreadsMutex[~data~0.base,~data~0.offset := 0]; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 1 assume true; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] JOIN 1 join my_drv_disconnect_#t~mem35 assign my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 SUMMARY for call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); srcloc: L3796 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3827-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet36.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem35|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc my_drv_disconnect_#t~mem35; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~nondet30|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 havoc #t~nondet30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(3, my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); srcloc: L3829 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~int(3, my_drv_disconnect_~data.base, 44 + my_drv_disconnect_~data.offset, 4); srcloc: L3829-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] 0 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3797 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem37 := read~int(my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); srcloc: L3830 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 ldv_assert_#in~expression := (if 3 == my_drv_disconnect_#t~mem37 then 1 else 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume 0 == ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 assume !false; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=63, my_callback_~arg.offset=40, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, my_callback_~dev~0.base=63, my_callback_~dev~0.offset=40, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~d~0.base=63, ULTIMATE.start_my_drv_probe_~d~0.offset=40, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=63, |my_callback_#in~arg.offset|=40, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem37|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=49, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=58, |~#t2~0.offset|=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L3774] -1 call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3774] -1 call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [?] -1 havoc main_#t~ret41, main_#t~ret42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_#t~mem46, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL.base=0, #NULL.offset=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 main_#t~ret41 := my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 main_~ret~0 := main_#t~ret41; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret41=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 havoc main_#t~ret41; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3848-L3862] -1 assume 0 == main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3850] -1 call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3851] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3851] -1 havoc my_drv_probe_#t~nondet32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset, my_drv_probe_~res~0; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3803-L3823] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3804] -1 my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3808] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3809] -1 call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3810] -1 call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3812] -1 assume -2147483648 <= my_drv_probe_#t~nondet32 && my_drv_probe_#t~nondet32 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3812] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet32; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3812] -1 havoc my_drv_probe_#t~nondet32; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3813-L3814] -1 assume !(0 != my_drv_probe_~res~0); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3816] -1 call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3816] FORK -1 fork 0 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3816] -1 havoc my_drv_probe_#t~nondet33; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3817] -1 call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3817] FORK -1 fork 1 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3817] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3818] -1 my_drv_probe_#res := 0; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3791-L3801] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40] [L3792] 0 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3793] 0 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3791-L3801] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3792] 1 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 0 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3793] 1 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 1 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 main_#t~ret42 := my_drv_probe_#res; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_#t~ret42=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret42 && main_#t~ret42 <= 2147483647; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_#t~ret42=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret42; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_#t~ret42=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 havoc main_#t~ret42; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3852-L3856] -1 assume 0 == main_~probe_ret~0; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3853] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem35, my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_#t~mem37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~mem39, my_drv_disconnect_#t~nondet40.base, my_drv_disconnect_#t~nondet40.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3825-L3836] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3826] -1 call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 call my_drv_disconnect_#t~mem35 := read~int(~#t1~0.base, ~#t1~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 1 call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 1 havoc #t~nondet30; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3797] 1 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3798] 1 call #t~mem31 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #t~mem31=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3798] 1 call write~int(1 + #t~mem31, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #t~mem31=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3798] 1 havoc #t~mem31; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3799] 1 #pthreadsMutex := #pthreadsMutex[~data~0.base,~data~0.offset := 0]; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3800] 1 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3791-L3801] 1 ensures true; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] JOIN 1 join my_drv_disconnect_#t~mem35 assign my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36.base=0, my_drv_disconnect_#t~nondet36.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 0 call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36.base=0, my_drv_disconnect_#t~nondet36.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36.base=0, my_drv_disconnect_#t~nondet36.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 havoc my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 havoc my_drv_disconnect_#t~mem35; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 0 havoc #t~nondet30; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3829] -1 call write~int(3, my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3830] -1 call write~int(3, my_drv_disconnect_~data.base, 44 + my_drv_disconnect_~data.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3797] 0 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3831] -1 call my_drv_disconnect_#t~mem37 := read~int(my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3831] -1 ldv_assert_#in~expression := (if 3 == my_drv_disconnect_#t~mem37 then 1 else 0); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3831] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3772] -1 assume 0 == ldv_assert_~expression; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3772] -1 assert false; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L3774] -1 call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3774] -1 call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [?] -1 havoc main_#t~ret41, main_#t~ret42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_#t~mem46, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL.base=0, #NULL.offset=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 main_#t~ret41 := my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 main_~ret~0 := main_#t~ret41; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret41=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3847] -1 havoc main_#t~ret41; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3848-L3862] -1 assume 0 == main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3850] -1 call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3851] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3851] -1 havoc my_drv_probe_#t~nondet32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset, my_drv_probe_~res~0; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3803-L3823] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3804] -1 my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3808] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3809] -1 call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3810] -1 call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3812] -1 assume -2147483648 <= my_drv_probe_#t~nondet32 && my_drv_probe_#t~nondet32 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3812] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet32; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3812] -1 havoc my_drv_probe_#t~nondet32; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3813-L3814] -1 assume !(0 != my_drv_probe_~res~0); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3816] -1 call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3816] FORK -1 fork 0 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3816] -1 havoc my_drv_probe_#t~nondet33; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3817] -1 call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3817] FORK -1 fork 1 my_callback(my_drv_probe_~d~0.base, my_drv_probe_~d~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3817] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3818] -1 my_drv_probe_#res := 0; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0] [L3791-L3801] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40] [L3792] 0 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3793] 0 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3791-L3801] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3792] 1 ~dev~0.base, ~dev~0.offset := ~arg.base, ~arg.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 0 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3793] 1 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 1 ~__mptr~0.base, ~__mptr~0.offset := ~dev~0.base, ~dev~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 main_#t~ret42 := my_drv_probe_#res; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_#t~ret42=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret42 && main_#t~ret42 <= 2147483647; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_#t~ret42=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret42; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_#t~ret42=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3851] -1 havoc main_#t~ret42; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3852-L3856] -1 assume 0 == main_~probe_ret~0; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3853] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem35, my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_#t~mem37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~mem39, my_drv_disconnect_#t~nondet40.base, my_drv_disconnect_#t~nondet40.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3825-L3836] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3826] -1 call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 call my_drv_disconnect_#t~mem35 := read~int(~#t1~0.base, ~#t1~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3794] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 1 call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 1 havoc #t~nondet30; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3797] 1 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3798] 1 call #t~mem31 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #t~mem31=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3798] 1 call write~int(1 + #t~mem31, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #t~mem31=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3798] 1 havoc #t~mem31; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3799] 1 #pthreadsMutex := #pthreadsMutex[~data~0.base,~data~0.offset := 0]; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3800] 1 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3791-L3801] 1 ensures true; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] JOIN 1 join my_drv_disconnect_#t~mem35 assign my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36.base=0, my_drv_disconnect_#t~nondet36.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 0 call #t~nondet30 := #PthreadsMutexLock(~data~0.base, ~data~0.offset); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36.base=0, my_drv_disconnect_#t~nondet36.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36.base=0, my_drv_disconnect_#t~nondet36.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 havoc my_drv_disconnect_#t~nondet36.base, my_drv_disconnect_#t~nondet36.offset; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3827] -1 havoc my_drv_disconnect_#t~mem35; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~nondet30=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3796] 0 havoc #t~nondet30; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3829] -1 call write~int(3, my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3830] -1 call write~int(3, my_drv_disconnect_~data.base, 44 + my_drv_disconnect_~data.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3797] 0 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3831] -1 call my_drv_disconnect_#t~mem37 := read~int(my_drv_disconnect_~data.base, 40 + my_drv_disconnect_~data.offset, 4); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3831] -1 ldv_assert_#in~expression := (if 3 == my_drv_disconnect_#t~mem37 then 1 else 0); VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3831] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3772] -1 assume 0 == ldv_assert_~expression; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [L3772] -1 assert false; VAL [#in~arg.base=63, #in~arg.offset=40, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0.base=49, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~d~0.base=63, my_drv_probe_~d~0.offset=40, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=58, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=63, ~arg.offset=40, ~data~0.base=63, ~data~0.offset=0, ~dev~0.base=63, ~dev~0.offset=40] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [?] -1 havoc main_#t~ret41, main_#t~ret42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_#t~mem46, main_~probe_ret~0, main_~#data~1, main_~ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL!base=0, #NULL!offset=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 main_#t~ret41 := my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 main_~ret~0 := main_#t~ret41; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret41=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 havoc main_#t~ret41; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3848] COND TRUE -1 0 == main_~ret~0 VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3850] FCALL -1 call main_~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3851] -1 my_drv_probe_#in~data := main_~#data~1; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3851] -1 havoc my_drv_probe_#t~nondet32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_~data, my_drv_probe_~d~0, my_drv_probe_~res~0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3803-L3823] -1 my_drv_probe_~data := my_drv_probe_#in~data; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3804] -1 my_drv_probe_~d~0 := { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: my_drv_probe_~data!base, offset: my_drv_probe_~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 assume -2147483648 <= my_drv_probe_#t~nondet32 && my_drv_probe_#t~nondet32 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 havoc my_drv_probe_#t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3813-L3814] COND FALSE -1 !(0 != my_drv_probe_~res~0) VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FORK -1 fork 0 my_callback(my_drv_probe_~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] -1 havoc my_drv_probe_#t~nondet33; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FORK -1 fork 1 my_callback(my_drv_probe_~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3818] -1 my_drv_probe_#res := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3791-L3801] 0 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40] [L3792] 0 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 0 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3791-L3801] 1 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3792] 1 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 1 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 main_#t~ret42 := my_drv_probe_#res; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_#t~ret42=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret42 && main_#t~ret42 <= 2147483647; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_#t~ret42=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_#t~ret42=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 havoc main_#t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3852] COND TRUE -1 0 == main_~probe_ret~0 VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3853] -1 my_drv_disconnect_#in~data := main_~#data~1; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem35, my_drv_disconnect_#t~nondet36, my_drv_disconnect_#t~mem37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~mem39, my_drv_disconnect_#t~nondet40, my_drv_disconnect_~data, my_drv_disconnect_~#status~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3825-L3836] -1 my_drv_disconnect_~data := my_drv_disconnect_#in~data; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3826] FCALL -1 call my_drv_disconnect_~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call my_drv_disconnect_#t~mem35 := read~int(~#t1~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 1 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 1 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call #t~mem31 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call write~int(1 + #t~mem31, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] 1 havoc #t~mem31; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3799] 1 #pthreadsMutex[{ base: ~data~0!base, offset: ~data~0!offset }] := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3800] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] JOIN 1 join my_drv_disconnect_#t~mem35 assign my_drv_disconnect_#t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36!base=0, my_drv_disconnect_#t~nondet36!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 0 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36!base=0, my_drv_disconnect_#t~nondet36!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet36, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36!base=0, my_drv_disconnect_#t~nondet36!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc my_drv_disconnect_#t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc my_drv_disconnect_#t~mem35; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 0 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3829] FCALL -1 call write~int(3, { base: my_drv_disconnect_~data!base, offset: 40 + my_drv_disconnect_~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3830] FCALL -1 call write~int(3, { base: my_drv_disconnect_~data!base, offset: 44 + my_drv_disconnect_~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] FCALL -1 call my_drv_disconnect_#t~mem37 := read~int({ base: my_drv_disconnect_~data!base, offset: 40 + my_drv_disconnect_~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] -1 ldv_assert_#in~expression := (if 3 == my_drv_disconnect_#t~mem37 then 1 else 0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] COND TRUE -1 0 == ldv_assert_~expression VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [?] -1 havoc main_#t~ret41, main_#t~ret42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_#t~mem46, main_~probe_ret~0, main_~#data~1, main_~ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL!base=0, #NULL!offset=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 main_#t~ret41 := my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret41=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 main_~ret~0 := main_#t~ret41; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret41=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 havoc main_#t~ret41; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3848] COND TRUE -1 0 == main_~ret~0 VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3850] FCALL -1 call main_~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3851] -1 my_drv_probe_#in~data := main_~#data~1; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3851] -1 havoc my_drv_probe_#t~nondet32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_~data, my_drv_probe_~d~0, my_drv_probe_~res~0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3803-L3823] -1 my_drv_probe_~data := my_drv_probe_#in~data; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3804] -1 my_drv_probe_~d~0 := { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: my_drv_probe_~data!base, offset: my_drv_probe_~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 assume -2147483648 <= my_drv_probe_#t~nondet32 && my_drv_probe_#t~nondet32 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 havoc my_drv_probe_#t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3813-L3814] COND FALSE -1 !(0 != my_drv_probe_~res~0) VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FORK -1 fork 0 my_callback(my_drv_probe_~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] -1 havoc my_drv_probe_#t~nondet33; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FORK -1 fork 1 my_callback(my_drv_probe_~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3818] -1 my_drv_probe_#res := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3791-L3801] 0 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40] [L3792] 0 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 0 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3791-L3801] 1 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3792] 1 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 1 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 main_#t~ret42 := my_drv_probe_#res; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_#t~ret42=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret42 && main_#t~ret42 <= 2147483647; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_#t~ret42=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_#t~ret42=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 havoc main_#t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3852] COND TRUE -1 0 == main_~probe_ret~0 VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3853] -1 my_drv_disconnect_#in~data := main_~#data~1; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem35, my_drv_disconnect_#t~nondet36, my_drv_disconnect_#t~mem37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~mem39, my_drv_disconnect_#t~nondet40, my_drv_disconnect_~data, my_drv_disconnect_~#status~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3825-L3836] -1 my_drv_disconnect_~data := my_drv_disconnect_#in~data; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3826] FCALL -1 call my_drv_disconnect_~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call my_drv_disconnect_#t~mem35 := read~int(~#t1~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 1 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 1 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call #t~mem31 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call write~int(1 + #t~mem31, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] 1 havoc #t~mem31; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3799] 1 #pthreadsMutex[{ base: ~data~0!base, offset: ~data~0!offset }] := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3800] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] JOIN 1 join my_drv_disconnect_#t~mem35 assign my_drv_disconnect_#t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36!base=0, my_drv_disconnect_#t~nondet36!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 0 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36!base=0, my_drv_disconnect_#t~nondet36!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet36, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_#t~nondet36!base=0, my_drv_disconnect_#t~nondet36!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc my_drv_disconnect_#t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem35=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc my_drv_disconnect_#t~mem35; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 0 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3829] FCALL -1 call write~int(3, { base: my_drv_disconnect_~data!base, offset: 40 + my_drv_disconnect_~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3830] FCALL -1 call write~int(3, { base: my_drv_disconnect_~data!base, offset: 44 + my_drv_disconnect_~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] FCALL -1 call my_drv_disconnect_#t~mem37 := read~int({ base: my_drv_disconnect_~data!base, offset: 40 + my_drv_disconnect_~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] -1 ldv_assert_#in~expression := (if 3 == my_drv_disconnect_#t~mem37 then 1 else 0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] COND TRUE -1 0 == ldv_assert_~expression VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem37=1, my_drv_disconnect_~#status~0!base=49, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~d~0!base=63, my_drv_probe_~d~0!offset=40, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3839] -1 #res := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 assume -2147483648 <= #t~ret41 && #t~ret41 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 ~ret~0 := #t~ret41; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 havoc #t~ret41; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3848] COND TRUE -1 0 == ~ret~0 VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3849] -1 havoc ~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3850] FCALL -1 call ~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3803-L3823] -1 ~data := #in~data; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3804] -1 ~d~0 := { base: ~data!base, offset: 40 + ~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: ~data!base, offset: ~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 assume -2147483648 <= #t~nondet32 && #t~nondet32 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 ~res~0 := #t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 havoc #t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3813-L3814] COND FALSE -1 !(0 != ~res~0) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FORK -1 fork 0 my_callback(~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] -1 havoc #t~nondet33; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FORK -1 fork 1 my_callback(~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] -1 havoc #t~nondet34; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3818] -1 #res := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3791-L3801] 0 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40] [L3792] 0 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 0 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3791-L3801] 1 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3792] 1 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 1 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 assume -2147483648 <= #t~ret42 && #t~ret42 <= 2147483647; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 ~probe_ret~0 := #t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 havoc #t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3852] COND TRUE -1 0 == ~probe_ret~0 VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3825-L3836] -1 ~data := #in~data; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3826] FCALL -1 call ~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call #t~mem35 := read~int(~#t1~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 1 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 1 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call #t~mem31 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call write~int(1 + #t~mem31, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] 1 havoc #t~mem31; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3799] 1 #pthreadsMutex[{ base: ~data~0!base, offset: ~data~0!offset }] := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3800] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] JOIN 1 join #t~mem35 assign #t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 0 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call write~$Pointer$(#t~nondet36, ~#status~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc #t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc #t~mem35; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 0 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3829] FCALL -1 call write~int(3, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3830] FCALL -1 call write~int(3, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] FCALL -1 call #t~mem37 := read~int({ base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] COND TRUE -1 0 == ~expression VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3839] -1 #res := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 assume -2147483648 <= #t~ret41 && #t~ret41 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 ~ret~0 := #t~ret41; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3847] -1 havoc #t~ret41; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3848] COND TRUE -1 0 == ~ret~0 VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3849] -1 havoc ~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3850] FCALL -1 call ~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3803-L3823] -1 ~data := #in~data; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3804] -1 ~d~0 := { base: ~data!base, offset: 40 + ~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: ~data!base, offset: ~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 assume -2147483648 <= #t~nondet32 && #t~nondet32 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 ~res~0 := #t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3812] -1 havoc #t~nondet32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3813-L3814] COND FALSE -1 !(0 != ~res~0) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] FORK -1 fork 0 my_callback(~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3816] -1 havoc #t~nondet33; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] FORK -1 fork 1 my_callback(~d~0); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3817] -1 havoc #t~nondet34; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3818] -1 #res := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0] [L3791-L3801] 0 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40] [L3792] 0 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 0 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3791-L3801] 1 ~arg := #in~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3792] 1 ~dev~0 := ~arg; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3793] 1 havoc ~data~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~__mptr~0 := ~dev~0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 assume -2147483648 <= #t~ret42 && #t~ret42 <= 2147483647; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 ~probe_ret~0 := #t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3851] -1 havoc #t~ret42; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3852] COND TRUE -1 0 == ~probe_ret~0 VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3825-L3836] -1 ~data := #in~data; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3826] FCALL -1 call ~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call #t~mem35 := read~int(~#t1~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3794] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 1 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 1 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call #t~mem31 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] FCALL 1 call write~int(1 + #t~mem31, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #t~mem31=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3798] 1 havoc #t~mem31; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3799] 1 #pthreadsMutex[{ base: ~data~0!base, offset: ~data~0!offset }] := 0; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3800] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] JOIN 1 join #t~mem35 assign #t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] FCALL 0 call #t~nondet30 := #PthreadsMutexLock({ base: ~data~0!base, offset: ~data~0!offset }); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] FCALL -1 call write~$Pointer$(#t~nondet36, ~#status~0, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc #t~nondet36; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3827] -1 havoc #t~mem35; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~nondet30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3796] 0 havoc #t~nondet30; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3829] FCALL -1 call write~int(3, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3830] FCALL -1 call write~int(3, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3797] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3831] FCALL -1 call #t~mem37 := read~int({ base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] COND TRUE -1 0 == ~expression VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=63, #in~arg!offset=40, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=58, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=63, ~arg!offset=40, ~data~0!base=63, ~data~0!offset=0, ~dev~0!base=63, ~dev~0!offset=40] [L3774] -1 pthread_t t1,t2; VAL [t1={69:0}, t2={58:0}] [L3839] -1 return 0; VAL [t1={69:0}, t2={58:0}] [L3847] -1 int ret = my_drv_init(); VAL [t1={69:0}, t2={58:0}] [L3848] COND TRUE -1 ret==0 VAL [t1={69:0}, t2={58:0}] [L3849] -1 int probe_ret; VAL [t1={69:0}, t2={58:0}] [L3850] -1 struct my_data data; VAL [t1={69:0}, t2={58:0}] [L3804] -1 struct device *d = &data->dev; VAL [t1={69:0}, t2={58:0}] [L3809] -1 data->shared.a = 0 VAL [t1={69:0}, t2={58:0}] [L3810] -1 data->shared.b = 0 VAL [t1={69:0}, t2={58:0}] [L3812] -1 int res = __VERIFIER_nondet_int(); VAL [t1={69:0}, t2={58:0}] [L3813] COND FALSE -1 !(\read(res)) VAL [t1={69:0}, t2={58:0}] [L3816] FCALL, FORK -1 pthread_create(&t1, ((void *)0), my_callback, (void *)d) VAL [arg={63:40}, t1={69:0}, t2={58:0}] [L3817] FCALL, FORK -1 pthread_create(&t2, ((void *)0), my_callback, (void *)d) VAL [arg={63:40}, t1={69:0}, t2={58:0}] [L3818] -1 return 0; VAL [arg={63:40}, t1={69:0}, t2={58:0}] [L3792] 0 struct device *dev = (struct device*)arg; VAL [arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3793] 0 struct my_data *data; VAL [arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3792] 1 struct device *dev = (struct device*)arg; VAL [arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3794] 0 const typeof( ((struct my_data *)0)->dev ) *__mptr = (dev); VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3793] 1 struct my_data *data; VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3794] 0 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3794] 1 const typeof( ((struct my_data *)0)->dev ) *__mptr = (dev); VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3851] -1 probe_ret = my_drv_probe(&data) VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3852] COND TRUE -1 probe_ret==0 VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3826] -1 void *status; VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3827] -1 \read(t1) VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3794] 1 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3797] 1 data->shared.a = 1 VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3798] EXPR 1 data->shared.b VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, data->shared.b=0, dev={63:40}, t1={69:0}, t2={58:0}] [L3798] 1 data->shared.b = data->shared.b + 1 VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, data->shared.b=0, dev={63:40}, t1={69:0}, t2={58:0}] [L3800] 1 return 0; VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3827] FCALL, JOIN 1 pthread_join(t1, &status) VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3829] -1 data->shared.a = 3 VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3830] -1 data->shared.b = 3 VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3797] 0 data->shared.a = 1 VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3831] -1 data->shared.a VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3772] COND TRUE -1 !expression VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3772] -1 __VERIFIER_error() VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] ----- [2018-11-23 03:43:08,292 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_edb2091b-50e0-466e-b32f-4383087c122e/bin-2019/uautomizer/witness.graphml [2018-11-23 03:43:08,292 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 03:43:08,293 INFO L168 Benchmark]: Toolchain (without parser) took 20089.49 ms. Allocated memory was 1.0 GB in the beginning and 1.7 GB in the end (delta: 639.6 MB). Free memory was 953.1 MB in the beginning and 1.2 GB in the end (delta: -262.1 MB). Peak memory consumption was 377.5 MB. Max. memory is 11.5 GB. [2018-11-23 03:43:08,294 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 979.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 03:43:08,294 INFO L168 Benchmark]: CACSL2BoogieTranslator took 872.11 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 189.3 MB). Free memory was 950.4 MB in the beginning and 1.1 GB in the end (delta: -119.4 MB). Peak memory consumption was 85.0 MB. Max. memory is 11.5 GB. [2018-11-23 03:43:08,295 INFO L168 Benchmark]: Boogie Procedure Inliner took 52.79 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 4.9 MB). Peak memory consumption was 4.9 MB. Max. memory is 11.5 GB. [2018-11-23 03:43:08,295 INFO L168 Benchmark]: Boogie Preprocessor took 35.45 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. [2018-11-23 03:43:08,296 INFO L168 Benchmark]: RCFGBuilder took 545.16 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 47.1 MB). Peak memory consumption was 47.1 MB. Max. memory is 11.5 GB. [2018-11-23 03:43:08,296 INFO L168 Benchmark]: TraceAbstraction took 16335.75 ms. Allocated memory was 1.2 GB in the beginning and 1.7 GB in the end (delta: 450.4 MB). Free memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: -274.8 MB). Peak memory consumption was 175.5 MB. Max. memory is 11.5 GB. [2018-11-23 03:43:08,296 INFO L168 Benchmark]: Witness Printer took 2243.96 ms. Allocated memory is still 1.7 GB. Free memory was 1.3 GB in the beginning and 1.2 GB in the end (delta: 70.9 MB). Peak memory consumption was 70.9 MB. Max. memory is 11.5 GB. [2018-11-23 03:43:08,299 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 979.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 872.11 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 189.3 MB). Free memory was 950.4 MB in the beginning and 1.1 GB in the end (delta: -119.4 MB). Peak memory consumption was 85.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 52.79 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 4.9 MB). Peak memory consumption was 4.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 35.45 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 545.16 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 47.1 MB). Peak memory consumption was 47.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 16335.75 ms. Allocated memory was 1.2 GB in the beginning and 1.7 GB in the end (delta: 450.4 MB). Free memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: -274.8 MB). Peak memory consumption was 175.5 MB. Max. memory is 11.5 GB. * Witness Printer took 2243.96 ms. Allocated memory is still 1.7 GB. Free memory was 1.3 GB in the beginning and 1.2 GB in the end (delta: 70.9 MB). Peak memory consumption was 70.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 3772]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L3774] -1 pthread_t t1,t2; VAL [t1={69:0}, t2={58:0}] [L3839] -1 return 0; VAL [t1={69:0}, t2={58:0}] [L3847] -1 int ret = my_drv_init(); VAL [t1={69:0}, t2={58:0}] [L3848] COND TRUE -1 ret==0 VAL [t1={69:0}, t2={58:0}] [L3849] -1 int probe_ret; VAL [t1={69:0}, t2={58:0}] [L3850] -1 struct my_data data; VAL [t1={69:0}, t2={58:0}] [L3804] -1 struct device *d = &data->dev; VAL [t1={69:0}, t2={58:0}] [L3809] -1 data->shared.a = 0 VAL [t1={69:0}, t2={58:0}] [L3810] -1 data->shared.b = 0 VAL [t1={69:0}, t2={58:0}] [L3812] -1 int res = __VERIFIER_nondet_int(); VAL [t1={69:0}, t2={58:0}] [L3813] COND FALSE -1 !(\read(res)) VAL [t1={69:0}, t2={58:0}] [L3816] FCALL, FORK -1 pthread_create(&t1, ((void *)0), my_callback, (void *)d) VAL [arg={63:40}, t1={69:0}, t2={58:0}] [L3817] FCALL, FORK -1 pthread_create(&t2, ((void *)0), my_callback, (void *)d) VAL [arg={63:40}, t1={69:0}, t2={58:0}] [L3818] -1 return 0; VAL [arg={63:40}, t1={69:0}, t2={58:0}] [L3792] 0 struct device *dev = (struct device*)arg; VAL [arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3793] 0 struct my_data *data; VAL [arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3792] 1 struct device *dev = (struct device*)arg; VAL [arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3794] 0 const typeof( ((struct my_data *)0)->dev ) *__mptr = (dev); VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3793] 1 struct my_data *data; VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, dev={63:40}, t1={69:0}, t2={58:0}] [L3794] 0 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3794] 1 const typeof( ((struct my_data *)0)->dev ) *__mptr = (dev); VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3851] -1 probe_ret = my_drv_probe(&data) VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3852] COND TRUE -1 probe_ret==0 VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3826] -1 void *status; VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3827] -1 \read(t1) VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3794] 1 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3797] 1 data->shared.a = 1 VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3798] EXPR 1 data->shared.b VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, data->shared.b=0, dev={63:40}, t1={69:0}, t2={58:0}] [L3798] 1 data->shared.b = data->shared.b + 1 VAL [__mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, data->shared.b=0, dev={63:40}, t1={69:0}, t2={58:0}] [L3800] 1 return 0; VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3827] FCALL, JOIN 1 pthread_join(t1, &status) VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3829] -1 data->shared.a = 3 VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3830] -1 data->shared.b = 3 VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3797] 0 data->shared.a = 1 VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3831] -1 data->shared.a VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3772] COND TRUE -1 !expression VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] [L3772] -1 __VERIFIER_error() VAL [\result={0:0}, __mptr={63:40}, arg={63:40}, arg={63:40}, data={63:0}, dev={63:40}, t1={69:0}, t2={58:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 161 locations, 6 error locations. UNSAFE Result, 16.2s OverallTime, 10 OverallIterations, 1 TraceHistogramMax, 10.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 2377 SDtfs, 7221 SDslu, 10704 SDs, 0 SdLazy, 3096 SolverSat, 194 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 235 GetRequests, 38 SyntacticMatches, 10 SemanticMatches, 187 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 534 ImplicationChecksByTransitivity, 8.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=9536occurred in iteration=2, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.9s AutomataMinimizationTime, 9 MinimizatonAttempts, 21104 StatesRemovedByMinimization, 8 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.1s SatisfiabilityAnalysisTime, 2.8s InterpolantComputationTime, 699 NumberOfCodeBlocks, 699 NumberOfCodeBlocksAsserted, 10 NumberOfCheckSat, 610 ConstructedInterpolants, 0 QuantifiedInterpolants, 247047 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 9 InterpolantComputations, 9 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...