./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/ldv-races/race-3_2-container_of-global_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/ldv-races/race-3_2-container_of-global_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash be78f24495f6395b0c8bd7d622003423e0349301 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.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 09:52:16,726 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 09:52:16,727 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 09:52:16,734 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 09:52:16,734 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 09:52:16,735 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 09:52:16,735 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 09:52:16,737 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 09:52:16,738 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 09:52:16,738 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 09:52:16,739 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 09:52:16,739 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 09:52:16,740 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 09:52:16,740 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 09:52:16,741 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 09:52:16,741 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 09:52:16,742 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 09:52:16,743 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 09:52:16,744 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 09:52:16,744 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 09:52:16,745 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 09:52:16,746 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 09:52:16,748 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 09:52:16,748 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 09:52:16,748 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 09:52:16,748 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 09:52:16,749 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 09:52:16,749 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 09:52:16,750 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 09:52:16,750 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 09:52:16,750 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 09:52:16,751 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 09:52:16,751 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 09:52:16,751 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 09:52:16,751 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 09:52:16,752 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 09:52:16,752 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-23 09:52:16,762 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 09:52:16,762 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 09:52:16,763 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 09:52:16,763 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 09:52:16,763 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 09:52:16,763 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 09:52:16,763 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 09:52:16,764 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 09:52:16,764 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 09:52:16,764 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 09:52:16,764 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 09:52:16,764 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 09:52:16,764 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 09:52:16,764 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 09:52:16,765 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 09:52:16,765 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 09:52:16,765 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 09:52:16,765 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 09:52:16,765 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 09:52:16,765 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 09:52:16,765 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 09:52:16,765 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 09:52:16,766 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 09:52:16,766 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 09:52:16,766 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 09:52:16,766 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 09:52:16,766 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 09:52:16,766 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 09:52:16,766 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 09:52:16,767 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 09:52:16,767 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> be78f24495f6395b0c8bd7d622003423e0349301 [2018-11-23 09:52:16,793 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 09:52:16,802 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 09:52:16,805 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 09:52:16,806 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 09:52:16,806 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 09:52:16,807 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-races/race-3_2-container_of-global_false-unreach-call.i [2018-11-23 09:52:16,852 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer/data/b8d03fa1c/1218bd8ab45149c79c96f0af7067dca5/FLAG61f8973d7 [2018-11-23 09:52:17,336 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 09:52:17,337 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/sv-benchmarks/c/ldv-races/race-3_2-container_of-global_false-unreach-call.i [2018-11-23 09:52:17,351 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer/data/b8d03fa1c/1218bd8ab45149c79c96f0af7067dca5/FLAG61f8973d7 [2018-11-23 09:52:17,826 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer/data/b8d03fa1c/1218bd8ab45149c79c96f0af7067dca5 [2018-11-23 09:52:17,829 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 09:52:17,830 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 09:52:17,831 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 09:52:17,831 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 09:52:17,833 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 09:52:17,834 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 09:52:17" (1/1) ... [2018-11-23 09:52:17,835 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7befe0c1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:17, skipping insertion in model container [2018-11-23 09:52:17,835 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 09:52:17" (1/1) ... [2018-11-23 09:52:17,842 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 09:52:17,884 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 09:52:18,454 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 09:52:18,462 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 09:52:18,507 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 09:52:18,744 INFO L195 MainTranslator]: Completed translation [2018-11-23 09:52:18,744 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:18 WrapperNode [2018-11-23 09:52:18,744 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 09:52:18,745 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 09:52:18,745 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 09:52:18,745 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 09:52:18,752 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:18" (1/1) ... [2018-11-23 09:52:18,772 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:18" (1/1) ... [2018-11-23 09:52:18,794 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 09:52:18,794 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 09:52:18,794 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 09:52:18,794 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 09:52:18,802 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:18" (1/1) ... [2018-11-23 09:52:18,802 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:18" (1/1) ... [2018-11-23 09:52:18,805 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:18" (1/1) ... [2018-11-23 09:52:18,806 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:18" (1/1) ... [2018-11-23 09:52:18,815 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:18" (1/1) ... [2018-11-23 09:52:18,817 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:18" (1/1) ... [2018-11-23 09:52:18,820 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:18" (1/1) ... [2018-11-23 09:52:18,825 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 09:52:18,825 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 09:52:18,825 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 09:52:18,825 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 09:52:18,826 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:18" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 09:52:18,876 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 09:52:18,876 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 09:52:18,876 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-23 09:52:18,876 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-11-23 09:52:18,876 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 09:52:18,877 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 09:52:18,877 INFO L130 BoogieDeclarations]: Found specification of procedure my_callback [2018-11-23 09:52:18,877 INFO L138 BoogieDeclarations]: Found implementation of procedure my_callback [2018-11-23 09:52:18,877 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 09:52:18,877 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-11-23 09:52:18,878 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-23 09:52:19,399 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 09:52:19,399 INFO L280 CfgBuilder]: Removed 24 assue(true) statements. [2018-11-23 09:52:19,400 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 09:52:19 BoogieIcfgContainer [2018-11-23 09:52:19,400 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 09:52:19,400 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 09:52:19,401 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 09:52:19,403 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 09:52:19,403 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 09:52:17" (1/3) ... [2018-11-23 09:52:19,405 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@50a51129 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 09:52:19, skipping insertion in model container [2018-11-23 09:52:19,405 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 09:52:18" (2/3) ... [2018-11-23 09:52:19,405 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@50a51129 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 09:52:19, skipping insertion in model container [2018-11-23 09:52:19,405 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 09:52:19" (3/3) ... [2018-11-23 09:52:19,407 INFO L112 eAbstractionObserver]: Analyzing ICFG race-3_2-container_of-global_false-unreach-call.i [2018-11-23 09:52:19,431 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,431 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,431 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,431 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,431 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,432 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,432 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~__mptr~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,432 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~__mptr~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,432 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~__mptr~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,432 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~__mptr~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,432 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,433 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,433 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,433 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,433 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,434 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,434 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,434 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,435 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,435 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,435 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,435 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,435 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,436 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,436 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,436 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,436 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,436 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,437 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,437 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~__mptr~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,437 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~__mptr~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,437 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~__mptr~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,437 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~__mptr~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,437 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,438 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,438 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,438 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,438 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,439 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,439 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,439 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,439 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,439 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,439 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,440 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,440 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 09:52:19,457 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-23 09:52:19,458 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 09:52:19,463 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2018-11-23 09:52:19,474 INFO L257 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2018-11-23 09:52:19,492 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 09:52:19,493 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 09:52:19,493 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 09:52:19,493 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 09:52:19,493 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 09:52:19,493 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 09:52:19,493 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 09:52:19,494 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 09:52:19,494 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 09:52:19,503 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 137places, 145 transitions [2018-11-23 09:52:19,628 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 4725 states. [2018-11-23 09:52:19,631 INFO L276 IsEmpty]: Start isEmpty. Operand 4725 states. [2018-11-23 09:52:19,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-11-23 09:52:19,638 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:19,639 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:19,641 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:19,646 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:19,646 INFO L82 PathProgramCache]: Analyzing trace with hash 441784776, now seen corresponding path program 1 times [2018-11-23 09:52:19,648 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:19,648 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:19,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:19,739 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:52:19,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:19,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:19,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:19,954 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:19,954 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 09:52:19,957 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 09:52:19,965 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 09:52:19,966 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 09:52:19,967 INFO L87 Difference]: Start difference. First operand 4725 states. Second operand 6 states. [2018-11-23 09:52:20,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:20,295 INFO L93 Difference]: Finished difference Result 4724 states and 12876 transitions. [2018-11-23 09:52:20,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 09:52:20,296 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2018-11-23 09:52:20,297 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:20,318 INFO L225 Difference]: With dead ends: 4724 [2018-11-23 09:52:20,318 INFO L226 Difference]: Without dead ends: 3864 [2018-11-23 09:52:20,320 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=39, Invalid=71, Unknown=0, NotChecked=0, Total=110 [2018-11-23 09:52:20,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3864 states. [2018-11-23 09:52:20,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3864 to 3863. [2018-11-23 09:52:20,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3863 states. [2018-11-23 09:52:20,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3863 states to 3863 states and 10474 transitions. [2018-11-23 09:52:20,440 INFO L78 Accepts]: Start accepts. Automaton has 3863 states and 10474 transitions. Word has length 31 [2018-11-23 09:52:20,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:20,441 INFO L480 AbstractCegarLoop]: Abstraction has 3863 states and 10474 transitions. [2018-11-23 09:52:20,441 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 09:52:20,441 INFO L276 IsEmpty]: Start isEmpty. Operand 3863 states and 10474 transitions. [2018-11-23 09:52:20,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-11-23 09:52:20,442 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:20,442 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:20,442 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:20,442 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:20,443 INFO L82 PathProgramCache]: Analyzing trace with hash -804856226, now seen corresponding path program 1 times [2018-11-23 09:52:20,443 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:20,443 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:20,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:20,490 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:52:20,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:20,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:20,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:20,657 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:20,657 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 09:52:20,658 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 09:52:20,658 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 09:52:20,658 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-23 09:52:20,659 INFO L87 Difference]: Start difference. First operand 3863 states and 10474 transitions. Second operand 8 states. [2018-11-23 09:52:21,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:21,058 INFO L93 Difference]: Finished difference Result 3865 states and 10476 transitions. [2018-11-23 09:52:21,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 09:52:21,059 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 37 [2018-11-23 09:52:21,059 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:21,067 INFO L225 Difference]: With dead ends: 3865 [2018-11-23 09:52:21,067 INFO L226 Difference]: Without dead ends: 3865 [2018-11-23 09:52:21,068 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=70, Invalid=140, Unknown=0, NotChecked=0, Total=210 [2018-11-23 09:52:21,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3865 states. [2018-11-23 09:52:21,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3865 to 3861. [2018-11-23 09:52:21,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3861 states. [2018-11-23 09:52:21,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3861 states to 3861 states and 10472 transitions. [2018-11-23 09:52:21,119 INFO L78 Accepts]: Start accepts. Automaton has 3861 states and 10472 transitions. Word has length 37 [2018-11-23 09:52:21,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:21,120 INFO L480 AbstractCegarLoop]: Abstraction has 3861 states and 10472 transitions. [2018-11-23 09:52:21,120 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 09:52:21,120 INFO L276 IsEmpty]: Start isEmpty. Operand 3861 states and 10472 transitions. [2018-11-23 09:52:21,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-11-23 09:52:21,122 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:21,122 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:21,122 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:21,122 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:21,122 INFO L82 PathProgramCache]: Analyzing trace with hash 1378309502, now seen corresponding path program 1 times [2018-11-23 09:52:21,123 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:21,123 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:21,130 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:21,130 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:52:21,130 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:21,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:21,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:21,274 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:21,275 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 09:52:21,275 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 09:52:21,275 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 09:52:21,275 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-11-23 09:52:21,275 INFO L87 Difference]: Start difference. First operand 3861 states and 10472 transitions. Second operand 8 states. [2018-11-23 09:52:22,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:22,011 INFO L93 Difference]: Finished difference Result 5825 states and 15810 transitions. [2018-11-23 09:52:22,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 09:52:22,011 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 55 [2018-11-23 09:52:22,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:22,027 INFO L225 Difference]: With dead ends: 5825 [2018-11-23 09:52:22,027 INFO L226 Difference]: Without dead ends: 5825 [2018-11-23 09:52:22,028 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=131, Invalid=289, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:52:22,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5825 states. [2018-11-23 09:52:22,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5825 to 4385. [2018-11-23 09:52:22,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4385 states. [2018-11-23 09:52:22,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4385 states to 4385 states and 11916 transitions. [2018-11-23 09:52:22,097 INFO L78 Accepts]: Start accepts. Automaton has 4385 states and 11916 transitions. Word has length 55 [2018-11-23 09:52:22,097 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:22,097 INFO L480 AbstractCegarLoop]: Abstraction has 4385 states and 11916 transitions. [2018-11-23 09:52:22,097 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 09:52:22,097 INFO L276 IsEmpty]: Start isEmpty. Operand 4385 states and 11916 transitions. [2018-11-23 09:52:22,101 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-11-23 09:52:22,101 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:22,101 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:22,101 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:22,101 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:22,101 INFO L82 PathProgramCache]: Analyzing trace with hash -1957942992, now seen corresponding path program 1 times [2018-11-23 09:52:22,102 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:22,102 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:22,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:22,109 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:52:22,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:22,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:22,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:22,233 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:22,233 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 09:52:22,233 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 09:52:22,234 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 09:52:22,234 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-11-23 09:52:22,234 INFO L87 Difference]: Start difference. First operand 4385 states and 11916 transitions. Second operand 8 states. [2018-11-23 09:52:22,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:22,934 INFO L93 Difference]: Finished difference Result 6349 states and 17158 transitions. [2018-11-23 09:52:22,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 09:52:22,935 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 61 [2018-11-23 09:52:22,935 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:22,974 INFO L225 Difference]: With dead ends: 6349 [2018-11-23 09:52:22,975 INFO L226 Difference]: Without dead ends: 5317 [2018-11-23 09:52:22,975 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=107, Invalid=235, Unknown=0, NotChecked=0, Total=342 [2018-11-23 09:52:22,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5317 states. [2018-11-23 09:52:23,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5317 to 5125. [2018-11-23 09:52:23,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5125 states. [2018-11-23 09:52:23,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5125 states to 5125 states and 13985 transitions. [2018-11-23 09:52:23,070 INFO L78 Accepts]: Start accepts. Automaton has 5125 states and 13985 transitions. Word has length 61 [2018-11-23 09:52:23,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:23,071 INFO L480 AbstractCegarLoop]: Abstraction has 5125 states and 13985 transitions. [2018-11-23 09:52:23,071 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 09:52:23,071 INFO L276 IsEmpty]: Start isEmpty. Operand 5125 states and 13985 transitions. [2018-11-23 09:52:23,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-23 09:52:23,075 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:23,075 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:23,075 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:23,076 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:23,077 INFO L82 PathProgramCache]: Analyzing trace with hash -1563836415, now seen corresponding path program 1 times [2018-11-23 09:52:23,077 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:23,077 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:23,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:23,085 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:52:23,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:23,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:23,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:23,171 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:23,171 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 09:52:23,171 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 09:52:23,172 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 09:52:23,172 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 09:52:23,172 INFO L87 Difference]: Start difference. First operand 5125 states and 13985 transitions. Second operand 5 states. [2018-11-23 09:52:23,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:23,221 INFO L93 Difference]: Finished difference Result 1780 states and 4650 transitions. [2018-11-23 09:52:23,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 09:52:23,222 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 67 [2018-11-23 09:52:23,222 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:23,225 INFO L225 Difference]: With dead ends: 1780 [2018-11-23 09:52:23,225 INFO L226 Difference]: Without dead ends: 1780 [2018-11-23 09:52:23,226 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 09:52:23,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1780 states. [2018-11-23 09:52:23,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1780 to 1780. [2018-11-23 09:52:23,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1780 states. [2018-11-23 09:52:23,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1780 states to 1780 states and 4650 transitions. [2018-11-23 09:52:23,256 INFO L78 Accepts]: Start accepts. Automaton has 1780 states and 4650 transitions. Word has length 67 [2018-11-23 09:52:23,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:23,257 INFO L480 AbstractCegarLoop]: Abstraction has 1780 states and 4650 transitions. [2018-11-23 09:52:23,257 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 09:52:23,257 INFO L276 IsEmpty]: Start isEmpty. Operand 1780 states and 4650 transitions. [2018-11-23 09:52:23,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:52:23,260 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:23,261 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:23,261 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:23,261 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:23,261 INFO L82 PathProgramCache]: Analyzing trace with hash -1243979628, now seen corresponding path program 1 times [2018-11-23 09:52:23,262 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:23,262 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:23,271 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:23,272 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:52:23,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:23,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:24,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:24,023 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:24,023 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2018-11-23 09:52:24,024 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-23 09:52:24,024 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-23 09:52:24,024 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=266, Unknown=0, NotChecked=0, Total=306 [2018-11-23 09:52:24,024 INFO L87 Difference]: Start difference. First operand 1780 states and 4650 transitions. Second operand 18 states. [2018-11-23 09:52:24,877 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 36 [2018-11-23 09:52:25,020 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 40 [2018-11-23 09:52:25,184 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 45 [2018-11-23 09:52:25,440 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 33 [2018-11-23 09:52:25,561 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 35 [2018-11-23 09:52:26,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:26,226 INFO L93 Difference]: Finished difference Result 2172 states and 5448 transitions. [2018-11-23 09:52:26,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-23 09:52:26,226 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 96 [2018-11-23 09:52:26,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:26,229 INFO L225 Difference]: With dead ends: 2172 [2018-11-23 09:52:26,229 INFO L226 Difference]: Without dead ends: 2172 [2018-11-23 09:52:26,229 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 162 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=337, Invalid=923, Unknown=0, NotChecked=0, Total=1260 [2018-11-23 09:52:26,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2172 states. [2018-11-23 09:52:26,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2172 to 1942. [2018-11-23 09:52:26,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1942 states. [2018-11-23 09:52:26,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1942 states to 1942 states and 4978 transitions. [2018-11-23 09:52:26,249 INFO L78 Accepts]: Start accepts. Automaton has 1942 states and 4978 transitions. Word has length 96 [2018-11-23 09:52:26,249 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:26,249 INFO L480 AbstractCegarLoop]: Abstraction has 1942 states and 4978 transitions. [2018-11-23 09:52:26,249 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-23 09:52:26,249 INFO L276 IsEmpty]: Start isEmpty. Operand 1942 states and 4978 transitions. [2018-11-23 09:52:26,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:52:26,252 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:26,252 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:26,252 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:26,252 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:26,252 INFO L82 PathProgramCache]: Analyzing trace with hash -1707679114, now seen corresponding path program 2 times [2018-11-23 09:52:26,253 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:26,253 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:26,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:26,259 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:52:26,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:26,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:26,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:26,942 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:26,942 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2018-11-23 09:52:26,942 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-23 09:52:26,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-23 09:52:26,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=334, Unknown=0, NotChecked=0, Total=380 [2018-11-23 09:52:26,943 INFO L87 Difference]: Start difference. First operand 1942 states and 4978 transitions. Second operand 20 states. [2018-11-23 09:52:27,825 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 33 [2018-11-23 09:52:27,981 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 35 [2018-11-23 09:52:28,122 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 09:52:28,409 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 45 DAG size of output: 36 [2018-11-23 09:52:28,571 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 40 [2018-11-23 09:52:28,725 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 45 [2018-11-23 09:52:28,861 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 09:52:29,029 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 09:52:29,184 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 09:52:29,372 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 09:52:29,539 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 47 [2018-11-23 09:52:29,727 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 09:52:30,067 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 41 [2018-11-23 09:52:30,220 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 43 [2018-11-23 09:52:30,368 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 09:52:30,491 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 40 [2018-11-23 09:52:30,819 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 40 [2018-11-23 09:52:31,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:31,043 INFO L93 Difference]: Finished difference Result 2544 states and 6190 transitions. [2018-11-23 09:52:31,043 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-11-23 09:52:31,044 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 96 [2018-11-23 09:52:31,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:31,047 INFO L225 Difference]: With dead ends: 2544 [2018-11-23 09:52:31,047 INFO L226 Difference]: Without dead ends: 2544 [2018-11-23 09:52:31,048 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 300 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=632, Invalid=1624, Unknown=0, NotChecked=0, Total=2256 [2018-11-23 09:52:31,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2544 states. [2018-11-23 09:52:31,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2544 to 1915. [2018-11-23 09:52:31,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1915 states. [2018-11-23 09:52:31,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1915 states to 1915 states and 4915 transitions. [2018-11-23 09:52:31,069 INFO L78 Accepts]: Start accepts. Automaton has 1915 states and 4915 transitions. Word has length 96 [2018-11-23 09:52:31,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:31,070 INFO L480 AbstractCegarLoop]: Abstraction has 1915 states and 4915 transitions. [2018-11-23 09:52:31,070 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-23 09:52:31,070 INFO L276 IsEmpty]: Start isEmpty. Operand 1915 states and 4915 transitions. [2018-11-23 09:52:31,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:52:31,072 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:31,073 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:31,073 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:31,073 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:31,073 INFO L82 PathProgramCache]: Analyzing trace with hash 1355459034, now seen corresponding path program 3 times [2018-11-23 09:52:31,073 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:31,073 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:31,079 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:31,079 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:52:31,079 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:31,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:31,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:31,726 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:31,726 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2018-11-23 09:52:31,726 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-23 09:52:31,727 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-23 09:52:31,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=266, Unknown=0, NotChecked=0, Total=306 [2018-11-23 09:52:31,727 INFO L87 Difference]: Start difference. First operand 1915 states and 4915 transitions. Second operand 18 states. [2018-11-23 09:52:32,474 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 38 [2018-11-23 09:52:32,617 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 42 [2018-11-23 09:52:32,866 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 41 [2018-11-23 09:52:33,007 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 46 [2018-11-23 09:52:33,287 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 44 [2018-11-23 09:52:33,425 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 09:52:33,543 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 40 [2018-11-23 09:52:33,871 WARN L180 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 40 [2018-11-23 09:52:34,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:34,078 INFO L93 Difference]: Finished difference Result 2557 states and 6323 transitions. [2018-11-23 09:52:34,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-23 09:52:34,078 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 96 [2018-11-23 09:52:34,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:34,081 INFO L225 Difference]: With dead ends: 2557 [2018-11-23 09:52:34,081 INFO L226 Difference]: Without dead ends: 2557 [2018-11-23 09:52:34,082 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=359, Invalid=901, Unknown=0, NotChecked=0, Total=1260 [2018-11-23 09:52:34,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2557 states. [2018-11-23 09:52:34,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2557 to 2152. [2018-11-23 09:52:34,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2152 states. [2018-11-23 09:52:34,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2152 states to 2152 states and 5534 transitions. [2018-11-23 09:52:34,106 INFO L78 Accepts]: Start accepts. Automaton has 2152 states and 5534 transitions. Word has length 96 [2018-11-23 09:52:34,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:34,106 INFO L480 AbstractCegarLoop]: Abstraction has 2152 states and 5534 transitions. [2018-11-23 09:52:34,107 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-23 09:52:34,107 INFO L276 IsEmpty]: Start isEmpty. Operand 2152 states and 5534 transitions. [2018-11-23 09:52:34,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:52:34,109 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:34,109 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:34,109 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:34,110 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:34,111 INFO L82 PathProgramCache]: Analyzing trace with hash 449789656, now seen corresponding path program 4 times [2018-11-23 09:52:34,111 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:34,111 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:34,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:34,116 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:52:34,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:34,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:35,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:35,064 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:35,064 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:52:35,065 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:52:35,065 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:52:35,065 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:52:35,065 INFO L87 Difference]: Start difference. First operand 2152 states and 5534 transitions. Second operand 21 states. [2018-11-23 09:52:35,720 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:52:35,861 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 09:52:36,016 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 43 [2018-11-23 09:52:36,429 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 42 [2018-11-23 09:52:36,590 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 46 [2018-11-23 09:52:36,797 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 46 [2018-11-23 09:52:36,976 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 50 [2018-11-23 09:52:37,166 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 51 [2018-11-23 09:52:37,375 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 61 [2018-11-23 09:52:37,731 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 45 [2018-11-23 09:52:37,944 WARN L180 SmtUtils]: Spent 175.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 09:52:38,107 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 42 [2018-11-23 09:52:38,510 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 09:52:38,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:38,768 INFO L93 Difference]: Finished difference Result 3287 states and 7934 transitions. [2018-11-23 09:52:38,769 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-23 09:52:38,769 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:52:38,769 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:38,771 INFO L225 Difference]: With dead ends: 3287 [2018-11-23 09:52:38,771 INFO L226 Difference]: Without dead ends: 3287 [2018-11-23 09:52:38,772 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 248 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=486, Invalid=1320, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 09:52:38,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3287 states. [2018-11-23 09:52:38,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3287 to 2329. [2018-11-23 09:52:38,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2329 states. [2018-11-23 09:52:38,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2329 states to 2329 states and 5985 transitions. [2018-11-23 09:52:38,801 INFO L78 Accepts]: Start accepts. Automaton has 2329 states and 5985 transitions. Word has length 96 [2018-11-23 09:52:38,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:38,803 INFO L480 AbstractCegarLoop]: Abstraction has 2329 states and 5985 transitions. [2018-11-23 09:52:38,803 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:52:38,803 INFO L276 IsEmpty]: Start isEmpty. Operand 2329 states and 5985 transitions. [2018-11-23 09:52:38,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:52:38,807 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:38,807 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:38,807 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:38,807 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:38,807 INFO L82 PathProgramCache]: Analyzing trace with hash -1754005574, now seen corresponding path program 5 times [2018-11-23 09:52:38,808 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:38,808 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:38,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:38,815 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:52:38,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:38,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:39,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:39,727 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:39,727 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:52:39,727 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:52:39,727 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:52:39,728 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:52:39,728 INFO L87 Difference]: Start difference. First operand 2329 states and 5985 transitions. Second operand 21 states. [2018-11-23 09:52:40,363 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:52:40,502 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 09:52:40,655 WARN L180 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 43 [2018-11-23 09:52:40,874 WARN L180 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 43 [2018-11-23 09:52:41,046 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 47 [2018-11-23 09:52:41,374 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 46 [2018-11-23 09:52:41,586 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 46 [2018-11-23 09:52:41,759 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 50 [2018-11-23 09:52:41,956 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 51 [2018-11-23 09:52:42,169 WARN L180 SmtUtils]: Spent 174.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 61 [2018-11-23 09:52:42,558 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 09:52:42,714 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 45 [2018-11-23 09:52:42,886 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 48 [2018-11-23 09:52:43,040 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 09:52:43,184 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 46 [2018-11-23 09:52:43,429 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 42 [2018-11-23 09:52:43,726 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 46 [2018-11-23 09:52:43,868 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 09:52:44,212 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 49 [2018-11-23 09:52:44,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:44,333 INFO L93 Difference]: Finished difference Result 5310 states and 12783 transitions. [2018-11-23 09:52:44,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-11-23 09:52:44,333 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:52:44,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:44,344 INFO L225 Difference]: With dead ends: 5310 [2018-11-23 09:52:44,344 INFO L226 Difference]: Without dead ends: 5310 [2018-11-23 09:52:44,345 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 401 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=665, Invalid=1785, Unknown=0, NotChecked=0, Total=2450 [2018-11-23 09:52:44,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5310 states. [2018-11-23 09:52:44,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5310 to 2362. [2018-11-23 09:52:44,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2362 states. [2018-11-23 09:52:44,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2362 states to 2362 states and 6084 transitions. [2018-11-23 09:52:44,392 INFO L78 Accepts]: Start accepts. Automaton has 2362 states and 6084 transitions. Word has length 96 [2018-11-23 09:52:44,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:44,393 INFO L480 AbstractCegarLoop]: Abstraction has 2362 states and 6084 transitions. [2018-11-23 09:52:44,393 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:52:44,393 INFO L276 IsEmpty]: Start isEmpty. Operand 2362 states and 6084 transitions. [2018-11-23 09:52:44,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:52:44,396 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:44,396 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:44,397 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:44,397 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:44,397 INFO L82 PathProgramCache]: Analyzing trace with hash 1290945078, now seen corresponding path program 6 times [2018-11-23 09:52:44,397 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:44,397 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:44,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:44,405 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:52:44,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:44,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:45,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:45,348 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:45,348 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:52:45,349 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:52:45,349 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:52:45,349 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:52:45,349 INFO L87 Difference]: Start difference. First operand 2362 states and 6084 transitions. Second operand 21 states. [2018-11-23 09:52:45,764 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 24 [2018-11-23 09:52:46,037 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:52:46,181 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 09:52:46,336 WARN L180 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 43 [2018-11-23 09:52:46,581 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 43 [2018-11-23 09:52:46,758 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 47 [2018-11-23 09:52:46,939 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 48 [2018-11-23 09:52:47,145 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 52 [2018-11-23 09:52:47,473 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 46 [2018-11-23 09:52:47,704 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 09:52:47,963 WARN L180 SmtUtils]: Spent 212.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 51 [2018-11-23 09:52:48,188 WARN L180 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 61 [2018-11-23 09:52:48,587 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 54 [2018-11-23 09:52:48,747 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 45 [2018-11-23 09:52:48,937 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 52 [2018-11-23 09:52:49,089 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 09:52:49,250 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 50 [2018-11-23 09:52:49,377 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 42 [2018-11-23 09:52:49,571 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 50 [2018-11-23 09:52:49,712 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 09:52:50,069 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 09:52:50,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:50,188 INFO L93 Difference]: Finished difference Result 4637 states and 11344 transitions. [2018-11-23 09:52:50,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-11-23 09:52:50,188 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:52:50,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:50,193 INFO L225 Difference]: With dead ends: 4637 [2018-11-23 09:52:50,193 INFO L226 Difference]: Without dead ends: 4637 [2018-11-23 09:52:50,194 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 350 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=651, Invalid=1701, Unknown=0, NotChecked=0, Total=2352 [2018-11-23 09:52:50,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4637 states. [2018-11-23 09:52:50,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4637 to 2461. [2018-11-23 09:52:50,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2461 states. [2018-11-23 09:52:50,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2461 states to 2461 states and 6381 transitions. [2018-11-23 09:52:50,225 INFO L78 Accepts]: Start accepts. Automaton has 2461 states and 6381 transitions. Word has length 96 [2018-11-23 09:52:50,225 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:50,225 INFO L480 AbstractCegarLoop]: Abstraction has 2461 states and 6381 transitions. [2018-11-23 09:52:50,225 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:52:50,225 INFO L276 IsEmpty]: Start isEmpty. Operand 2461 states and 6381 transitions. [2018-11-23 09:52:50,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:52:50,228 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:50,228 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:50,228 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:50,228 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:50,229 INFO L82 PathProgramCache]: Analyzing trace with hash -1220162766, now seen corresponding path program 7 times [2018-11-23 09:52:50,229 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:50,229 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:50,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:50,234 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:52:50,234 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:50,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:51,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:51,155 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:51,155 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:52:51,156 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:52:51,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:52:51,156 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:52:51,156 INFO L87 Difference]: Start difference. First operand 2461 states and 6381 transitions. Second operand 21 states. [2018-11-23 09:52:51,809 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:52:52,107 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 09:52:52,265 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 42 [2018-11-23 09:52:52,428 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 46 [2018-11-23 09:52:52,626 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 46 [2018-11-23 09:52:52,809 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 09:52:52,997 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 51 [2018-11-23 09:52:53,208 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 61 [2018-11-23 09:52:53,531 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 09:52:53,680 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 09:52:53,827 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 09:52:54,281 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 09:52:54,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:54,525 INFO L93 Difference]: Finished difference Result 3589 states and 8624 transitions. [2018-11-23 09:52:54,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-23 09:52:54,525 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:52:54,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:54,529 INFO L225 Difference]: With dead ends: 3589 [2018-11-23 09:52:54,529 INFO L226 Difference]: Without dead ends: 3589 [2018-11-23 09:52:54,530 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 247 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=474, Invalid=1332, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 09:52:54,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3589 states. [2018-11-23 09:52:54,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3589 to 2488. [2018-11-23 09:52:54,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2488 states. [2018-11-23 09:52:54,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2488 states to 2488 states and 6444 transitions. [2018-11-23 09:52:54,553 INFO L78 Accepts]: Start accepts. Automaton has 2488 states and 6444 transitions. Word has length 96 [2018-11-23 09:52:54,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:54,554 INFO L480 AbstractCegarLoop]: Abstraction has 2488 states and 6444 transitions. [2018-11-23 09:52:54,554 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:52:54,554 INFO L276 IsEmpty]: Start isEmpty. Operand 2488 states and 6444 transitions. [2018-11-23 09:52:54,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:52:54,557 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:54,557 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:54,558 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:54,558 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:54,558 INFO L82 PathProgramCache]: Analyzing trace with hash -410312364, now seen corresponding path program 8 times [2018-11-23 09:52:54,558 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:54,558 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:54,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:54,564 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:52:54,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:54,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:55,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:55,547 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:55,547 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:52:55,547 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:52:55,547 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:52:55,547 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:52:55,547 INFO L87 Difference]: Start difference. First operand 2488 states and 6444 transitions. Second operand 21 states. [2018-11-23 09:52:56,218 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:52:56,463 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 09:52:56,639 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 09:52:56,814 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 47 [2018-11-23 09:52:57,003 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 51 [2018-11-23 09:52:57,191 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 51 [2018-11-23 09:52:57,405 WARN L180 SmtUtils]: Spent 176.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 61 [2018-11-23 09:52:57,724 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 09:52:57,872 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 09:52:58,019 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 09:52:58,479 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 09:52:58,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:52:58,739 INFO L93 Difference]: Finished difference Result 3752 states and 8953 transitions. [2018-11-23 09:52:58,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 09:52:58,739 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:52:58,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:52:58,743 INFO L225 Difference]: With dead ends: 3752 [2018-11-23 09:52:58,743 INFO L226 Difference]: Without dead ends: 3752 [2018-11-23 09:52:58,743 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 230 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=444, Invalid=1278, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:52:58,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3752 states. [2018-11-23 09:52:58,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3752 to 2490. [2018-11-23 09:52:58,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2490 states. [2018-11-23 09:52:58,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2490 states to 2490 states and 6449 transitions. [2018-11-23 09:52:58,783 INFO L78 Accepts]: Start accepts. Automaton has 2490 states and 6449 transitions. Word has length 96 [2018-11-23 09:52:58,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:52:58,783 INFO L480 AbstractCegarLoop]: Abstraction has 2490 states and 6449 transitions. [2018-11-23 09:52:58,783 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:52:58,783 INFO L276 IsEmpty]: Start isEmpty. Operand 2490 states and 6449 transitions. [2018-11-23 09:52:58,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:52:58,786 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:52:58,787 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:52:58,787 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:52:58,787 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:52:58,787 INFO L82 PathProgramCache]: Analyzing trace with hash -487269194, now seen corresponding path program 9 times [2018-11-23 09:52:58,787 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:52:58,787 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:52:58,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:58,793 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:52:58,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:52:58,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:52:59,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:52:59,740 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:52:59,740 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:52:59,740 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:52:59,740 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:52:59,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:52:59,740 INFO L87 Difference]: Start difference. First operand 2490 states and 6449 transitions. Second operand 21 states. [2018-11-23 09:53:00,389 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:53:00,659 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 09:53:00,835 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 42 [2018-11-23 09:53:01,032 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 09:53:01,235 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 09:53:01,427 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 09:53:01,645 WARN L180 SmtUtils]: Spent 185.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 62 [2018-11-23 09:53:01,976 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 09:53:02,120 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 09:53:02,266 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 09:53:02,706 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 09:53:02,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:02,932 INFO L93 Difference]: Finished difference Result 3457 states and 8359 transitions. [2018-11-23 09:53:02,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 09:53:02,932 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:02,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:02,934 INFO L225 Difference]: With dead ends: 3457 [2018-11-23 09:53:02,934 INFO L226 Difference]: Without dead ends: 3457 [2018-11-23 09:53:02,935 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 231 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=445, Invalid=1277, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:53:02,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3457 states. [2018-11-23 09:53:02,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3457 to 2496. [2018-11-23 09:53:02,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2496 states. [2018-11-23 09:53:02,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2496 states to 2496 states and 6464 transitions. [2018-11-23 09:53:02,965 INFO L78 Accepts]: Start accepts. Automaton has 2496 states and 6464 transitions. Word has length 96 [2018-11-23 09:53:02,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:02,965 INFO L480 AbstractCegarLoop]: Abstraction has 2496 states and 6464 transitions. [2018-11-23 09:53:02,966 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:02,966 INFO L276 IsEmpty]: Start isEmpty. Operand 2496 states and 6464 transitions. [2018-11-23 09:53:02,969 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:02,969 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:02,969 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:02,969 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:02,969 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:02,969 INFO L82 PathProgramCache]: Analyzing trace with hash 1248556006, now seen corresponding path program 10 times [2018-11-23 09:53:02,969 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:02,970 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:02,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:02,974 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:53:02,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:02,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:03,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:03,999 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:03,999 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:03,999 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:03,999 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:04,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:04,000 INFO L87 Difference]: Start difference. First operand 2496 states and 6464 transitions. Second operand 21 states. [2018-11-23 09:53:04,698 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:53:04,903 WARN L180 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 09:53:05,070 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 44 [2018-11-23 09:53:05,262 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 48 [2018-11-23 09:53:05,633 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 47 [2018-11-23 09:53:05,812 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 51 [2018-11-23 09:53:06,002 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 51 [2018-11-23 09:53:06,211 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 61 [2018-11-23 09:53:06,614 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 50 [2018-11-23 09:53:06,790 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 48 [2018-11-23 09:53:06,945 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 47 [2018-11-23 09:53:07,174 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 46 [2018-11-23 09:53:07,351 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 46 [2018-11-23 09:53:07,619 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 50 [2018-11-23 09:53:07,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:07,630 INFO L93 Difference]: Finished difference Result 5854 states and 14349 transitions. [2018-11-23 09:53:07,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 09:53:07,630 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:07,630 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:07,634 INFO L225 Difference]: With dead ends: 5854 [2018-11-23 09:53:07,634 INFO L226 Difference]: Without dead ends: 5854 [2018-11-23 09:53:07,634 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 213 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=466, Invalid=1256, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:53:07,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5854 states. [2018-11-23 09:53:07,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5854 to 2540. [2018-11-23 09:53:07,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2540 states. [2018-11-23 09:53:07,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2540 states to 2540 states and 6596 transitions. [2018-11-23 09:53:07,665 INFO L78 Accepts]: Start accepts. Automaton has 2540 states and 6596 transitions. Word has length 96 [2018-11-23 09:53:07,665 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:07,666 INFO L480 AbstractCegarLoop]: Abstraction has 2540 states and 6596 transitions. [2018-11-23 09:53:07,666 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:07,666 INFO L276 IsEmpty]: Start isEmpty. Operand 2540 states and 6596 transitions. [2018-11-23 09:53:07,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:07,668 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:07,668 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:07,669 INFO L423 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:07,669 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:07,669 INFO L82 PathProgramCache]: Analyzing trace with hash -1460638, now seen corresponding path program 11 times [2018-11-23 09:53:07,669 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:07,669 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:07,672 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:07,672 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:53:07,672 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:07,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:08,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:08,514 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:08,515 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:08,515 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:08,515 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:08,515 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:08,515 INFO L87 Difference]: Start difference. First operand 2540 states and 6596 transitions. Second operand 21 states. [2018-11-23 09:53:09,247 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:53:09,465 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 09:53:09,635 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 44 [2018-11-23 09:53:09,836 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 48 [2018-11-23 09:53:10,011 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 48 [2018-11-23 09:53:10,229 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 52 [2018-11-23 09:53:10,656 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 51 [2018-11-23 09:53:10,844 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 51 [2018-11-23 09:53:11,078 WARN L180 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 61 [2018-11-23 09:53:11,522 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 54 [2018-11-23 09:53:11,693 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 50 [2018-11-23 09:53:11,886 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 52 [2018-11-23 09:53:12,057 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 48 [2018-11-23 09:53:12,231 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 50 [2018-11-23 09:53:12,412 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 47 [2018-11-23 09:53:12,625 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 50 [2018-11-23 09:53:12,846 WARN L180 SmtUtils]: Spent 201.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 46 [2018-11-23 09:53:12,997 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 09:53:13,174 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 46 [2018-11-23 09:53:13,347 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 53 [2018-11-23 09:53:13,505 WARN L180 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 50 [2018-11-23 09:53:13,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:13,519 INFO L93 Difference]: Finished difference Result 6960 states and 17185 transitions. [2018-11-23 09:53:13,519 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-23 09:53:13,519 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:13,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:13,525 INFO L225 Difference]: With dead ends: 6960 [2018-11-23 09:53:13,525 INFO L226 Difference]: Without dead ends: 6960 [2018-11-23 09:53:13,526 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 292 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=604, Invalid=1558, Unknown=0, NotChecked=0, Total=2162 [2018-11-23 09:53:13,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6960 states. [2018-11-23 09:53:13,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6960 to 2507. [2018-11-23 09:53:13,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2507 states. [2018-11-23 09:53:13,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2507 states to 2507 states and 6497 transitions. [2018-11-23 09:53:13,572 INFO L78 Accepts]: Start accepts. Automaton has 2507 states and 6497 transitions. Word has length 96 [2018-11-23 09:53:13,572 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:13,572 INFO L480 AbstractCegarLoop]: Abstraction has 2507 states and 6497 transitions. [2018-11-23 09:53:13,572 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:13,572 INFO L276 IsEmpty]: Start isEmpty. Operand 2507 states and 6497 transitions. [2018-11-23 09:53:13,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:13,575 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:13,575 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:13,575 INFO L423 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:13,575 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:13,576 INFO L82 PathProgramCache]: Analyzing trace with hash -803922638, now seen corresponding path program 12 times [2018-11-23 09:53:13,576 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:13,576 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:13,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:13,579 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:53:13,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:13,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:14,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:14,489 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:14,489 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:14,489 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:14,489 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:14,490 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:14,490 INFO L87 Difference]: Start difference. First operand 2507 states and 6497 transitions. Second operand 21 states. [2018-11-23 09:53:15,149 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:53:15,348 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 09:53:15,627 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 09:53:15,801 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 47 [2018-11-23 09:53:15,990 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 51 [2018-11-23 09:53:16,178 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 51 [2018-11-23 09:53:16,394 WARN L180 SmtUtils]: Spent 176.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 61 [2018-11-23 09:53:16,768 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 43 [2018-11-23 09:53:16,956 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 45 [2018-11-23 09:53:17,118 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 44 [2018-11-23 09:53:17,347 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 42 [2018-11-23 09:53:17,643 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 42 [2018-11-23 09:53:17,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:17,921 INFO L93 Difference]: Finished difference Result 4983 states and 12154 transitions. [2018-11-23 09:53:17,921 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 09:53:17,921 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:17,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:17,925 INFO L225 Difference]: With dead ends: 4983 [2018-11-23 09:53:17,925 INFO L226 Difference]: Without dead ends: 4983 [2018-11-23 09:53:17,925 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 224 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=455, Invalid=1267, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:53:17,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4983 states. [2018-11-23 09:53:17,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4983 to 2509. [2018-11-23 09:53:17,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2509 states. [2018-11-23 09:53:17,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2509 states to 2509 states and 6502 transitions. [2018-11-23 09:53:17,961 INFO L78 Accepts]: Start accepts. Automaton has 2509 states and 6502 transitions. Word has length 96 [2018-11-23 09:53:17,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:17,962 INFO L480 AbstractCegarLoop]: Abstraction has 2509 states and 6502 transitions. [2018-11-23 09:53:17,962 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:17,962 INFO L276 IsEmpty]: Start isEmpty. Operand 2509 states and 6502 transitions. [2018-11-23 09:53:17,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:17,964 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:17,964 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:17,964 INFO L423 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:17,964 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:17,964 INFO L82 PathProgramCache]: Analyzing trace with hash -880879468, now seen corresponding path program 13 times [2018-11-23 09:53:17,964 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:17,964 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:17,969 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:17,969 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:53:17,969 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:17,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:18,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:18,920 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:18,920 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:18,920 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:18,921 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:18,921 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:18,921 INFO L87 Difference]: Start difference. First operand 2509 states and 6502 transitions. Second operand 21 states. [2018-11-23 09:53:19,608 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:53:19,808 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 39 [2018-11-23 09:53:20,108 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 42 [2018-11-23 09:53:20,302 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 09:53:20,504 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 09:53:20,696 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 09:53:20,918 WARN L180 SmtUtils]: Spent 187.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 62 [2018-11-23 09:53:21,287 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 43 [2018-11-23 09:53:21,463 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 45 [2018-11-23 09:53:21,627 WARN L180 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 44 [2018-11-23 09:53:21,764 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 42 [2018-11-23 09:53:22,138 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 42 [2018-11-23 09:53:22,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:22,395 INFO L93 Difference]: Finished difference Result 4880 states and 11957 transitions. [2018-11-23 09:53:22,396 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 09:53:22,396 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:22,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:22,399 INFO L225 Difference]: With dead ends: 4880 [2018-11-23 09:53:22,399 INFO L226 Difference]: Without dead ends: 4880 [2018-11-23 09:53:22,399 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 225 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=456, Invalid=1266, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:53:22,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4880 states. [2018-11-23 09:53:22,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4880 to 2507. [2018-11-23 09:53:22,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2507 states. [2018-11-23 09:53:22,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2507 states to 2507 states and 6497 transitions. [2018-11-23 09:53:22,435 INFO L78 Accepts]: Start accepts. Automaton has 2507 states and 6497 transitions. Word has length 96 [2018-11-23 09:53:22,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:22,435 INFO L480 AbstractCegarLoop]: Abstraction has 2507 states and 6497 transitions. [2018-11-23 09:53:22,435 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:22,435 INFO L276 IsEmpty]: Start isEmpty. Operand 2507 states and 6497 transitions. [2018-11-23 09:53:22,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:22,437 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:22,438 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:22,438 INFO L423 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:22,438 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:22,438 INFO L82 PathProgramCache]: Analyzing trace with hash 1205381460, now seen corresponding path program 14 times [2018-11-23 09:53:22,438 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:22,438 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:22,441 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:22,442 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:53:22,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:22,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:23,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:23,364 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:23,364 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:23,364 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:23,364 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:23,364 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:23,364 INFO L87 Difference]: Start difference. First operand 2507 states and 6497 transitions. Second operand 21 states. [2018-11-23 09:53:24,037 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:53:24,254 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 39 [2018-11-23 09:53:24,432 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 43 [2018-11-23 09:53:24,636 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 09:53:24,822 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 09:53:25,056 WARN L180 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 54 [2018-11-23 09:53:25,510 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 53 [2018-11-23 09:53:25,699 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 53 [2018-11-23 09:53:25,914 WARN L180 SmtUtils]: Spent 182.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 62 [2018-11-23 09:53:26,369 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 52 [2018-11-23 09:53:26,574 WARN L180 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 56 [2018-11-23 09:53:26,764 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 50 [2018-11-23 09:53:26,966 WARN L180 SmtUtils]: Spent 178.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 54 [2018-11-23 09:53:27,128 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 48 [2018-11-23 09:53:27,300 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 52 [2018-11-23 09:53:27,500 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 48 [2018-11-23 09:53:27,692 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 52 [2018-11-23 09:53:27,956 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 51 [2018-11-23 09:53:28,089 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 09:53:28,233 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 55 [2018-11-23 09:53:28,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:28,250 INFO L93 Difference]: Finished difference Result 5593 states and 13805 transitions. [2018-11-23 09:53:28,250 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-23 09:53:28,250 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:28,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:28,253 INFO L225 Difference]: With dead ends: 5593 [2018-11-23 09:53:28,253 INFO L226 Difference]: Without dead ends: 5593 [2018-11-23 09:53:28,254 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 287 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=605, Invalid=1557, Unknown=0, NotChecked=0, Total=2162 [2018-11-23 09:53:28,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5593 states. [2018-11-23 09:53:28,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5593 to 2540. [2018-11-23 09:53:28,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2540 states. [2018-11-23 09:53:28,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2540 states to 2540 states and 6596 transitions. [2018-11-23 09:53:28,281 INFO L78 Accepts]: Start accepts. Automaton has 2540 states and 6596 transitions. Word has length 96 [2018-11-23 09:53:28,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:28,282 INFO L480 AbstractCegarLoop]: Abstraction has 2540 states and 6596 transitions. [2018-11-23 09:53:28,282 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:28,282 INFO L276 IsEmpty]: Start isEmpty. Operand 2540 states and 6596 transitions. [2018-11-23 09:53:28,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:28,284 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:28,284 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:28,284 INFO L423 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:28,284 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:28,284 INFO L82 PathProgramCache]: Analyzing trace with hash 1693361800, now seen corresponding path program 15 times [2018-11-23 09:53:28,284 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:28,284 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:28,288 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:28,288 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:53:28,288 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:28,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:29,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:29,224 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:29,224 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:29,225 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:29,225 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:29,225 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:29,225 INFO L87 Difference]: Start difference. First operand 2540 states and 6596 transitions. Second operand 21 states. [2018-11-23 09:53:29,869 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:53:30,067 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 39 [2018-11-23 09:53:30,240 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 43 [2018-11-23 09:53:30,442 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 09:53:30,774 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 49 [2018-11-23 09:53:30,972 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 53 [2018-11-23 09:53:31,165 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 53 [2018-11-23 09:53:31,386 WARN L180 SmtUtils]: Spent 186.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 62 [2018-11-23 09:53:31,768 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 52 [2018-11-23 09:53:31,958 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 50 [2018-11-23 09:53:32,122 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 48 [2018-11-23 09:53:32,533 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 48 [2018-11-23 09:53:32,814 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 09:53:32,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:32,824 INFO L93 Difference]: Finished difference Result 4425 states and 10876 transitions. [2018-11-23 09:53:32,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 09:53:32,825 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:32,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:32,827 INFO L225 Difference]: With dead ends: 4425 [2018-11-23 09:53:32,827 INFO L226 Difference]: Without dead ends: 4425 [2018-11-23 09:53:32,828 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 218 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=467, Invalid=1255, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:53:32,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4425 states. [2018-11-23 09:53:32,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4425 to 2540. [2018-11-23 09:53:32,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2540 states. [2018-11-23 09:53:32,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2540 states to 2540 states and 6596 transitions. [2018-11-23 09:53:32,853 INFO L78 Accepts]: Start accepts. Automaton has 2540 states and 6596 transitions. Word has length 96 [2018-11-23 09:53:32,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:32,853 INFO L480 AbstractCegarLoop]: Abstraction has 2540 states and 6596 transitions. [2018-11-23 09:53:32,853 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:32,853 INFO L276 IsEmpty]: Start isEmpty. Operand 2540 states and 6596 transitions. [2018-11-23 09:53:32,855 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:32,855 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:32,855 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:32,856 INFO L423 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:32,856 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:32,856 INFO L82 PathProgramCache]: Analyzing trace with hash -1736009256, now seen corresponding path program 16 times [2018-11-23 09:53:32,856 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:32,856 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:32,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:32,859 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:53:32,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:32,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:33,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:33,675 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:33,676 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:33,676 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:33,676 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:33,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:33,676 INFO L87 Difference]: Start difference. First operand 2540 states and 6596 transitions. Second operand 21 states. [2018-11-23 09:53:34,443 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 09:53:34,597 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 42 [2018-11-23 09:53:34,762 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 46 [2018-11-23 09:53:34,970 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 46 [2018-11-23 09:53:35,155 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 09:53:35,341 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 51 [2018-11-23 09:53:35,550 WARN L180 SmtUtils]: Spent 174.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 61 [2018-11-23 09:53:36,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:36,626 INFO L93 Difference]: Finished difference Result 3269 states and 8034 transitions. [2018-11-23 09:53:36,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-23 09:53:36,626 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:36,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:36,628 INFO L225 Difference]: With dead ends: 3269 [2018-11-23 09:53:36,629 INFO L226 Difference]: Without dead ends: 3269 [2018-11-23 09:53:36,629 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 286 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=464, Invalid=1342, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 09:53:36,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3269 states. [2018-11-23 09:53:36,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3269 to 2480. [2018-11-23 09:53:36,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2480 states. [2018-11-23 09:53:36,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2480 states to 2480 states and 6455 transitions. [2018-11-23 09:53:36,651 INFO L78 Accepts]: Start accepts. Automaton has 2480 states and 6455 transitions. Word has length 96 [2018-11-23 09:53:36,651 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:36,651 INFO L480 AbstractCegarLoop]: Abstraction has 2480 states and 6455 transitions. [2018-11-23 09:53:36,651 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:36,651 INFO L276 IsEmpty]: Start isEmpty. Operand 2480 states and 6455 transitions. [2018-11-23 09:53:36,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:36,653 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:36,653 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:36,654 INFO L423 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:36,654 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:36,654 INFO L82 PathProgramCache]: Analyzing trace with hash -926158854, now seen corresponding path program 17 times [2018-11-23 09:53:36,654 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:36,654 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:36,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:36,657 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:53:36,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:36,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:37,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:37,554 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:37,554 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:37,554 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:37,554 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:37,554 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:37,554 INFO L87 Difference]: Start difference. First operand 2480 states and 6455 transitions. Second operand 21 states. [2018-11-23 09:53:38,387 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 09:53:38,584 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 09:53:38,764 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 47 [2018-11-23 09:53:38,960 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 51 [2018-11-23 09:53:39,146 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 51 [2018-11-23 09:53:39,358 WARN L180 SmtUtils]: Spent 175.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 61 [2018-11-23 09:53:40,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:40,539 INFO L93 Difference]: Finished difference Result 3810 states and 9142 transitions. [2018-11-23 09:53:40,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 09:53:40,539 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:40,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:40,541 INFO L225 Difference]: With dead ends: 3810 [2018-11-23 09:53:40,541 INFO L226 Difference]: Without dead ends: 3810 [2018-11-23 09:53:40,542 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 245 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=433, Invalid=1289, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:53:40,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3810 states. [2018-11-23 09:53:40,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3810 to 2482. [2018-11-23 09:53:40,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2482 states. [2018-11-23 09:53:40,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2482 states to 2482 states and 6460 transitions. [2018-11-23 09:53:40,564 INFO L78 Accepts]: Start accepts. Automaton has 2482 states and 6460 transitions. Word has length 96 [2018-11-23 09:53:40,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:40,564 INFO L480 AbstractCegarLoop]: Abstraction has 2482 states and 6460 transitions. [2018-11-23 09:53:40,564 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:40,564 INFO L276 IsEmpty]: Start isEmpty. Operand 2482 states and 6460 transitions. [2018-11-23 09:53:40,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:40,566 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:40,566 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:40,566 INFO L423 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:40,566 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:40,566 INFO L82 PathProgramCache]: Analyzing trace with hash -1003115684, now seen corresponding path program 18 times [2018-11-23 09:53:40,566 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:40,566 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:40,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:40,569 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:53:40,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:40,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:41,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:41,373 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:41,373 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:41,374 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:41,374 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:41,374 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:41,374 INFO L87 Difference]: Start difference. First operand 2482 states and 6460 transitions. Second operand 21 states. [2018-11-23 09:53:42,219 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 09:53:42,419 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 42 [2018-11-23 09:53:42,614 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 48 [2018-11-23 09:53:42,825 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 52 [2018-11-23 09:53:43,013 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 52 [2018-11-23 09:53:43,225 WARN L180 SmtUtils]: Spent 180.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 61 [2018-11-23 09:53:44,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:44,396 INFO L93 Difference]: Finished difference Result 3515 states and 8548 transitions. [2018-11-23 09:53:44,396 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 09:53:44,396 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:44,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:44,398 INFO L225 Difference]: With dead ends: 3515 [2018-11-23 09:53:44,398 INFO L226 Difference]: Without dead ends: 3515 [2018-11-23 09:53:44,399 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 240 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=434, Invalid=1288, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:53:44,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3515 states. [2018-11-23 09:53:44,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3515 to 2474. [2018-11-23 09:53:44,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2474 states. [2018-11-23 09:53:44,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2474 states to 2474 states and 6440 transitions. [2018-11-23 09:53:44,422 INFO L78 Accepts]: Start accepts. Automaton has 2474 states and 6440 transitions. Word has length 96 [2018-11-23 09:53:44,422 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:44,422 INFO L480 AbstractCegarLoop]: Abstraction has 2474 states and 6440 transitions. [2018-11-23 09:53:44,422 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:44,422 INFO L276 IsEmpty]: Start isEmpty. Operand 2474 states and 6440 transitions. [2018-11-23 09:53:44,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:44,424 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:44,424 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:44,424 INFO L423 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:44,424 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:44,424 INFO L82 PathProgramCache]: Analyzing trace with hash -1189275176, now seen corresponding path program 19 times [2018-11-23 09:53:44,425 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:44,425 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:44,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:44,427 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:53:44,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:44,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:45,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:45,286 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:45,286 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:45,287 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:45,287 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:45,287 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:45,287 INFO L87 Difference]: Start difference. First operand 2474 states and 6440 transitions. Second operand 21 states. [2018-11-23 09:53:46,127 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 36 [2018-11-23 09:53:46,303 WARN L180 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 41 [2018-11-23 09:53:46,476 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 46 [2018-11-23 09:53:46,665 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 51 [2018-11-23 09:53:46,852 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 51 [2018-11-23 09:53:47,066 WARN L180 SmtUtils]: Spent 176.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 61 [2018-11-23 09:53:48,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:48,197 INFO L93 Difference]: Finished difference Result 3489 states and 8492 transitions. [2018-11-23 09:53:48,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 09:53:48,197 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:48,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:48,199 INFO L225 Difference]: With dead ends: 3489 [2018-11-23 09:53:48,200 INFO L226 Difference]: Without dead ends: 3489 [2018-11-23 09:53:48,200 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 245 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=433, Invalid=1289, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:53:48,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3489 states. [2018-11-23 09:53:48,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3489 to 2482. [2018-11-23 09:53:48,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2482 states. [2018-11-23 09:53:48,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2482 states to 2482 states and 6460 transitions. [2018-11-23 09:53:48,222 INFO L78 Accepts]: Start accepts. Automaton has 2482 states and 6460 transitions. Word has length 96 [2018-11-23 09:53:48,223 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:48,223 INFO L480 AbstractCegarLoop]: Abstraction has 2482 states and 6460 transitions. [2018-11-23 09:53:48,223 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:48,223 INFO L276 IsEmpty]: Start isEmpty. Operand 2482 states and 6460 transitions. [2018-11-23 09:53:48,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:48,224 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:48,225 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:48,225 INFO L423 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:48,225 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:48,225 INFO L82 PathProgramCache]: Analyzing trace with hash -1266232006, now seen corresponding path program 20 times [2018-11-23 09:53:48,225 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:48,225 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:48,228 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:48,228 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:53:48,228 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:48,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:49,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:49,097 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:49,097 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:49,097 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:49,097 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:49,098 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:49,098 INFO L87 Difference]: Start difference. First operand 2482 states and 6460 transitions. Second operand 21 states. [2018-11-23 09:53:49,957 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 37 [2018-11-23 09:53:50,133 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 41 [2018-11-23 09:53:50,329 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 48 [2018-11-23 09:53:50,533 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 52 [2018-11-23 09:53:50,720 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 52 [2018-11-23 09:53:50,936 WARN L180 SmtUtils]: Spent 181.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 61 [2018-11-23 09:53:52,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:52,113 INFO L93 Difference]: Finished difference Result 3707 states and 8945 transitions. [2018-11-23 09:53:52,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 09:53:52,114 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:52,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:52,116 INFO L225 Difference]: With dead ends: 3707 [2018-11-23 09:53:52,116 INFO L226 Difference]: Without dead ends: 3707 [2018-11-23 09:53:52,116 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 240 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=434, Invalid=1288, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:53:52,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3707 states. [2018-11-23 09:53:52,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3707 to 2480. [2018-11-23 09:53:52,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2480 states. [2018-11-23 09:53:52,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2480 states to 2480 states and 6455 transitions. [2018-11-23 09:53:52,139 INFO L78 Accepts]: Start accepts. Automaton has 2480 states and 6455 transitions. Word has length 96 [2018-11-23 09:53:52,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:52,139 INFO L480 AbstractCegarLoop]: Abstraction has 2480 states and 6455 transitions. [2018-11-23 09:53:52,139 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:52,140 INFO L276 IsEmpty]: Start isEmpty. Operand 2480 states and 6455 transitions. [2018-11-23 09:53:52,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:52,141 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:52,141 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:52,142 INFO L423 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:52,142 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:52,142 INFO L82 PathProgramCache]: Analyzing trace with hash -683357736, now seen corresponding path program 21 times [2018-11-23 09:53:52,142 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:52,142 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:52,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:52,145 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:53:52,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:52,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:52,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:52,971 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:52,971 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:52,972 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:52,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:52,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:52,972 INFO L87 Difference]: Start difference. First operand 2480 states and 6455 transitions. Second operand 21 states. [2018-11-23 09:53:53,774 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 37 [2018-11-23 09:53:53,930 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 42 [2018-11-23 09:53:54,100 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 46 [2018-11-23 09:53:54,309 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 09:53:54,522 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 53 [2018-11-23 09:53:54,715 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 09:53:54,935 WARN L180 SmtUtils]: Spent 185.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 62 [2018-11-23 09:53:55,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:53:55,995 INFO L93 Difference]: Finished difference Result 3192 states and 7893 transitions. [2018-11-23 09:53:55,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-23 09:53:55,996 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:53:55,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:53:55,998 INFO L225 Difference]: With dead ends: 3192 [2018-11-23 09:53:55,998 INFO L226 Difference]: Without dead ends: 3192 [2018-11-23 09:53:55,998 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 281 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=466, Invalid=1340, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 09:53:56,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3192 states. [2018-11-23 09:53:56,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3192 to 2498. [2018-11-23 09:53:56,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2498 states. [2018-11-23 09:53:56,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2498 states to 2498 states and 6500 transitions. [2018-11-23 09:53:56,017 INFO L78 Accepts]: Start accepts. Automaton has 2498 states and 6500 transitions. Word has length 96 [2018-11-23 09:53:56,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:53:56,018 INFO L480 AbstractCegarLoop]: Abstraction has 2498 states and 6500 transitions. [2018-11-23 09:53:56,018 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:53:56,018 INFO L276 IsEmpty]: Start isEmpty. Operand 2498 states and 6500 transitions. [2018-11-23 09:53:56,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:53:56,019 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:53:56,020 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:53:56,020 INFO L423 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:53:56,020 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:53:56,020 INFO L82 PathProgramCache]: Analyzing trace with hash 871020286, now seen corresponding path program 22 times [2018-11-23 09:53:56,020 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:53:56,020 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:53:56,023 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:56,023 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:53:56,023 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:53:56,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:53:56,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:53:56,934 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:53:56,934 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:53:56,934 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:53:56,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:53:56,935 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:53:56,935 INFO L87 Difference]: Start difference. First operand 2498 states and 6500 transitions. Second operand 21 states. [2018-11-23 09:53:57,607 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:53:57,771 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 39 [2018-11-23 09:53:57,938 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 09:53:58,131 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 48 [2018-11-23 09:53:58,441 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 47 [2018-11-23 09:53:58,624 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 52 [2018-11-23 09:53:58,820 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 52 [2018-11-23 09:53:59,035 WARN L180 SmtUtils]: Spent 180.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 62 [2018-11-23 09:53:59,401 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 09:53:59,582 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 09:53:59,736 WARN L180 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 47 [2018-11-23 09:53:59,978 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 46 [2018-11-23 09:54:00,159 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 47 [2018-11-23 09:54:00,421 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 50 [2018-11-23 09:54:00,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:00,431 INFO L93 Difference]: Finished difference Result 4235 states and 10394 transitions. [2018-11-23 09:54:00,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 09:54:00,431 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:54:00,431 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:00,433 INFO L225 Difference]: With dead ends: 4235 [2018-11-23 09:54:00,434 INFO L226 Difference]: Without dead ends: 4235 [2018-11-23 09:54:00,434 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 213 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=466, Invalid=1256, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:54:00,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4235 states. [2018-11-23 09:54:00,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4235 to 2498. [2018-11-23 09:54:00,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2498 states. [2018-11-23 09:54:00,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2498 states to 2498 states and 6500 transitions. [2018-11-23 09:54:00,457 INFO L78 Accepts]: Start accepts. Automaton has 2498 states and 6500 transitions. Word has length 96 [2018-11-23 09:54:00,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:00,457 INFO L480 AbstractCegarLoop]: Abstraction has 2498 states and 6500 transitions. [2018-11-23 09:54:00,457 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:54:00,457 INFO L276 IsEmpty]: Start isEmpty. Operand 2498 states and 6500 transitions. [2018-11-23 09:54:00,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:54:00,459 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:00,459 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:00,459 INFO L423 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:00,459 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:00,459 INFO L82 PathProgramCache]: Analyzing trace with hash -378996358, now seen corresponding path program 23 times [2018-11-23 09:54:00,459 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:00,459 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:00,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:00,462 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:54:00,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:00,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:54:01,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:54:01,294 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:54:01,294 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:54:01,294 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:54:01,295 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:54:01,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:54:01,295 INFO L87 Difference]: Start difference. First operand 2498 states and 6500 transitions. Second operand 21 states. [2018-11-23 09:54:01,963 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:54:02,131 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 39 [2018-11-23 09:54:02,306 WARN L180 SmtUtils]: Spent 145.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 09:54:02,494 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 48 [2018-11-23 09:54:02,672 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 49 [2018-11-23 09:54:02,884 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 53 [2018-11-23 09:54:03,244 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 51 [2018-11-23 09:54:03,428 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 52 [2018-11-23 09:54:03,646 WARN L180 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 62 [2018-11-23 09:54:04,042 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 55 [2018-11-23 09:54:04,216 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 09:54:04,410 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 53 [2018-11-23 09:54:04,584 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 09:54:04,751 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 51 [2018-11-23 09:54:04,901 WARN L180 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 47 [2018-11-23 09:54:05,098 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 51 [2018-11-23 09:54:05,263 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 47 [2018-11-23 09:54:05,402 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 09:54:05,651 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 54 [2018-11-23 09:54:05,772 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 50 [2018-11-23 09:54:05,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:05,780 INFO L93 Difference]: Finished difference Result 5297 states and 13147 transitions. [2018-11-23 09:54:05,781 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-23 09:54:05,781 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:54:05,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:05,784 INFO L225 Difference]: With dead ends: 5297 [2018-11-23 09:54:05,784 INFO L226 Difference]: Without dead ends: 5297 [2018-11-23 09:54:05,785 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 292 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=604, Invalid=1558, Unknown=0, NotChecked=0, Total=2162 [2018-11-23 09:54:05,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5297 states. [2018-11-23 09:54:05,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5297 to 2465. [2018-11-23 09:54:05,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2465 states. [2018-11-23 09:54:05,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2465 states to 2465 states and 6401 transitions. [2018-11-23 09:54:05,812 INFO L78 Accepts]: Start accepts. Automaton has 2465 states and 6401 transitions. Word has length 96 [2018-11-23 09:54:05,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:05,812 INFO L480 AbstractCegarLoop]: Abstraction has 2465 states and 6401 transitions. [2018-11-23 09:54:05,812 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:54:05,813 INFO L276 IsEmpty]: Start isEmpty. Operand 2465 states and 6401 transitions. [2018-11-23 09:54:05,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:54:05,815 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:05,815 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:05,815 INFO L423 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:05,815 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:05,815 INFO L82 PathProgramCache]: Analyzing trace with hash -1181458358, now seen corresponding path program 24 times [2018-11-23 09:54:05,815 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:05,816 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:05,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:05,819 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:54:05,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:05,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:54:06,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:54:06,677 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:54:06,677 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:54:06,677 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:54:06,678 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:54:06,678 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:54:06,678 INFO L87 Difference]: Start difference. First operand 2465 states and 6401 transitions. Second operand 21 states. [2018-11-23 09:54:07,364 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:54:07,532 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 09:54:07,829 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 42 [2018-11-23 09:54:08,002 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 47 [2018-11-23 09:54:08,195 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 51 [2018-11-23 09:54:08,387 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 52 [2018-11-23 09:54:08,606 WARN L180 SmtUtils]: Spent 180.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 62 [2018-11-23 09:54:09,009 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 43 [2018-11-23 09:54:09,190 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 45 [2018-11-23 09:54:09,352 WARN L180 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 09:54:09,581 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 42 [2018-11-23 09:54:09,874 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 09:54:10,154 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 45 [2018-11-23 09:54:10,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:10,173 INFO L93 Difference]: Finished difference Result 4435 states and 10826 transitions. [2018-11-23 09:54:10,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 09:54:10,173 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:54:10,174 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:10,177 INFO L225 Difference]: With dead ends: 4435 [2018-11-23 09:54:10,177 INFO L226 Difference]: Without dead ends: 4435 [2018-11-23 09:54:10,177 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 224 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=455, Invalid=1267, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:54:10,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4435 states. [2018-11-23 09:54:10,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4435 to 2467. [2018-11-23 09:54:10,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2467 states. [2018-11-23 09:54:10,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2467 states to 2467 states and 6406 transitions. [2018-11-23 09:54:10,206 INFO L78 Accepts]: Start accepts. Automaton has 2467 states and 6406 transitions. Word has length 96 [2018-11-23 09:54:10,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:10,206 INFO L480 AbstractCegarLoop]: Abstraction has 2467 states and 6406 transitions. [2018-11-23 09:54:10,206 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:54:10,206 INFO L276 IsEmpty]: Start isEmpty. Operand 2467 states and 6406 transitions. [2018-11-23 09:54:10,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:54:10,208 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:10,209 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:10,209 INFO L423 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:10,209 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:10,209 INFO L82 PathProgramCache]: Analyzing trace with hash -1258415188, now seen corresponding path program 25 times [2018-11-23 09:54:10,209 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:10,209 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:10,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:10,212 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:54:10,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:10,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:54:11,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:54:11,058 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:54:11,058 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:54:11,058 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:54:11,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:54:11,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:54:11,058 INFO L87 Difference]: Start difference. First operand 2467 states and 6406 transitions. Second operand 21 states. [2018-11-23 09:54:11,717 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:54:11,875 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 38 [2018-11-23 09:54:12,146 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 41 [2018-11-23 09:54:12,332 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 48 [2018-11-23 09:54:12,524 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 52 [2018-11-23 09:54:12,709 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 52 [2018-11-23 09:54:12,922 WARN L180 SmtUtils]: Spent 181.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 61 [2018-11-23 09:54:13,290 WARN L180 SmtUtils]: Spent 127.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 09:54:13,460 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 09:54:13,618 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 43 [2018-11-23 09:54:13,752 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 41 [2018-11-23 09:54:14,111 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 41 [2018-11-23 09:54:14,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:14,359 INFO L93 Difference]: Finished difference Result 4332 states and 10629 transitions. [2018-11-23 09:54:14,359 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 09:54:14,359 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:54:14,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:14,362 INFO L225 Difference]: With dead ends: 4332 [2018-11-23 09:54:14,362 INFO L226 Difference]: Without dead ends: 4332 [2018-11-23 09:54:14,363 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 225 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=456, Invalid=1266, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:54:14,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4332 states. [2018-11-23 09:54:14,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4332 to 2465. [2018-11-23 09:54:14,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2465 states. [2018-11-23 09:54:14,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2465 states to 2465 states and 6401 transitions. [2018-11-23 09:54:14,394 INFO L78 Accepts]: Start accepts. Automaton has 2465 states and 6401 transitions. Word has length 96 [2018-11-23 09:54:14,394 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:14,394 INFO L480 AbstractCegarLoop]: Abstraction has 2465 states and 6401 transitions. [2018-11-23 09:54:14,394 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:54:14,394 INFO L276 IsEmpty]: Start isEmpty. Operand 2465 states and 6401 transitions. [2018-11-23 09:54:14,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:54:14,396 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:14,396 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:14,396 INFO L423 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:14,396 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:14,396 INFO L82 PathProgramCache]: Analyzing trace with hash 827845740, now seen corresponding path program 26 times [2018-11-23 09:54:14,396 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:14,396 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:14,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:14,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:54:14,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:14,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:54:15,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:54:15,237 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:54:15,237 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:54:15,237 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:54:15,237 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:54:15,237 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:54:15,237 INFO L87 Difference]: Start difference. First operand 2465 states and 6401 transitions. Second operand 21 states. [2018-11-23 09:54:15,927 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:54:16,094 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 38 [2018-11-23 09:54:16,279 WARN L180 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 45 [2018-11-23 09:54:16,479 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 09:54:16,658 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 09:54:16,876 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 09:54:17,292 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 52 [2018-11-23 09:54:17,473 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 52 [2018-11-23 09:54:17,681 WARN L180 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 61 [2018-11-23 09:54:18,131 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 51 [2018-11-23 09:54:18,337 WARN L180 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 55 [2018-11-23 09:54:18,522 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 49 [2018-11-23 09:54:18,718 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 53 [2018-11-23 09:54:18,876 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 47 [2018-11-23 09:54:19,046 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 51 [2018-11-23 09:54:19,238 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 47 [2018-11-23 09:54:19,424 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 51 [2018-11-23 09:54:19,680 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 50 [2018-11-23 09:54:19,814 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 09:54:19,957 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 54 [2018-11-23 09:54:19,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:19,972 INFO L93 Difference]: Finished difference Result 6306 states and 15694 transitions. [2018-11-23 09:54:19,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-23 09:54:19,972 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:54:19,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:19,975 INFO L225 Difference]: With dead ends: 6306 [2018-11-23 09:54:19,975 INFO L226 Difference]: Without dead ends: 6306 [2018-11-23 09:54:19,975 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 287 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=605, Invalid=1557, Unknown=0, NotChecked=0, Total=2162 [2018-11-23 09:54:19,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6306 states. [2018-11-23 09:54:19,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6306 to 2476. [2018-11-23 09:54:19,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2476 states. [2018-11-23 09:54:20,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2476 states to 2476 states and 6434 transitions. [2018-11-23 09:54:20,001 INFO L78 Accepts]: Start accepts. Automaton has 2476 states and 6434 transitions. Word has length 96 [2018-11-23 09:54:20,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:20,001 INFO L480 AbstractCegarLoop]: Abstraction has 2476 states and 6434 transitions. [2018-11-23 09:54:20,001 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:54:20,001 INFO L276 IsEmpty]: Start isEmpty. Operand 2476 states and 6434 transitions. [2018-11-23 09:54:20,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:54:20,003 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:20,003 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:20,003 INFO L423 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:20,004 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:20,004 INFO L82 PathProgramCache]: Analyzing trace with hash 1315826080, now seen corresponding path program 27 times [2018-11-23 09:54:20,004 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:20,004 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:20,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:20,007 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:54:20,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:20,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:54:20,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:54:20,976 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:54:20,976 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:54:20,976 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:54:20,977 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:54:20,977 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:54:20,977 INFO L87 Difference]: Start difference. First operand 2476 states and 6434 transitions. Second operand 21 states. [2018-11-23 09:54:21,663 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:54:21,829 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 38 [2018-11-23 09:54:22,023 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 45 [2018-11-23 09:54:22,226 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 09:54:22,592 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 48 [2018-11-23 09:54:22,790 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 52 [2018-11-23 09:54:22,979 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 52 [2018-11-23 09:54:23,198 WARN L180 SmtUtils]: Spent 181.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 61 [2018-11-23 09:54:23,628 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 51 [2018-11-23 09:54:23,815 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 49 [2018-11-23 09:54:23,975 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 47 [2018-11-23 09:54:24,216 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 45 [2018-11-23 09:54:24,396 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 47 [2018-11-23 09:54:24,667 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 09:54:24,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:24,679 INFO L93 Difference]: Finished difference Result 5188 states and 12863 transitions. [2018-11-23 09:54:24,679 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 09:54:24,679 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:54:24,679 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:24,682 INFO L225 Difference]: With dead ends: 5188 [2018-11-23 09:54:24,682 INFO L226 Difference]: Without dead ends: 5188 [2018-11-23 09:54:24,682 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 218 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=467, Invalid=1255, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:54:24,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5188 states. [2018-11-23 09:54:24,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5188 to 2454. [2018-11-23 09:54:24,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2454 states. [2018-11-23 09:54:24,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2454 states to 2454 states and 6368 transitions. [2018-11-23 09:54:24,708 INFO L78 Accepts]: Start accepts. Automaton has 2454 states and 6368 transitions. Word has length 96 [2018-11-23 09:54:24,708 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:24,708 INFO L480 AbstractCegarLoop]: Abstraction has 2454 states and 6368 transitions. [2018-11-23 09:54:24,708 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:54:24,708 INFO L276 IsEmpty]: Start isEmpty. Operand 2454 states and 6368 transitions. [2018-11-23 09:54:24,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:54:24,711 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:24,711 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:24,711 INFO L423 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:24,711 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:24,711 INFO L82 PathProgramCache]: Analyzing trace with hash -506291782, now seen corresponding path program 28 times [2018-11-23 09:54:24,711 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:24,711 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:24,715 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:24,715 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:54:24,715 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:24,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:54:25,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:54:25,551 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:54:25,551 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:54:25,551 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:54:25,551 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:54:25,551 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:54:25,551 INFO L87 Difference]: Start difference. First operand 2454 states and 6368 transitions. Second operand 21 states. [2018-11-23 09:54:26,187 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:54:26,392 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 09:54:26,555 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 42 [2018-11-23 09:54:26,724 WARN L180 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 47 [2018-11-23 09:54:26,913 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 51 [2018-11-23 09:54:27,100 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 52 [2018-11-23 09:54:27,313 WARN L180 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 62 [2018-11-23 09:54:27,629 WARN L180 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 09:54:27,783 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 09:54:27,927 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 09:54:28,378 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 09:54:28,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:28,628 INFO L93 Difference]: Finished difference Result 3450 states and 8352 transitions. [2018-11-23 09:54:28,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 09:54:28,628 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:54:28,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:28,631 INFO L225 Difference]: With dead ends: 3450 [2018-11-23 09:54:28,631 INFO L226 Difference]: Without dead ends: 3450 [2018-11-23 09:54:28,631 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 230 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=444, Invalid=1278, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:54:28,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3450 states. [2018-11-23 09:54:28,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3450 to 2448. [2018-11-23 09:54:28,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2448 states. [2018-11-23 09:54:28,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2448 states to 2448 states and 6353 transitions. [2018-11-23 09:54:28,653 INFO L78 Accepts]: Start accepts. Automaton has 2448 states and 6353 transitions. Word has length 96 [2018-11-23 09:54:28,654 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:28,654 INFO L480 AbstractCegarLoop]: Abstraction has 2448 states and 6353 transitions. [2018-11-23 09:54:28,654 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:54:28,654 INFO L276 IsEmpty]: Start isEmpty. Operand 2448 states and 6353 transitions. [2018-11-23 09:54:28,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:54:28,656 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:28,656 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:28,656 INFO L423 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:28,657 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:28,657 INFO L82 PathProgramCache]: Analyzing trace with hash -583248612, now seen corresponding path program 29 times [2018-11-23 09:54:28,657 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:28,657 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:28,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:28,661 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:54:28,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:28,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:54:29,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:54:29,480 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:54:29,480 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:54:29,480 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:54:29,480 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:54:29,480 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:54:29,480 INFO L87 Difference]: Start difference. First operand 2448 states and 6353 transitions. Second operand 21 states. [2018-11-23 09:54:30,160 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:54:30,397 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 37 [2018-11-23 09:54:30,580 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 41 [2018-11-23 09:54:30,781 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 48 [2018-11-23 09:54:30,991 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 52 [2018-11-23 09:54:31,179 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 52 [2018-11-23 09:54:31,397 WARN L180 SmtUtils]: Spent 180.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 61 [2018-11-23 09:54:31,783 WARN L180 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 09:54:31,950 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 09:54:32,093 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 09:54:32,289 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 37 [2018-11-23 09:54:32,553 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 09:54:32,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:32,817 INFO L93 Difference]: Finished difference Result 3668 states and 8805 transitions. [2018-11-23 09:54:32,817 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 09:54:32,817 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:54:32,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:32,819 INFO L225 Difference]: With dead ends: 3668 [2018-11-23 09:54:32,819 INFO L226 Difference]: Without dead ends: 3668 [2018-11-23 09:54:32,819 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 225 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=445, Invalid=1277, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 09:54:32,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3668 states. [2018-11-23 09:54:32,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3668 to 2446. [2018-11-23 09:54:32,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2446 states. [2018-11-23 09:54:32,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2446 states to 2446 states and 6348 transitions. [2018-11-23 09:54:32,840 INFO L78 Accepts]: Start accepts. Automaton has 2446 states and 6348 transitions. Word has length 96 [2018-11-23 09:54:32,840 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:32,840 INFO L480 AbstractCegarLoop]: Abstraction has 2446 states and 6348 transitions. [2018-11-23 09:54:32,840 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:54:32,840 INFO L276 IsEmpty]: Start isEmpty. Operand 2446 states and 6348 transitions. [2018-11-23 09:54:32,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:54:32,841 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:32,842 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:32,842 INFO L423 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:32,842 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:32,842 INFO L82 PathProgramCache]: Analyzing trace with hash -374342, now seen corresponding path program 30 times [2018-11-23 09:54:32,842 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:32,842 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:32,845 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:32,845 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:54:32,845 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:32,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:54:33,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:54:33,673 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:54:33,673 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:54:33,673 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:54:33,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:54:33,673 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:54:33,673 INFO L87 Difference]: Start difference. First operand 2446 states and 6348 transitions. Second operand 21 states. [2018-11-23 09:54:34,365 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:54:34,608 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 37 [2018-11-23 09:54:34,767 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 42 [2018-11-23 09:54:34,937 WARN L180 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 46 [2018-11-23 09:54:35,150 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 09:54:35,369 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 53 [2018-11-23 09:54:35,563 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 09:54:35,786 WARN L180 SmtUtils]: Spent 185.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 62 [2018-11-23 09:54:36,152 WARN L180 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 09:54:36,312 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 09:54:36,457 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 09:54:36,909 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 09:54:37,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:37,144 INFO L93 Difference]: Finished difference Result 3402 states and 8279 transitions. [2018-11-23 09:54:37,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-23 09:54:37,144 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:54:37,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:37,146 INFO L225 Difference]: With dead ends: 3402 [2018-11-23 09:54:37,146 INFO L226 Difference]: Without dead ends: 3402 [2018-11-23 09:54:37,146 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 243 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=476, Invalid=1330, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 09:54:37,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3402 states. [2018-11-23 09:54:37,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3402 to 2440. [2018-11-23 09:54:37,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2440 states. [2018-11-23 09:54:37,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2440 states to 2440 states and 6333 transitions. [2018-11-23 09:54:37,165 INFO L78 Accepts]: Start accepts. Automaton has 2440 states and 6333 transitions. Word has length 96 [2018-11-23 09:54:37,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:37,165 INFO L480 AbstractCegarLoop]: Abstraction has 2440 states and 6333 transitions. [2018-11-23 09:54:37,165 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:54:37,165 INFO L276 IsEmpty]: Start isEmpty. Operand 2440 states and 6333 transitions. [2018-11-23 09:54:37,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:54:37,166 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:37,166 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:37,167 INFO L423 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:37,167 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:37,167 INFO L82 PathProgramCache]: Analyzing trace with hash 1768965558, now seen corresponding path program 31 times [2018-11-23 09:54:37,167 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:37,167 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:37,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:37,170 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:54:37,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:37,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:54:37,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:54:37,976 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:54:37,976 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:54:37,976 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:54:37,977 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:54:37,977 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:54:37,977 INFO L87 Difference]: Start difference. First operand 2440 states and 6333 transitions. Second operand 21 states. [2018-11-23 09:54:38,659 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:54:38,813 WARN L180 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 39 [2018-11-23 09:54:38,975 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 09:54:39,163 WARN L180 SmtUtils]: Spent 145.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 44 [2018-11-23 09:54:39,375 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 50 [2018-11-23 09:54:39,555 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 09:54:39,778 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 54 [2018-11-23 09:54:40,128 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 46 [2018-11-23 09:54:40,374 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 53 [2018-11-23 09:54:40,562 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 53 [2018-11-23 09:54:40,788 WARN L180 SmtUtils]: Spent 185.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 62 [2018-11-23 09:54:41,222 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 46 [2018-11-23 09:54:41,423 WARN L180 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 56 [2018-11-23 09:54:41,587 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 45 [2018-11-23 09:54:41,787 WARN L180 SmtUtils]: Spent 175.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 54 [2018-11-23 09:54:41,925 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 43 [2018-11-23 09:54:42,096 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 52 [2018-11-23 09:54:42,270 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 43 [2018-11-23 09:54:42,459 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 52 [2018-11-23 09:54:42,718 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 51 [2018-11-23 09:54:42,983 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 55 [2018-11-23 09:54:42,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:42,998 INFO L93 Difference]: Finished difference Result 4083 states and 10082 transitions. [2018-11-23 09:54:42,998 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-11-23 09:54:42,998 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:54:42,998 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:43,000 INFO L225 Difference]: With dead ends: 4083 [2018-11-23 09:54:43,000 INFO L226 Difference]: Without dead ends: 4083 [2018-11-23 09:54:43,000 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 339 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=653, Invalid=1699, Unknown=0, NotChecked=0, Total=2352 [2018-11-23 09:54:43,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4083 states. [2018-11-23 09:54:43,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4083 to 1967. [2018-11-23 09:54:43,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1967 states. [2018-11-23 09:54:43,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1967 states to 1967 states and 5046 transitions. [2018-11-23 09:54:43,018 INFO L78 Accepts]: Start accepts. Automaton has 1967 states and 5046 transitions. Word has length 96 [2018-11-23 09:54:43,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:43,018 INFO L480 AbstractCegarLoop]: Abstraction has 1967 states and 5046 transitions. [2018-11-23 09:54:43,019 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:54:43,019 INFO L276 IsEmpty]: Start isEmpty. Operand 1967 states and 5046 transitions. [2018-11-23 09:54:43,020 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:54:43,020 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:43,020 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:43,020 INFO L423 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:43,020 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:43,020 INFO L82 PathProgramCache]: Analyzing trace with hash -2038021398, now seen corresponding path program 32 times [2018-11-23 09:54:43,020 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:43,020 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:43,023 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:43,023 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:54:43,023 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:43,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:54:43,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:54:43,845 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:54:43,845 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:54:43,846 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:54:43,846 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:54:43,846 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:54:43,846 INFO L87 Difference]: Start difference. First operand 1967 states and 5046 transitions. Second operand 21 states. [2018-11-23 09:54:44,491 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:54:44,641 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 39 [2018-11-23 09:54:44,801 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 09:54:44,987 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 44 [2018-11-23 09:54:45,191 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 09:54:45,530 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 46 [2018-11-23 09:54:45,736 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 09:54:45,941 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 09:54:46,134 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 09:54:46,362 WARN L180 SmtUtils]: Spent 185.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 62 [2018-11-23 09:54:46,773 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 46 [2018-11-23 09:54:46,963 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 52 [2018-11-23 09:54:47,128 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 45 [2018-11-23 09:54:47,312 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 50 [2018-11-23 09:54:47,452 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 43 [2018-11-23 09:54:47,609 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 48 [2018-11-23 09:54:47,848 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 46 [2018-11-23 09:54:48,011 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 43 [2018-11-23 09:54:48,185 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 48 [2018-11-23 09:54:48,682 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 51 [2018-11-23 09:54:48,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:48,700 INFO L93 Difference]: Finished difference Result 4336 states and 10537 transitions. [2018-11-23 09:54:48,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-11-23 09:54:48,701 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:54:48,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:48,704 INFO L225 Difference]: With dead ends: 4336 [2018-11-23 09:54:48,704 INFO L226 Difference]: Without dead ends: 4336 [2018-11-23 09:54:48,704 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 396 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=667, Invalid=1783, Unknown=0, NotChecked=0, Total=2450 [2018-11-23 09:54:48,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4336 states. [2018-11-23 09:54:48,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4336 to 1956. [2018-11-23 09:54:48,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1956 states. [2018-11-23 09:54:48,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1956 states to 1956 states and 5013 transitions. [2018-11-23 09:54:48,725 INFO L78 Accepts]: Start accepts. Automaton has 1956 states and 5013 transitions. Word has length 96 [2018-11-23 09:54:48,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:48,725 INFO L480 AbstractCegarLoop]: Abstraction has 1956 states and 5013 transitions. [2018-11-23 09:54:48,725 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:54:48,725 INFO L276 IsEmpty]: Start isEmpty. Operand 1956 states and 5013 transitions. [2018-11-23 09:54:48,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 09:54:48,727 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:48,727 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:48,727 INFO L423 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:48,727 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:48,727 INFO L82 PathProgramCache]: Analyzing trace with hash -907863174, now seen corresponding path program 33 times [2018-11-23 09:54:48,727 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:48,727 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:48,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:48,738 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:54:48,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:48,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:54:49,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:54:49,554 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:54:49,554 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 09:54:49,554 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 09:54:49,554 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 09:54:49,554 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 09:54:49,554 INFO L87 Difference]: Start difference. First operand 1956 states and 5013 transitions. Second operand 21 states. [2018-11-23 09:54:50,247 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 09:54:50,400 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 39 [2018-11-23 09:54:50,562 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 09:54:50,919 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 42 [2018-11-23 09:54:51,105 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 46 [2018-11-23 09:54:51,314 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 09:54:51,521 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 53 [2018-11-23 09:54:51,714 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 53 [2018-11-23 09:54:51,938 WARN L180 SmtUtils]: Spent 190.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 62 [2018-11-23 09:54:52,336 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 46 [2018-11-23 09:54:52,501 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 45 [2018-11-23 09:54:52,641 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 43 [2018-11-23 09:54:53,019 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 43 [2018-11-23 09:54:53,171 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 42 [2018-11-23 09:54:53,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:53,317 INFO L93 Difference]: Finished difference Result 2857 states and 6970 transitions. [2018-11-23 09:54:53,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-23 09:54:53,318 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 09:54:53,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:53,320 INFO L225 Difference]: With dead ends: 2857 [2018-11-23 09:54:53,320 INFO L226 Difference]: Without dead ends: 2857 [2018-11-23 09:54:53,320 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 254 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=488, Invalid=1318, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 09:54:53,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2857 states. [2018-11-23 09:54:53,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2857 to 1778. [2018-11-23 09:54:53,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1778 states. [2018-11-23 09:54:53,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1778 states to 1778 states and 4648 transitions. [2018-11-23 09:54:53,337 INFO L78 Accepts]: Start accepts. Automaton has 1778 states and 4648 transitions. Word has length 96 [2018-11-23 09:54:53,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:53,337 INFO L480 AbstractCegarLoop]: Abstraction has 1778 states and 4648 transitions. [2018-11-23 09:54:53,337 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 09:54:53,337 INFO L276 IsEmpty]: Start isEmpty. Operand 1778 states and 4648 transitions. [2018-11-23 09:54:53,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 09:54:53,339 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:53,339 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:53,339 INFO L423 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:53,339 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:53,339 INFO L82 PathProgramCache]: Analyzing trace with hash 388540451, now seen corresponding path program 1 times [2018-11-23 09:54:53,339 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:53,339 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:53,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:53,344 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:54:53,344 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:53,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:54:54,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:54:54,859 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:54:54,859 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [] total 27 [2018-11-23 09:54:54,860 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-11-23 09:54:54,860 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-11-23 09:54:54,860 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=638, Unknown=0, NotChecked=0, Total=702 [2018-11-23 09:54:54,860 INFO L87 Difference]: Start difference. First operand 1778 states and 4648 transitions. Second operand 27 states. [2018-11-23 09:54:55,863 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 46 [2018-11-23 09:54:56,012 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 51 [2018-11-23 09:54:56,247 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 54 [2018-11-23 09:54:57,890 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 61 [2018-11-23 09:54:59,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:54:59,599 INFO L93 Difference]: Finished difference Result 2578 states and 6470 transitions. [2018-11-23 09:54:59,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-11-23 09:54:59,599 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 102 [2018-11-23 09:54:59,599 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:54:59,600 INFO L225 Difference]: With dead ends: 2578 [2018-11-23 09:54:59,600 INFO L226 Difference]: Without dead ends: 2399 [2018-11-23 09:54:59,601 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 953 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=727, Invalid=3563, Unknown=0, NotChecked=0, Total=4290 [2018-11-23 09:54:59,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2399 states. [2018-11-23 09:54:59,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2399 to 1778. [2018-11-23 09:54:59,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1778 states. [2018-11-23 09:54:59,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1778 states to 1778 states and 4636 transitions. [2018-11-23 09:54:59,615 INFO L78 Accepts]: Start accepts. Automaton has 1778 states and 4636 transitions. Word has length 102 [2018-11-23 09:54:59,615 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:54:59,615 INFO L480 AbstractCegarLoop]: Abstraction has 1778 states and 4636 transitions. [2018-11-23 09:54:59,615 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-11-23 09:54:59,615 INFO L276 IsEmpty]: Start isEmpty. Operand 1778 states and 4636 transitions. [2018-11-23 09:54:59,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 09:54:59,616 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:54:59,617 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:54:59,617 INFO L423 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:54:59,617 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:54:59,617 INFO L82 PathProgramCache]: Analyzing trace with hash -39798651, now seen corresponding path program 2 times [2018-11-23 09:54:59,617 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:54:59,617 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:54:59,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:59,620 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:54:59,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:54:59,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:55:01,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:55:01,801 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:55:01,801 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [] total 33 [2018-11-23 09:55:01,801 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-23 09:55:01,801 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-23 09:55:01,801 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=971, Unknown=0, NotChecked=0, Total=1056 [2018-11-23 09:55:01,802 INFO L87 Difference]: Start difference. First operand 1778 states and 4636 transitions. Second operand 33 states. [2018-11-23 09:55:02,686 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 09:55:02,915 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 47 [2018-11-23 09:55:03,149 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 49 [2018-11-23 09:55:03,357 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 54 [2018-11-23 09:55:03,595 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 57 [2018-11-23 09:55:03,833 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 59 [2018-11-23 09:55:05,652 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 96 DAG size of output: 69 [2018-11-23 09:55:05,982 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 104 DAG size of output: 71 [2018-11-23 09:55:06,143 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 94 DAG size of output: 64 [2018-11-23 09:55:06,290 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 62 [2018-11-23 09:55:07,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:55:07,318 INFO L93 Difference]: Finished difference Result 2301 states and 5911 transitions. [2018-11-23 09:55:07,319 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-11-23 09:55:07,319 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 102 [2018-11-23 09:55:07,319 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:55:07,320 INFO L225 Difference]: With dead ends: 2301 [2018-11-23 09:55:07,320 INFO L226 Difference]: Without dead ends: 2161 [2018-11-23 09:55:07,320 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 855 ImplicationChecksByTransitivity, 5.7s TimeCoverageRelationStatistics Valid=715, Invalid=3841, Unknown=0, NotChecked=0, Total=4556 [2018-11-23 09:55:07,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2161 states. [2018-11-23 09:55:07,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2161 to 1822. [2018-11-23 09:55:07,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1822 states. [2018-11-23 09:55:07,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1822 states to 1822 states and 4753 transitions. [2018-11-23 09:55:07,333 INFO L78 Accepts]: Start accepts. Automaton has 1822 states and 4753 transitions. Word has length 102 [2018-11-23 09:55:07,333 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:55:07,333 INFO L480 AbstractCegarLoop]: Abstraction has 1822 states and 4753 transitions. [2018-11-23 09:55:07,334 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-23 09:55:07,334 INFO L276 IsEmpty]: Start isEmpty. Operand 1822 states and 4753 transitions. [2018-11-23 09:55:07,335 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 09:55:07,335 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:55:07,335 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:55:07,335 INFO L423 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:55:07,335 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:55:07,335 INFO L82 PathProgramCache]: Analyzing trace with hash -604871447, now seen corresponding path program 3 times [2018-11-23 09:55:07,335 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:55:07,335 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:55:07,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:07,339 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:55:07,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:07,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:55:09,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:55:09,408 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:55:09,408 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [34] imperfect sequences [] total 34 [2018-11-23 09:55:09,408 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-11-23 09:55:09,409 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-11-23 09:55:09,409 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=88, Invalid=1034, Unknown=0, NotChecked=0, Total=1122 [2018-11-23 09:55:09,409 INFO L87 Difference]: Start difference. First operand 1822 states and 4753 transitions. Second operand 34 states. [2018-11-23 09:55:10,313 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 09:55:10,538 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 47 [2018-11-23 09:55:10,775 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 49 [2018-11-23 09:55:10,983 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 54 [2018-11-23 09:55:11,225 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 57 [2018-11-23 09:55:11,478 WARN L180 SmtUtils]: Spent 182.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 59 [2018-11-23 09:55:12,489 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 64 [2018-11-23 09:55:13,370 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 90 DAG size of output: 67 [2018-11-23 09:55:13,698 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 94 DAG size of output: 69 [2018-11-23 09:55:13,994 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 62 [2018-11-23 09:55:15,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:55:15,013 INFO L93 Difference]: Finished difference Result 2315 states and 5965 transitions. [2018-11-23 09:55:15,013 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-11-23 09:55:15,013 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 102 [2018-11-23 09:55:15,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:55:15,015 INFO L225 Difference]: With dead ends: 2315 [2018-11-23 09:55:15,015 INFO L226 Difference]: Without dead ends: 2188 [2018-11-23 09:55:15,015 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 878 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=728, Invalid=3964, Unknown=0, NotChecked=0, Total=4692 [2018-11-23 09:55:15,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2188 states. [2018-11-23 09:55:15,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2188 to 1910. [2018-11-23 09:55:15,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1910 states. [2018-11-23 09:55:15,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1910 states to 1910 states and 4987 transitions. [2018-11-23 09:55:15,033 INFO L78 Accepts]: Start accepts. Automaton has 1910 states and 4987 transitions. Word has length 102 [2018-11-23 09:55:15,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:55:15,034 INFO L480 AbstractCegarLoop]: Abstraction has 1910 states and 4987 transitions. [2018-11-23 09:55:15,034 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-11-23 09:55:15,034 INFO L276 IsEmpty]: Start isEmpty. Operand 1910 states and 4987 transitions. [2018-11-23 09:55:15,036 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 09:55:15,036 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:55:15,036 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:55:15,036 INFO L423 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:55:15,036 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:55:15,036 INFO L82 PathProgramCache]: Analyzing trace with hash 1479820581, now seen corresponding path program 4 times [2018-11-23 09:55:15,037 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:55:15,037 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:55:15,041 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:15,041 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:55:15,041 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:15,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:55:17,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:55:17,004 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:55:17,004 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [] total 33 [2018-11-23 09:55:17,004 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-23 09:55:17,004 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-23 09:55:17,004 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=973, Unknown=0, NotChecked=0, Total=1056 [2018-11-23 09:55:17,005 INFO L87 Difference]: Start difference. First operand 1910 states and 4987 transitions. Second operand 33 states. [2018-11-23 09:55:17,936 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 41 [2018-11-23 09:55:18,167 WARN L180 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 49 [2018-11-23 09:55:18,403 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 51 [2018-11-23 09:55:18,623 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 56 [2018-11-23 09:55:18,869 WARN L180 SmtUtils]: Spent 176.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 59 [2018-11-23 09:55:19,119 WARN L180 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 61 [2018-11-23 09:55:20,127 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 66 [2018-11-23 09:55:20,648 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 68 [2018-11-23 09:55:20,965 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 61 [2018-11-23 09:55:21,749 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 64 [2018-11-23 09:55:23,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:55:23,139 INFO L93 Difference]: Finished difference Result 2447 states and 6262 transitions. [2018-11-23 09:55:23,139 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-11-23 09:55:23,139 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 102 [2018-11-23 09:55:23,139 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:55:23,140 INFO L225 Difference]: With dead ends: 2447 [2018-11-23 09:55:23,140 INFO L226 Difference]: Without dead ends: 2183 [2018-11-23 09:55:23,141 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1038 ImplicationChecksByTransitivity, 6.1s TimeCoverageRelationStatistics Valid=847, Invalid=4409, Unknown=0, NotChecked=0, Total=5256 [2018-11-23 09:55:23,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2183 states. [2018-11-23 09:55:23,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2183 to 1954. [2018-11-23 09:55:23,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1954 states. [2018-11-23 09:55:23,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1954 states to 1954 states and 5064 transitions. [2018-11-23 09:55:23,155 INFO L78 Accepts]: Start accepts. Automaton has 1954 states and 5064 transitions. Word has length 102 [2018-11-23 09:55:23,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:55:23,155 INFO L480 AbstractCegarLoop]: Abstraction has 1954 states and 5064 transitions. [2018-11-23 09:55:23,155 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-23 09:55:23,155 INFO L276 IsEmpty]: Start isEmpty. Operand 1954 states and 5064 transitions. [2018-11-23 09:55:23,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 09:55:23,156 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:55:23,156 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:55:23,157 INFO L423 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:55:23,157 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:55:23,157 INFO L82 PathProgramCache]: Analyzing trace with hash -1842981911, now seen corresponding path program 5 times [2018-11-23 09:55:23,157 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:55:23,157 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:55:23,160 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:23,160 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:55:23,160 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:23,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:55:24,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:55:24,503 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:55:24,503 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [] total 27 [2018-11-23 09:55:24,503 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-11-23 09:55:24,503 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-11-23 09:55:24,503 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=640, Unknown=0, NotChecked=0, Total=702 [2018-11-23 09:55:24,503 INFO L87 Difference]: Start difference. First operand 1954 states and 5064 transitions. Second operand 27 states. [2018-11-23 09:55:25,305 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 42 [2018-11-23 09:55:25,522 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 50 [2018-11-23 09:55:25,751 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 55 [2018-11-23 09:55:25,968 WARN L180 SmtUtils]: Spent 180.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 61 [2018-11-23 09:55:26,236 WARN L180 SmtUtils]: Spent 188.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 63 [2018-11-23 09:55:27,107 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 62 [2018-11-23 09:55:27,589 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 64 [2018-11-23 09:55:28,134 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 67 [2018-11-23 09:55:28,415 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 62 [2018-11-23 09:55:29,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:55:29,992 INFO L93 Difference]: Finished difference Result 2635 states and 6663 transitions. [2018-11-23 09:55:29,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-11-23 09:55:29,992 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 102 [2018-11-23 09:55:29,993 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:55:29,994 INFO L225 Difference]: With dead ends: 2635 [2018-11-23 09:55:29,994 INFO L226 Difference]: Without dead ends: 2214 [2018-11-23 09:55:29,995 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 832 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=712, Invalid=3448, Unknown=0, NotChecked=0, Total=4160 [2018-11-23 09:55:29,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2214 states. [2018-11-23 09:55:30,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2214 to 1634. [2018-11-23 09:55:30,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1634 states. [2018-11-23 09:55:30,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1634 states to 1634 states and 4228 transitions. [2018-11-23 09:55:30,009 INFO L78 Accepts]: Start accepts. Automaton has 1634 states and 4228 transitions. Word has length 102 [2018-11-23 09:55:30,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:55:30,009 INFO L480 AbstractCegarLoop]: Abstraction has 1634 states and 4228 transitions. [2018-11-23 09:55:30,009 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-11-23 09:55:30,009 INFO L276 IsEmpty]: Start isEmpty. Operand 1634 states and 4228 transitions. [2018-11-23 09:55:30,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 09:55:30,010 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:55:30,011 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:55:30,011 INFO L423 AbstractCegarLoop]: === Iteration 44 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:55:30,011 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:55:30,011 INFO L82 PathProgramCache]: Analyzing trace with hash -103840989, now seen corresponding path program 6 times [2018-11-23 09:55:30,011 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:55:30,011 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:55:30,015 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:30,015 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:55:30,016 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:30,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:55:31,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:55:31,867 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:55:31,867 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [] total 32 [2018-11-23 09:55:31,868 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-11-23 09:55:31,868 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-11-23 09:55:31,868 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=911, Unknown=0, NotChecked=0, Total=992 [2018-11-23 09:55:31,868 INFO L87 Difference]: Start difference. First operand 1634 states and 4228 transitions. Second operand 32 states. [2018-11-23 09:55:32,791 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 09:55:33,020 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 47 [2018-11-23 09:55:33,255 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 49 [2018-11-23 09:55:33,463 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 54 [2018-11-23 09:55:33,714 WARN L180 SmtUtils]: Spent 180.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 61 [2018-11-23 09:55:33,963 WARN L180 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 63 [2018-11-23 09:55:34,985 WARN L180 SmtUtils]: Spent 188.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 62 [2018-11-23 09:55:35,842 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 102 DAG size of output: 67 [2018-11-23 09:55:36,225 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 110 DAG size of output: 69 [2018-11-23 09:55:36,561 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 62 [2018-11-23 09:55:37,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:55:37,629 INFO L93 Difference]: Finished difference Result 1939 states and 4894 transitions. [2018-11-23 09:55:37,629 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-11-23 09:55:37,629 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 102 [2018-11-23 09:55:37,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:55:37,630 INFO L225 Difference]: With dead ends: 1939 [2018-11-23 09:55:37,630 INFO L226 Difference]: Without dead ends: 1760 [2018-11-23 09:55:37,630 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 806 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=719, Invalid=3703, Unknown=0, NotChecked=0, Total=4422 [2018-11-23 09:55:37,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1760 states. [2018-11-23 09:55:37,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1760 to 1640. [2018-11-23 09:55:37,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1640 states. [2018-11-23 09:55:37,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1640 states to 1640 states and 4237 transitions. [2018-11-23 09:55:37,642 INFO L78 Accepts]: Start accepts. Automaton has 1640 states and 4237 transitions. Word has length 102 [2018-11-23 09:55:37,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:55:37,642 INFO L480 AbstractCegarLoop]: Abstraction has 1640 states and 4237 transitions. [2018-11-23 09:55:37,642 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-11-23 09:55:37,642 INFO L276 IsEmpty]: Start isEmpty. Operand 1640 states and 4237 transitions. [2018-11-23 09:55:37,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 09:55:37,643 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:55:37,643 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:55:37,643 INFO L423 AbstractCegarLoop]: === Iteration 45 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:55:37,643 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:55:37,643 INFO L82 PathProgramCache]: Analyzing trace with hash 1196016419, now seen corresponding path program 7 times [2018-11-23 09:55:37,643 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:55:37,643 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:55:37,646 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:37,646 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:55:37,646 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:37,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:55:38,315 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 41 [2018-11-23 09:55:40,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:55:40,149 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:55:40,149 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [35] imperfect sequences [] total 35 [2018-11-23 09:55:40,149 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-11-23 09:55:40,149 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-11-23 09:55:40,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=88, Invalid=1102, Unknown=0, NotChecked=0, Total=1190 [2018-11-23 09:55:40,150 INFO L87 Difference]: Start difference. First operand 1640 states and 4237 transitions. Second operand 35 states. [2018-11-23 09:55:41,098 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 49 [2018-11-23 09:55:41,292 WARN L180 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 48 [2018-11-23 09:55:41,570 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 54 [2018-11-23 09:55:41,861 WARN L180 SmtUtils]: Spent 182.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 59 [2018-11-23 09:55:42,143 WARN L180 SmtUtils]: Spent 223.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 65 [2018-11-23 09:55:42,457 WARN L180 SmtUtils]: Spent 223.00 ms on a formula simplification. DAG size of input: 105 DAG size of output: 72 [2018-11-23 09:55:42,769 WARN L180 SmtUtils]: Spent 236.00 ms on a formula simplification. DAG size of input: 107 DAG size of output: 74 [2018-11-23 09:55:44,131 WARN L180 SmtUtils]: Spent 237.00 ms on a formula simplification. DAG size of input: 114 DAG size of output: 73 [2018-11-23 09:55:44,506 WARN L180 SmtUtils]: Spent 256.00 ms on a formula simplification. DAG size of input: 121 DAG size of output: 77 [2018-11-23 09:55:44,683 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 68 [2018-11-23 09:55:45,176 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 107 DAG size of output: 74 [2018-11-23 09:55:45,962 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 115 DAG size of output: 76 [2018-11-23 09:55:46,416 WARN L180 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 110 DAG size of output: 73 [2018-11-23 09:55:46,741 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 67 [2018-11-23 09:55:47,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:55:47,904 INFO L93 Difference]: Finished difference Result 1895 states and 4796 transitions. [2018-11-23 09:55:47,904 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-11-23 09:55:47,904 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 102 [2018-11-23 09:55:47,905 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:55:47,905 INFO L225 Difference]: With dead ends: 1895 [2018-11-23 09:55:47,905 INFO L226 Difference]: Without dead ends: 1755 [2018-11-23 09:55:47,906 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 81 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1286 ImplicationChecksByTransitivity, 7.6s TimeCoverageRelationStatistics Valid=923, Invalid=5239, Unknown=0, NotChecked=0, Total=6162 [2018-11-23 09:55:47,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1755 states. [2018-11-23 09:55:47,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1755 to 1642. [2018-11-23 09:55:47,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1642 states. [2018-11-23 09:55:47,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1642 states to 1642 states and 4240 transitions. [2018-11-23 09:55:47,918 INFO L78 Accepts]: Start accepts. Automaton has 1642 states and 4240 transitions. Word has length 102 [2018-11-23 09:55:47,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:55:47,918 INFO L480 AbstractCegarLoop]: Abstraction has 1642 states and 4240 transitions. [2018-11-23 09:55:47,918 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-11-23 09:55:47,918 INFO L276 IsEmpty]: Start isEmpty. Operand 1642 states and 4240 transitions. [2018-11-23 09:55:47,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 09:55:47,919 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:55:47,919 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:55:47,919 INFO L423 AbstractCegarLoop]: === Iteration 46 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:55:47,919 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:55:47,919 INFO L82 PathProgramCache]: Analyzing trace with hash -804041717, now seen corresponding path program 8 times [2018-11-23 09:55:47,920 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:55:47,920 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:55:47,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:47,922 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:55:47,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:47,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:55:49,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:55:49,855 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:55:49,855 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [] total 33 [2018-11-23 09:55:49,856 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-23 09:55:49,856 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-23 09:55:49,856 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=971, Unknown=0, NotChecked=0, Total=1056 [2018-11-23 09:55:49,856 INFO L87 Difference]: Start difference. First operand 1642 states and 4240 transitions. Second operand 33 states. [2018-11-23 09:55:50,737 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 09:55:50,960 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 47 [2018-11-23 09:55:51,193 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 49 [2018-11-23 09:55:51,402 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 54 [2018-11-23 09:55:51,648 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 61 [2018-11-23 09:55:51,902 WARN L180 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 63 [2018-11-23 09:55:52,905 WARN L180 SmtUtils]: Spent 193.00 ms on a formula simplification. DAG size of input: 92 DAG size of output: 62 [2018-11-23 09:55:53,198 WARN L180 SmtUtils]: Spent 204.00 ms on a formula simplification. DAG size of input: 98 DAG size of output: 66 [2018-11-23 09:55:53,481 WARN L180 SmtUtils]: Spent 226.00 ms on a formula simplification. DAG size of input: 111 DAG size of output: 70 [2018-11-23 09:55:53,779 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 63 [2018-11-23 09:55:54,134 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 65 [2018-11-23 09:55:54,288 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 58 [2018-11-23 09:55:54,578 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 106 DAG size of output: 66 [2018-11-23 09:55:54,867 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 96 DAG size of output: 64 [2018-11-23 09:55:55,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:55:55,982 INFO L93 Difference]: Finished difference Result 1972 states and 4919 transitions. [2018-11-23 09:55:55,982 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-11-23 09:55:55,982 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 102 [2018-11-23 09:55:55,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:55:55,983 INFO L225 Difference]: With dead ends: 1972 [2018-11-23 09:55:55,983 INFO L226 Difference]: Without dead ends: 1845 [2018-11-23 09:55:55,983 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 973 ImplicationChecksByTransitivity, 6.1s TimeCoverageRelationStatistics Valid=837, Invalid=4133, Unknown=0, NotChecked=0, Total=4970 [2018-11-23 09:55:55,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1845 states. [2018-11-23 09:55:55,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1845 to 1646. [2018-11-23 09:55:55,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1646 states. [2018-11-23 09:55:55,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1646 states to 1646 states and 4246 transitions. [2018-11-23 09:55:55,995 INFO L78 Accepts]: Start accepts. Automaton has 1646 states and 4246 transitions. Word has length 102 [2018-11-23 09:55:55,995 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:55:55,995 INFO L480 AbstractCegarLoop]: Abstraction has 1646 states and 4246 transitions. [2018-11-23 09:55:55,995 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-23 09:55:55,995 INFO L276 IsEmpty]: Start isEmpty. Operand 1646 states and 4246 transitions. [2018-11-23 09:55:55,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 09:55:55,997 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:55:55,997 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:55:55,997 INFO L423 AbstractCegarLoop]: === Iteration 47 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:55:55,997 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:55:55,997 INFO L82 PathProgramCache]: Analyzing trace with hash -1961079829, now seen corresponding path program 1 times [2018-11-23 09:55:55,997 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:55:55,997 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:55:56,000 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:56,000 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 09:55:56,000 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:56,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 09:55:56,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 09:55:56,594 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 09:55:56,594 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2018-11-23 09:55:56,594 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-23 09:55:56,594 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-23 09:55:56,594 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2018-11-23 09:55:56,595 INFO L87 Difference]: Start difference. First operand 1646 states and 4246 transitions. Second operand 20 states. [2018-11-23 09:55:58,048 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 43 [2018-11-23 09:55:58,297 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 48 [2018-11-23 09:55:58,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 09:55:58,569 INFO L93 Difference]: Finished difference Result 2412 states and 6128 transitions. [2018-11-23 09:55:58,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-23 09:55:58,569 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 102 [2018-11-23 09:55:58,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 09:55:58,571 INFO L225 Difference]: With dead ends: 2412 [2018-11-23 09:55:58,571 INFO L226 Difference]: Without dead ends: 2377 [2018-11-23 09:55:58,571 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 121 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=382, Invalid=878, Unknown=0, NotChecked=0, Total=1260 [2018-11-23 09:55:58,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2377 states. [2018-11-23 09:55:58,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2377 to 1914. [2018-11-23 09:55:58,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1914 states. [2018-11-23 09:55:58,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 4893 transitions. [2018-11-23 09:55:58,587 INFO L78 Accepts]: Start accepts. Automaton has 1914 states and 4893 transitions. Word has length 102 [2018-11-23 09:55:58,587 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 09:55:58,587 INFO L480 AbstractCegarLoop]: Abstraction has 1914 states and 4893 transitions. [2018-11-23 09:55:58,587 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-23 09:55:58,587 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 4893 transitions. [2018-11-23 09:55:58,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 09:55:58,589 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 09:55:58,589 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 09:55:58,589 INFO L423 AbstractCegarLoop]: === Iteration 48 === [ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 09:55:58,589 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 09:55:58,589 INFO L82 PathProgramCache]: Analyzing trace with hash -326014713, now seen corresponding path program 9 times [2018-11-23 09:55:58,589 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 09:55:58,589 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 09:55:58,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:58,594 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 09:55:58,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 09:55:58,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 09:55:58,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 09:55:58,636 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [287] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [202] L-1-->L3774: Formula: (= |v_#valid_1| (store |v_#valid_2| 0 0)) InVars {#valid=|v_#valid_2|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [276] L3774-->L3774-1: Formula: (and (= (select |v_#valid_4| |v_~#t1~0.base_1|) 0) (not (= |v_~#t1~0.base_1| 0)) (= 0 |v_~#t1~0.offset_1|) (= |v_#length_1| (store |v_#length_2| |v_~#t1~0.base_1| 4)) (= (store |v_#valid_4| |v_~#t1~0.base_1| 1) |v_#valid_3|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_4|} OutVars{~#t1~0.offset=|v_~#t1~0.offset_1|, #length=|v_#length_1|, ~#t1~0.base=|v_~#t1~0.base_1|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[~#t1~0.base, #valid, ~#t1~0.offset, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0] [?] -1 [272] L3774-1-->L3774-2: Formula: (= 0 (select (select |v_#memory_int_1| |v_~#t1~0.base_2|) |v_~#t1~0.offset_2|)) InVars {#memory_int=|v_#memory_int_1|, ~#t1~0.offset=|v_~#t1~0.offset_2|, ~#t1~0.base=|v_~#t1~0.base_2|} OutVars{#memory_int=|v_#memory_int_1|, ~#t1~0.offset=|v_~#t1~0.offset_2|, ~#t1~0.base=|v_~#t1~0.base_2|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0] [?] -1 [278] L3774-2-->L3774-3: Formula: (and (= 0 (select |v_#valid_6| |v_~#t2~0.base_1|)) (= (store |v_#length_4| |v_~#t2~0.base_1| 4) |v_#length_3|) (not (= 0 |v_~#t2~0.base_1|)) (= 0 |v_~#t2~0.offset_1|) (= |v_#valid_5| (store |v_#valid_6| |v_~#t2~0.base_1| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_6|} OutVars{#length=|v_#length_3|, ~#t2~0.base=|v_~#t2~0.base_1|, ~#t2~0.offset=|v_~#t2~0.offset_1|, #valid=|v_#valid_5|} AuxVars[] AssignedVars[~#t2~0.offset, #valid, #length, ~#t2~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0] [?] -1 [280] L3774-3-->L3774-4: Formula: (= (select (select |v_#memory_int_2| |v_~#t2~0.base_2|) |v_~#t2~0.offset_2|) 0) InVars {#memory_int=|v_#memory_int_2|, ~#t2~0.base=|v_~#t2~0.base_2|, ~#t2~0.offset=|v_~#t2~0.offset_2|} OutVars{#memory_int=|v_#memory_int_2|, ~#t2~0.base=|v_~#t2~0.base_2|, ~#t2~0.offset=|v_~#t2~0.offset_2|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0] [?] -1 [277] L3774-4-->L-1-1: Formula: (and (= v_~my_dev~0.base_1 0) (= v_~my_dev~0.offset_1 0)) InVars {} OutVars{~my_dev~0.offset=v_~my_dev~0.offset_1, ~my_dev~0.base=v_~my_dev~0.base_1} AuxVars[] AssignedVars[~my_dev~0.base, ~my_dev~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [308] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [307] L-1-2-->L3847: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~mem45=|v_ULTIMATE.start_main_#t~mem45_1|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_1|, ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_1, ULTIMATE.start_main_#t~mem44=|v_ULTIMATE.start_main_#t~mem44_1|, ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_1|, ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_1|, ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_1|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_1|, ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_1, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem45, ULTIMATE.start_main_#t~mem43, ULTIMATE.start_main_~ret~0, ULTIMATE.start_main_#t~mem44, ULTIMATE.start_main_#t~ret40, ULTIMATE.start_main_#t~mem42, ULTIMATE.start_main_#t~ret41, ULTIMATE.start_main_~#data~1.offset, ULTIMATE.start_main_~probe_ret~0, ULTIMATE.start_main_~#data~1.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [204] L3847-->L3839: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_init_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [195] L3839-->L3839-1: Formula: (= |v_ULTIMATE.start_my_drv_init_#res_2| 0) InVars {} OutVars{ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_init_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [318] L3839-1-->L3847-1: Formula: (= |v_ULTIMATE.start_main_#t~ret40_2| |v_ULTIMATE.start_my_drv_init_#res_3|) InVars {ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_3|} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_2|, ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret40] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [214] L3847-1-->L3847-2: Formula: (and (<= 0 (+ |v_ULTIMATE.start_main_#t~ret40_3| 2147483648)) (<= |v_ULTIMATE.start_main_#t~ret40_3| 2147483647)) InVars {ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_3|} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_3|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [209] L3847-2-->L3847-3: Formula: (= v_ULTIMATE.start_main_~ret~0_2 |v_ULTIMATE.start_main_#t~ret40_4|) InVars {ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_4|} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_4|, ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_~ret~0] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [191] L3847-3-->L3848: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret40] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [285] L3848-->L3849: Formula: (= v_ULTIMATE.start_main_~ret~0_3 0) InVars {ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_3} OutVars{ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_3} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [253] L3849-->L3850: Formula: true InVars {} OutVars{ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_~probe_ret~0] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [196] L3850-->L3850-1: Formula: (and (= 0 |v_ULTIMATE.start_main_~#data~1.offset_2|) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#data~1.base_2|) 0) (not (= |v_ULTIMATE.start_main_~#data~1.base_2| 0)) (= (store |v_#length_6| |v_ULTIMATE.start_main_~#data~1.base_2| 48) |v_#length_5|) (= (store |v_#valid_8| |v_ULTIMATE.start_main_~#data~1.base_2| 1) |v_#valid_7|)) InVars {#length=|v_#length_6|, #valid=|v_#valid_8|} OutVars{ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_2|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[#valid, ULTIMATE.start_main_~#data~1.offset, #length, ULTIMATE.start_main_~#data~1.base] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [314] L3850-1-->L3851: Formula: (and (= |v_ULTIMATE.start_my_drv_probe_#in~data.base_1| |v_ULTIMATE.start_main_~#data~1.base_3|) (= |v_ULTIMATE.start_my_drv_probe_#in~data.offset_1| |v_ULTIMATE.start_main_~#data~1.offset_3|)) InVars {ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_3|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_3|} OutVars{ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_1|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_3|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_3|, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#in~data.base, ULTIMATE.start_my_drv_probe_#in~data.offset] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [284] L3851-->L3851-1: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#res] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [283] L3851-1-->L3805: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_1|, ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_1, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_1, ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_1|, ULTIMATE.start_my_drv_probe_#t~nondet35=|v_ULTIMATE.start_my_drv_probe_#t~nondet35_1|, ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_1, ULTIMATE.start_my_drv_probe_#t~nondet34=|v_ULTIMATE.start_my_drv_probe_#t~nondet34_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem31, ULTIMATE.start_my_drv_probe_#t~mem32, ULTIMATE.start_my_drv_probe_~data.base, ULTIMATE.start_my_drv_probe_~data.offset, ULTIMATE.start_my_drv_probe_#t~nondet33, ULTIMATE.start_my_drv_probe_#t~nondet35, ULTIMATE.start_my_drv_probe_~res~0, ULTIMATE.start_my_drv_probe_#t~nondet34] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [252] L3805-->L3808: Formula: (and (= v_ULTIMATE.start_my_drv_probe_~data.offset_2 |v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|) (= v_ULTIMATE.start_my_drv_probe_~data.base_2 |v_ULTIMATE.start_my_drv_probe_#in~data.base_2|)) InVars {ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_2|, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|} OutVars{ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_2, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_2, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~data.base, ULTIMATE.start_my_drv_probe_~data.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [242] L3808-->L3809: Formula: (= |v_#pthreadsMutex_1| (store |v_#pthreadsMutex_2| v_ULTIMATE.start_my_drv_probe_~data.base_3 (store (select |v_#pthreadsMutex_2| v_ULTIMATE.start_my_drv_probe_~data.base_3) v_ULTIMATE.start_my_drv_probe_~data.offset_3 0))) InVars {#pthreadsMutex=|v_#pthreadsMutex_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_3, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_3} OutVars{#pthreadsMutex=|v_#pthreadsMutex_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_3, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_3} AuxVars[] AssignedVars[#pthreadsMutex] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [309] L3809-->L3809-1: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_4 40))) (and (= |v_#memory_$Pointer$.offset_1| (store |v_#memory_$Pointer$.offset_2| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#memory_$Pointer$.offset_2| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0 (select (select |v_#memory_$Pointer$.offset_1| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0)))) (= |v_#memory_int_3| (store |v_#memory_int_4| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#memory_int_4| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0 0))) (= (store |v_#memory_$Pointer$.base_2| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#memory_$Pointer$.base_2| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0 (select (select |v_#memory_$Pointer$.base_1| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0))) |v_#memory_$Pointer$.base_1|))) InVars {#memory_int=|v_#memory_int_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_4, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_2|} OutVars{#memory_int=|v_#memory_int_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_4, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_1|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [306] L3809-1-->L3810: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_5 44))) (and (= |v_#memory_$Pointer$.base_3| (store |v_#memory_$Pointer$.base_4| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_$Pointer$.base_4| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_3| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0)))) (= |v_#memory_int_5| (store |v_#memory_int_6| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_int_6| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 0))) (= |v_#memory_$Pointer$.offset_3| (store |v_#memory_$Pointer$.offset_4| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_$Pointer$.offset_4| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_3| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0)))))) InVars {#memory_int=|v_#memory_int_6|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_4|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_5, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_4|} OutVars{#memory_int=|v_#memory_int_5|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_3|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_5, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_3|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [267] L3810-->L3811: Formula: (= (select (select |v_#memory_int_7| v_ULTIMATE.start_my_drv_probe_~data.base_6) (+ v_ULTIMATE.start_my_drv_probe_~data.offset_6 40)) |v_ULTIMATE.start_my_drv_probe_#t~mem31_2|) InVars {#memory_int=|v_#memory_int_7|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_6, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_6} OutVars{#memory_int=|v_#memory_int_7|, ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_6, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_6} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem31] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [224] L3811-->L3811-1: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_1| (ite (= 0 |v_ULTIMATE.start_my_drv_probe_#t~mem31_3|) 1 0)) InVars {ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [219] L3811-1-->L3772: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [259] L3772-->L3772-1: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_2 |v_ULTIMATE.start_ldv_assert_#in~expression_2|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_2|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_2|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_2} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [262] L3772-1-->L3772-4: Formula: (not (= 0 v_ULTIMATE.start_ldv_assert_~expression_4)) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_4} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_4} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [239] L3772-4-->L3812: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem31] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [296] L3812-->L3812-1: Formula: (= (select (select |v_#memory_int_8| v_ULTIMATE.start_my_drv_probe_~data.base_7) (+ v_ULTIMATE.start_my_drv_probe_~data.offset_7 44)) |v_ULTIMATE.start_my_drv_probe_#t~mem32_2|) InVars {#memory_int=|v_#memory_int_8|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_7, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_7} OutVars{#memory_int=|v_#memory_int_8|, ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_7, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_7} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem32] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [299] L3812-1-->L3812-2: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_3| (ite (= 0 |v_ULTIMATE.start_my_drv_probe_#t~mem32_3|) 1 0)) InVars {ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_3|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [294] L3812-2-->L3772-5: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_5} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [241] L3772-5-->L3772-6: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_6 |v_ULTIMATE.start_ldv_assert_#in~expression_4|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_4|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_4|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_6} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [249] L3772-6-->L3772-9: Formula: (not (= 0 v_ULTIMATE.start_ldv_assert_~expression_8)) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_8} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_8} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [233] L3772-9-->L3814: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem32] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [211] L3814-->L3814-1: Formula: (and (<= 0 (+ |v_ULTIMATE.start_my_drv_probe_#t~nondet33_2| 2147483648)) (<= |v_ULTIMATE.start_my_drv_probe_#t~nondet33_2| 2147483647)) InVars {ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_2|} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_2|} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [210] L3814-1-->L3814-2: Formula: (= v_ULTIMATE.start_my_drv_probe_~res~0_2 |v_ULTIMATE.start_my_drv_probe_#t~nondet33_3|) InVars {ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_3|, ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_2} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~res~0] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [189] L3814-2-->L3815: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet33] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [289] L3815-->L3819: Formula: (= v_ULTIMATE.start_my_drv_probe_~res~0_4 0) InVars {ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_4} OutVars{ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_4} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [250] L3819-->L3822: Formula: (and (= v_~my_dev~0.base_2 v_ULTIMATE.start_my_drv_probe_~data.base_8) (= v_~my_dev~0.offset_2 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_8 40))) InVars {ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_8, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_8} OutVars{~my_dev~0.offset=v_~my_dev~0.offset_2, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_8, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_8, ~my_dev~0.base=v_~my_dev~0.base_2} AuxVars[] AssignedVars[~my_dev~0.base, ~my_dev~0.offset] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [222] L3822-->L3822-1: Formula: (and (= (store |v_#memory_int_10| |v_~#t1~0.base_3| (store (select |v_#memory_int_10| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| 0)) |v_#memory_int_9|) (= |v_#memory_$Pointer$.offset_5| (store |v_#memory_$Pointer$.offset_6| |v_~#t1~0.base_3| (store (select |v_#memory_$Pointer$.offset_6| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| (select (select |v_#memory_$Pointer$.offset_5| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3|)))) (= (store |v_#memory_$Pointer$.base_6| |v_~#t1~0.base_3| (store (select |v_#memory_$Pointer$.base_6| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| (select (select |v_#memory_$Pointer$.base_5| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3|))) |v_#memory_$Pointer$.base_5|)) InVars {#memory_int=|v_#memory_int_10|, ~#t1~0.offset=|v_~#t1~0.offset_3|, ~#t1~0.base=|v_~#t1~0.base_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_6|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_6|} OutVars{#memory_int=|v_#memory_int_9|, ~#t1~0.offset=|v_~#t1~0.offset_3|, ~#t1~0.base=|v_~#t1~0.base_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_5|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_5|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] FORK -1 [340] L3822-1-->my_callbackENTRY: Formula: (and (= 0 |v_Thread0_my_callback_#in~arg.offset_3|) (= 0 |v_Thread0_my_callback_#in~arg.base_3|) (= v_Thread0_my_callback_thidvar0_2 0)) InVars {} OutVars{Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_3|, Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_2, Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_my_callback_#in~arg.base, Thread0_my_callback_thidvar0, Thread0_my_callback_#in~arg.offset] VAL [Thread0_my_callback_thidvar0=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [320] my_callbackENTRY-->L3794: Formula: (and (= v_Thread0_my_callback_~arg.offset_1 |v_Thread0_my_callback_#in~arg.offset_1|) (= v_Thread0_my_callback_~arg.base_1 |v_Thread0_my_callback_#in~arg.base_1|)) InVars {Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_1|, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_1|} OutVars{Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_1|, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_1|, Thread0_my_callback_~arg.offset=v_Thread0_my_callback_~arg.offset_1, Thread0_my_callback_~arg.base=v_Thread0_my_callback_~arg.base_1} AuxVars[] AssignedVars[Thread0_my_callback_~arg.offset, Thread0_my_callback_~arg.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [321] L3794-->L3795: Formula: true InVars {} OutVars{Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_1, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_1} AuxVars[] AssignedVars[Thread0_my_callback_~data~0.offset, Thread0_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [226] L3822-2-->L3823: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet34=|v_ULTIMATE.start_my_drv_probe_#t~nondet34_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet34] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [322] L3795-->L3795-1: Formula: (and (= v_Thread0_my_callback_~__mptr~0.offset_1 v_~my_dev~0.offset_3) (= v_Thread0_my_callback_~__mptr~0.base_1 v_~my_dev~0.base_3)) InVars {~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3} OutVars{Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_1, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_1, ~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3} AuxVars[] AssignedVars[Thread0_my_callback_~__mptr~0.base, Thread0_my_callback_~__mptr~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [323] L3795-1-->L3799: Formula: (and (= v_Thread0_my_callback_~data~0.base_2 v_Thread0_my_callback_~__mptr~0.base_2) (= v_Thread0_my_callback_~data~0.offset_2 (+ v_Thread0_my_callback_~__mptr~0.offset_2 (- 40)))) InVars {Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_2, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_2} OutVars{Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_2, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_2, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_2, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_2} AuxVars[] AssignedVars[Thread0_my_callback_~data~0.offset, Thread0_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [324] L3799-->L3799-1: Formula: (let ((.cse0 (+ v_Thread0_my_callback_~data~0.offset_3 40))) (and (= |v_#memory_$Pointer$.base_17| (store |v_#memory_$Pointer$.base_18| v_Thread0_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.base_18| v_Thread0_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.base_17| v_Thread0_my_callback_~data~0.base_3) .cse0)))) (= (store |v_#memory_$Pointer$.offset_18| v_Thread0_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.offset_18| v_Thread0_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.offset_17| v_Thread0_my_callback_~data~0.base_3) .cse0))) |v_#memory_$Pointer$.offset_17|) (= (store |v_#memory_int_28| v_Thread0_my_callback_~data~0.base_3 (store (select |v_#memory_int_28| v_Thread0_my_callback_~data~0.base_3) .cse0 1)) |v_#memory_int_27|))) InVars {#memory_int=|v_#memory_int_28|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_18|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_18|} OutVars{#memory_int=|v_#memory_int_27|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_17|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_17|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [325] L3799-1-->L3800: Formula: (= |v_Thread0_my_callback_#t~mem30_1| (select (select |v_#memory_int_29| v_Thread0_my_callback_~data~0.base_4) (+ v_Thread0_my_callback_~data~0.offset_4 44))) InVars {#memory_int=|v_#memory_int_29|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_4, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_4} OutVars{#memory_int=|v_#memory_int_29|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_4, Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_1|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_4} AuxVars[] AssignedVars[Thread0_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [302] L3823-->L3823-1: Formula: (and (= (store |v_#memory_$Pointer$.base_8| |v_~#t2~0.base_3| (store (select |v_#memory_$Pointer$.base_8| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| (select (select |v_#memory_$Pointer$.base_7| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3|))) |v_#memory_$Pointer$.base_7|) (= (store |v_#memory_$Pointer$.offset_8| |v_~#t2~0.base_3| (store (select |v_#memory_$Pointer$.offset_8| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| (select (select |v_#memory_$Pointer$.offset_7| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3|))) |v_#memory_$Pointer$.offset_7|) (= |v_#memory_int_11| (store |v_#memory_int_12| |v_~#t2~0.base_3| (store (select |v_#memory_int_12| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| 1)))) InVars {#memory_int=|v_#memory_int_12|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_8|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_8|, ~#t2~0.base=|v_~#t2~0.base_3|, ~#t2~0.offset=|v_~#t2~0.offset_3|} OutVars{#memory_int=|v_#memory_int_11|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_7|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_7|, ~#t2~0.base=|v_~#t2~0.base_3|, ~#t2~0.offset=|v_~#t2~0.offset_3|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] FORK -1 [341] L3823-1-->my_callbackENTRY: Formula: (and (= |v_Thread1_my_callback_#in~arg.base_3| 0) (= 0 |v_Thread1_my_callback_#in~arg.offset_3|) (= v_Thread1_my_callback_thidvar0_2 1)) InVars {} OutVars{Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_2, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_3|, Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_my_callback_thidvar0, Thread1_my_callback_#in~arg.base, Thread1_my_callback_#in~arg.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [292] L3823-2-->L3824: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet35=|v_ULTIMATE.start_my_drv_probe_#t~nondet35_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet35] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [264] L3824-->L3828: Formula: (= |v_ULTIMATE.start_my_drv_probe_#res_2| 0) InVars {} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#res] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [330] my_callbackENTRY-->L3794: Formula: (and (= v_Thread1_my_callback_~arg.offset_1 |v_Thread1_my_callback_#in~arg.offset_1|) (= v_Thread1_my_callback_~arg.base_1 |v_Thread1_my_callback_#in~arg.base_1|)) InVars {Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_1|, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_1|} OutVars{Thread1_my_callback_~arg.base=v_Thread1_my_callback_~arg.base_1, Thread1_my_callback_~arg.offset=v_Thread1_my_callback_~arg.offset_1, Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_1|, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_1|} AuxVars[] AssignedVars[Thread1_my_callback_~arg.base, Thread1_my_callback_~arg.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [315] L3828-->L3851-2: Formula: (= |v_ULTIMATE.start_main_#t~ret41_2| |v_ULTIMATE.start_my_drv_probe_#res_4|) InVars {ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_4|} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_4|, ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret41] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [275] L3851-2-->L3851-3: Formula: (and (<= |v_ULTIMATE.start_main_#t~ret41_3| 2147483647) (<= 0 (+ |v_ULTIMATE.start_main_#t~ret41_3| 2147483648))) InVars {ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_3|} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_3|} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [273] L3851-3-->L3851-4: Formula: (= v_ULTIMATE.start_main_~probe_ret~0_3 |v_ULTIMATE.start_main_#t~ret41_4|) InVars {ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_4|} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_4|, ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_~probe_ret~0] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [274] L3851-4-->L3852: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret41] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [246] L3852-->L3853: Formula: (= v_ULTIMATE.start_main_~probe_ret~0_4 0) InVars {ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_4} OutVars{ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_4} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [304] L3853-->L3853-1: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#in~data.base_1| |v_ULTIMATE.start_main_~#data~1.base_4|) (= |v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_1| |v_ULTIMATE.start_main_~#data~1.offset_4|)) InVars {ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_4|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_4|} OutVars{ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_4|, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_1|, ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_1|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#in~data.offset, ULTIMATE.start_my_drv_disconnect_#in~data.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [310] L3853-1-->L3831: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_1|, ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_1, ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_1|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_1|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_1, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_1|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38, ULTIMATE.start_my_drv_disconnect_~data.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~data.base, ULTIMATE.start_my_drv_disconnect_~#status~0.base, ULTIMATE.start_my_drv_disconnect_#t~mem36, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [305] L3831-->L3832: Formula: (and (= v_ULTIMATE.start_my_drv_disconnect_~data.base_2 |v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|) (= v_ULTIMATE.start_my_drv_disconnect_~data.offset_2 |v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|)) InVars {ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|} OutVars{ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_2, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_2, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|, ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~data.offset, ULTIMATE.start_my_drv_disconnect_~data.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [266] L3832-->L3832-1: Formula: (and (= |v_#length_7| (store |v_#length_8| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2| 4)) (= (store |v_#valid_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2| 1) |v_#valid_9|) (= 0 (select |v_#valid_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|)) (= |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|))) InVars {#length=|v_#length_8|, #valid=|v_#valid_10|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_2|, #length=|v_#length_7|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.base, #valid, #length] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [331] L3794-->L3795: Formula: true InVars {} OutVars{Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_1, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_1} AuxVars[] AssignedVars[Thread1_my_callback_~data~0.offset, Thread1_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [332] L3795-->L3795-1: Formula: (and (= v_Thread1_my_callback_~__mptr~0.offset_1 v_~my_dev~0.offset_3) (= v_Thread1_my_callback_~__mptr~0.base_1 v_~my_dev~0.base_3)) InVars {~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3} OutVars{~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3, Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_1, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_1} AuxVars[] AssignedVars[Thread1_my_callback_~__mptr~0.base, Thread1_my_callback_~__mptr~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [268] L3832-1-->L3833: Formula: (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem36_2| (select (select |v_#memory_int_13| |v_~#t1~0.base_4|) |v_~#t1~0.offset_4|)) InVars {#memory_int=|v_#memory_int_13|, ~#t1~0.offset=|v_~#t1~0.offset_4|, ~#t1~0.base=|v_~#t1~0.base_4|} OutVars{#memory_int=|v_#memory_int_13|, ~#t1~0.offset=|v_~#t1~0.offset_4|, ~#t1~0.base=|v_~#t1~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem36] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [333] L3795-1-->L3799: Formula: (and (= v_Thread1_my_callback_~data~0.base_2 v_Thread1_my_callback_~__mptr~0.base_2) (= v_Thread1_my_callback_~data~0.offset_2 (+ v_Thread1_my_callback_~__mptr~0.offset_2 (- 40)))) InVars {Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_2, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_2} OutVars{Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_2, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_2, Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_2, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_2} AuxVars[] AssignedVars[Thread1_my_callback_~data~0.offset, Thread1_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [334] L3799-->L3799-1: Formula: (let ((.cse0 (+ v_Thread1_my_callback_~data~0.offset_3 40))) (and (= |v_#memory_$Pointer$.base_17| (store |v_#memory_$Pointer$.base_18| v_Thread1_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.base_18| v_Thread1_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.base_17| v_Thread1_my_callback_~data~0.base_3) .cse0)))) (= (store |v_#memory_$Pointer$.offset_18| v_Thread1_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.offset_18| v_Thread1_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.offset_17| v_Thread1_my_callback_~data~0.base_3) .cse0))) |v_#memory_$Pointer$.offset_17|) (= (store |v_#memory_int_28| v_Thread1_my_callback_~data~0.base_3 (store (select |v_#memory_int_28| v_Thread1_my_callback_~data~0.base_3) .cse0 1)) |v_#memory_int_27|))) InVars {#memory_int=|v_#memory_int_28|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_18|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_18|} OutVars{#memory_int=|v_#memory_int_27|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_17|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_17|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [335] L3799-1-->L3800: Formula: (= |v_Thread1_my_callback_#t~mem30_1| (select (select |v_#memory_int_29| v_Thread1_my_callback_~data~0.base_4) (+ v_Thread1_my_callback_~data~0.offset_4 44))) InVars {#memory_int=|v_#memory_int_29|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_4, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_4} OutVars{#memory_int=|v_#memory_int_29|, Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_1|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_4, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_4} AuxVars[] AssignedVars[Thread1_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [336] L3800-->L3800-1: Formula: (let ((.cse0 (+ v_Thread1_my_callback_~data~0.offset_5 44))) (and (= |v_#memory_$Pointer$.offset_19| (store |v_#memory_$Pointer$.offset_20| v_Thread1_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.offset_20| v_Thread1_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_19| v_Thread1_my_callback_~data~0.base_5) .cse0)))) (= |v_#memory_$Pointer$.base_19| (store |v_#memory_$Pointer$.base_20| v_Thread1_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.base_20| v_Thread1_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_19| v_Thread1_my_callback_~data~0.base_5) .cse0)))) (= (store |v_#memory_int_31| v_Thread1_my_callback_~data~0.base_5 (store (select |v_#memory_int_31| v_Thread1_my_callback_~data~0.base_5) .cse0 (+ |v_Thread1_my_callback_#t~mem30_2| 1))) |v_#memory_int_30|))) InVars {#memory_$Pointer$.base=|v_#memory_$Pointer$.base_20|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_31|, Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_2|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_20|} OutVars{#memory_$Pointer$.base=|v_#memory_$Pointer$.base_19|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_30|, Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_2|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_19|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [337] L3800-1-->L3802: Formula: true InVars {} OutVars{Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_3|} AuxVars[] AssignedVars[Thread1_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [338] L3802-->my_callbackFINAL: Formula: (and (= |v_Thread1_my_callback_#res.offset_1| 0) (= |v_Thread1_my_callback_#res.base_1| 0)) InVars {} OutVars{Thread1_my_callback_#res.offset=|v_Thread1_my_callback_#res.offset_1|, Thread1_my_callback_#res.base=|v_Thread1_my_callback_#res.base_1|} AuxVars[] AssignedVars[Thread1_my_callback_#res.offset, Thread1_my_callback_#res.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [339] my_callbackFINAL-->my_callbackEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [326] L3800-->L3800-1: Formula: (let ((.cse0 (+ v_Thread0_my_callback_~data~0.offset_5 44))) (and (= |v_#memory_$Pointer$.offset_19| (store |v_#memory_$Pointer$.offset_20| v_Thread0_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.offset_20| v_Thread0_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_19| v_Thread0_my_callback_~data~0.base_5) .cse0)))) (= |v_#memory_$Pointer$.base_19| (store |v_#memory_$Pointer$.base_20| v_Thread0_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.base_20| v_Thread0_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_19| v_Thread0_my_callback_~data~0.base_5) .cse0)))) (= (store |v_#memory_int_31| v_Thread0_my_callback_~data~0.base_5 (store (select |v_#memory_int_31| v_Thread0_my_callback_~data~0.base_5) .cse0 (+ |v_Thread0_my_callback_#t~mem30_2| 1))) |v_#memory_int_30|))) InVars {#memory_$Pointer$.base=|v_#memory_$Pointer$.base_20|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_31|, Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_2|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_20|} OutVars{#memory_$Pointer$.base=|v_#memory_$Pointer$.base_19|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_30|, Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_2|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_19|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [327] L3800-1-->L3802: Formula: true InVars {} OutVars{Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_3|} AuxVars[] AssignedVars[Thread0_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [328] L3802-->my_callbackFINAL: Formula: (and (= |v_Thread0_my_callback_#res.offset_1| 0) (= |v_Thread0_my_callback_#res.base_1| 0)) InVars {} OutVars{Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_1|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_1|} AuxVars[] AssignedVars[Thread0_my_callback_#res.base, Thread0_my_callback_#res.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [329] my_callbackFINAL-->my_callbackEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] JOIN 0 [342] my_callbackEXIT-->L3833-1: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem36_5| v_Thread0_my_callback_thidvar0_4) (= |v_Thread0_my_callback_#res.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_5|) (= |v_Thread0_my_callback_#res.base_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_5|)) InVars {Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_4, Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_3|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_5|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_3|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_5|, Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_4, Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_3|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_5|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_5|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [217] L3833-1-->L3833-2: Formula: (and (= |v_#memory_$Pointer$.offset_9| (store |v_#memory_$Pointer$.offset_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_$Pointer$.offset_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_2|))) (= (store |v_#memory_$Pointer$.base_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_$Pointer$.base_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_2|)) |v_#memory_$Pointer$.base_9|) (= (store |v_#memory_int_15| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_int_15| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| (select (select |v_#memory_int_14| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|))) |v_#memory_int_14|)) InVars {ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_2|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_10|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_2|, #memory_int=|v_#memory_int_15|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_10|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_2|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_9|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_2|, #memory_int=|v_#memory_int_14|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_9|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [220] L3833-2-->L3833-3: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem36] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [229] L3833-3-->L3834: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [303] L3834-->L3834-1: Formula: (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem38_2| (select (select |v_#memory_int_16| |v_~#t2~0.base_4|) |v_~#t2~0.offset_4|)) InVars {#memory_int=|v_#memory_int_16|, ~#t2~0.base=|v_~#t2~0.base_4|, ~#t2~0.offset=|v_~#t2~0.offset_4|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_2|, #memory_int=|v_#memory_int_16|, ~#t2~0.base=|v_~#t2~0.base_4|, ~#t2~0.offset=|v_~#t2~0.offset_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] JOIN 1 [345] my_callbackEXIT-->L3834-2: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_7| |v_Thread1_my_callback_#res.offset_5|) (= |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_7| |v_Thread1_my_callback_#res.base_5|) (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem38_7| v_Thread1_my_callback_thidvar0_6)) InVars {ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_7|, Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_6, Thread1_my_callback_#res.offset=|v_Thread1_my_callback_#res.offset_5|, Thread1_my_callback_#res.base=|v_Thread1_my_callback_#res.base_5|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_7|, Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_6, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_7|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_7|, Thread1_my_callback_#res.offset=|v_Thread1_my_callback_#res.offset_5|, Thread1_my_callback_#res.base=|v_Thread1_my_callback_#res.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [293] L3834-2-->L3834-3: Formula: (and (= (store |v_#memory_$Pointer$.base_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4| (store (select |v_#memory_$Pointer$.base_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_2|)) |v_#memory_$Pointer$.base_11|) (= |v_#memory_$Pointer$.offset_11| (store |v_#memory_$Pointer$.offset_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4| (store (select |v_#memory_$Pointer$.offset_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_2|))) (= (store |v_#memory_int_18| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4| (store (select |v_#memory_int_18| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4| (select (select |v_#memory_int_17| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4|))) |v_#memory_int_17|)) InVars {ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_12|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_2|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_2|, #memory_int=|v_#memory_int_18|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_12|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_11|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_2|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_2|, #memory_int=|v_#memory_int_17|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_11|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [295] L3834-3-->L3834-4: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [300] L3834-4-->L3832-2: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [271] L3832-2-->L3832-3: Formula: (= (store |v_#valid_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_5| 0) |v_#valid_11|) InVars {ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_5|, #valid=|v_#valid_12|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_5|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [270] L3832-3-->L3831-1: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_6|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_6|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [311] L3831-1-->L3854: Formula: (= (select (select |v_#memory_int_19| |v_ULTIMATE.start_main_~#data~1.base_5|) (+ |v_ULTIMATE.start_main_~#data~1.offset_5| 40)) |v_ULTIMATE.start_main_#t~mem42_2|) InVars {#memory_int=|v_#memory_int_19|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_5|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_5|} OutVars{#memory_int=|v_#memory_int_19|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_5|, ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_2|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem42] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [269] L3854-->L3854-1: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_5| (ite (= |v_ULTIMATE.start_main_#t~mem42_3| 1) 1 0)) InVars {ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_3|} OutVars{ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [265] L3854-1-->L3772-10: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_9} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [232] L3772-10-->L3772-11: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_10 |v_ULTIMATE.start_ldv_assert_#in~expression_6|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_6|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_6|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_10} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [238] L3772-11-->L3772-14: Formula: (not (= v_ULTIMATE.start_ldv_assert_~expression_12 0)) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_12} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_12} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [223] L3772-14-->L3855: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem42] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [236] L3855-->L3855-1: Formula: (= |v_ULTIMATE.start_main_#t~mem43_2| (select (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#data~1.base_6|) (+ |v_ULTIMATE.start_main_~#data~1.offset_6| 44))) InVars {#memory_int=|v_#memory_int_20|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_6|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_6|} OutVars{#memory_int=|v_#memory_int_20|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_2|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_6|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem43] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [225] L3855-1-->L3855-2: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_7| (ite (= |v_ULTIMATE.start_main_#t~mem43_3| 2) 1 0)) InVars {ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_3|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_7|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_3|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [215] L3855-2-->L3772-15: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_13} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [218] L3772-15-->L3772-16: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_14 |v_ULTIMATE.start_ldv_assert_#in~expression_8|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_8|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_8|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_14} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [227] L3772-16-->L3772-17: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_15 0) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_15} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_15} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [230] L3772-17-->ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 SUMMARY for call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); srcloc: L3774 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3774-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0] [?] -1 SUMMARY for call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); srcloc: L3774-2 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3774-3 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_init_#res := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_#t~ret40 := my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_~ret~0 := main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume 0 == main_~ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_~probe_ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); srcloc: L3850 VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#res; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3809 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3809-1 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3810 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3812 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem32; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 != my_drv_probe_~res~0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3822 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] FORK -1 fork 0 my_callback(0, 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet34; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3823 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] FORK -1 fork 1 my_callback(0, 0); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet35; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 my_drv_probe_#res := 0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 main_#t~ret41 := my_drv_probe_#res; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 main_~probe_ret~0 := main_#t~ret41; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc main_#t~ret41; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume 0 == main_~probe_ret~0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); srcloc: L3832 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3832-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 assume true; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 assume true; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3833-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3834 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3834-2 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem38; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); srcloc: L3832-2 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); srcloc: L3831-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume !(0 == ldv_assert_~expression); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc main_#t~mem42; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); srcloc: L3855 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume 0 == ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume !false; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 SUMMARY for call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); srcloc: L3774 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3774-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0] [?] -1 SUMMARY for call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); srcloc: L3774-2 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3774-3 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_init_#res := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_#t~ret40 := my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_~ret~0 := main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume 0 == main_~ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_~probe_ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); srcloc: L3850 VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#res; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3809 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3809-1 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3810 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3812 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem32; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 != my_drv_probe_~res~0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3822 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] FORK -1 fork 0 my_callback(0, 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet34; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3823 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] FORK -1 fork 1 my_callback(0, 0); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet35; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 my_drv_probe_#res := 0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 main_#t~ret41 := my_drv_probe_#res; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 main_~probe_ret~0 := main_#t~ret41; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc main_#t~ret41; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume 0 == main_~probe_ret~0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); srcloc: L3832 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3832-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 assume true; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 assume true; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3833-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3834 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3834-2 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem38; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); srcloc: L3832-2 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); srcloc: L3831-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume !(0 == ldv_assert_~expression); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc main_#t~mem42; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); srcloc: L3855 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume 0 == ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume !false; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L3774] -1 call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0] [L3774] -1 call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0] [L3774] -1 call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0] [L3774] -1 call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0] [L3791] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL.base=0, #NULL.offset=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3848-L3862] -1 assume 0 == main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3850] -1 call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3805-L3829] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3808] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3809] -1 call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3810] -1 call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3815-L3816] -1 assume !(0 != my_drv_probe_~res~0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3819] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3822] -1 call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3822] FORK -1 fork 0 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3794] 0 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3799] 0 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 0 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3823] -1 call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3823] FORK -1 fork 1 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3852-L3856] -1 assume 0 == main_~probe_ret~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3853] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3831-L3836] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3832] -1 call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3794] 1 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3799] 1 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 1 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 1 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3802] 1 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 1 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 0 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3802] 0 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 0 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3832] -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3855] -1 call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 assume 0 == ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 assert false; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L3774] -1 call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0] [L3774] -1 call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0] [L3774] -1 call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0] [L3774] -1 call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0] [L3791] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL.base=0, #NULL.offset=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3848-L3862] -1 assume 0 == main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3850] -1 call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3805-L3829] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3808] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3809] -1 call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3810] -1 call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3815-L3816] -1 assume !(0 != my_drv_probe_~res~0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3819] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3822] -1 call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3822] FORK -1 fork 0 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3794] 0 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3799] 0 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 0 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3823] -1 call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3823] FORK -1 fork 1 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3852-L3856] -1 assume 0 == main_~probe_ret~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3853] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3831-L3836] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3832] -1 call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3794] 1 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3799] 1 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 1 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 1 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3802] 1 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 1 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 0 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3802] 0 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 0 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3832] -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3855] -1 call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 assume 0 == ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 assert false; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1, main_~ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL!base=0, #NULL!offset=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == main_~ret~0 VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call main_~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 my_drv_probe_#in~data := main_~#data~1; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data, my_drv_probe_~res~0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 my_drv_probe_~data := my_drv_probe_#in~data; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: my_drv_probe_~data!base, offset: my_drv_probe_~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call my_drv_probe_#t~mem31 := read~int({ base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call my_drv_probe_#t~mem32 := read~int({ base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != my_drv_probe_~res~0) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == main_~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3853] -1 my_drv_disconnect_#in~data := main_~#data~1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39, my_drv_disconnect_~data, my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3831-L3836] -1 my_drv_disconnect_~data := my_drv_disconnect_#in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call my_drv_disconnect_~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] FCALL -1 call main_#t~mem42 := read~int({ base: main_~#data~1!base, offset: 40 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] FCALL -1 call main_#t~mem43 := read~int({ base: main_~#data~1!base, offset: 44 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ldv_assert_~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1, main_~ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL!base=0, #NULL!offset=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == main_~ret~0 VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call main_~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 my_drv_probe_#in~data := main_~#data~1; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data, my_drv_probe_~res~0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 my_drv_probe_~data := my_drv_probe_#in~data; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: my_drv_probe_~data!base, offset: my_drv_probe_~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call my_drv_probe_#t~mem31 := read~int({ base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call my_drv_probe_#t~mem32 := read~int({ base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != my_drv_probe_~res~0) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == main_~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3853] -1 my_drv_disconnect_#in~data := main_~#data~1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39, my_drv_disconnect_~data, my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3831-L3836] -1 my_drv_disconnect_~data := my_drv_disconnect_#in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call my_drv_disconnect_~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] FCALL -1 call main_#t~mem42 := read~int({ base: main_~#data~1!base, offset: 40 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] FCALL -1 call main_#t~mem43 := read~int({ base: main_~#data~1!base, offset: 44 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ldv_assert_~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 #res := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= #t~ret40 && #t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 ~ret~0 := #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == ~ret~0 VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc ~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call ~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 ~data := #in~data; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: ~data!base, offset: ~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call #t~mem31 := read~int({ base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc #t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call #t~mem32 := read~int({ base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc #t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= #t~nondet33 && #t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 ~res~0 := #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != ~res~0) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: ~data!base, offset: 40 + ~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] -1 havoc #t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3824] -1 #res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= #t~ret41 && #t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 ~probe_ret~0 := #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 havoc #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == ~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3831-L3836] -1 ~data := #in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call ~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call #t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] JOIN 0 join #t~mem36 assign #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(#t~nondet37, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc #t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call #t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] JOIN 1 join #t~mem38 assign #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(#t~nondet39, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc #t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] -1 havoc ~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] FCALL -1 call #t~mem42 := read~int({ base: ~#data~1!base, offset: 40 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 havoc #t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] FCALL -1 call #t~mem43 := read~int({ base: ~#data~1!base, offset: 44 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 #res := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= #t~ret40 && #t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 ~ret~0 := #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == ~ret~0 VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc ~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call ~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 ~data := #in~data; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: ~data!base, offset: ~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call #t~mem31 := read~int({ base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc #t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call #t~mem32 := read~int({ base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc #t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= #t~nondet33 && #t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 ~res~0 := #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != ~res~0) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: ~data!base, offset: 40 + ~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] -1 havoc #t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3824] -1 #res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= #t~ret41 && #t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 ~probe_ret~0 := #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 havoc #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == ~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3831-L3836] -1 ~data := #in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call ~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call #t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] JOIN 0 join #t~mem36 assign #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(#t~nondet37, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc #t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call #t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] JOIN 1 join #t~mem38 assign #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(#t~nondet39, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc #t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] -1 havoc ~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] FCALL -1 call #t~mem42 := read~int({ base: ~#data~1!base, offset: 40 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 havoc #t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] FCALL -1 call #t~mem43 := read~int({ base: ~#data~1!base, offset: 44 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3774] -1 pthread_t t1,t2; VAL [t1={70:0}, t2={61:0}] [L3791] -1 struct device *my_dev; VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3839] -1 return 0; VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3847] -1 int ret = my_drv_init(); VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3848] COND TRUE -1 ret==0 VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3849] -1 int probe_ret; VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3850] -1 struct my_data data; VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3809] -1 data->shared.a = 0 VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3810] -1 data->shared.b = 0 VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3811] -1 data->shared.a VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3772] COND FALSE -1 !(!expression) VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3812] -1 data->shared.b VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3772] COND FALSE -1 !(!expression) VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3814] -1 int res = __VERIFIER_nondet_int(); VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3815] COND FALSE -1 !(\read(res)) VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3819] -1 my_dev = &data->dev VAL [my_dev={64:40}, t1={70:0}, t2={61:0}] [L3822] FCALL, FORK -1 pthread_create(&t1, ((void *)0), my_callback, ((void *)0)) VAL [arg={0:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3794] 0 struct my_data *data; VAL [arg={0:0}, arg={0:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3795] 0 const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3795] 0 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3799] 0 data->shared.a = 1 VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3800] 0 data->shared.b VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3823] FCALL, FORK -1 pthread_create(&t2, ((void *)0), my_callback, ((void *)0)) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3824] -1 return 0; VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3851] -1 probe_ret = my_drv_probe(&data) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3852] COND TRUE -1 probe_ret==0 VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3832] -1 void *status; VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3794] 1 struct my_data *data; VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3795] 1 const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3833] -1 \read(t1) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3795] 1 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3799] 1 data->shared.a = 1 VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3800] EXPR 1 data->shared.b VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3800] 1 data->shared.b = data->shared.b + 1 VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3802] 1 return 0; VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3800] 0 data->shared.b = data->shared.b + 1 VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3802] 0 return 0; VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3833] FCALL, JOIN 0 pthread_join(t1, &status) VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3834] -1 \read(t2) VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3834] FCALL, JOIN 1 pthread_join(t2, &status) VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3854] -1 data.shared.a VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3772] COND FALSE -1 !(!expression) VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3855] -1 data.shared.b VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3772] COND TRUE -1 !expression VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3772] -1 __VERIFIER_error() VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] ----- [2018-11-23 09:56:00,349 INFO L305 ceAbstractionStarter]: Did not count any witness invariants because Icfg is not BoogieIcfg [2018-11-23 09:56:00,350 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 09:56:00 BasicIcfg [2018-11-23 09:56:00,350 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 09:56:00,351 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 09:56:00,351 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 09:56:00,351 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 09:56:00,351 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 09:52:19" (3/4) ... [2018-11-23 09:56:00,353 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [287] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [202] L-1-->L3774: Formula: (= |v_#valid_1| (store |v_#valid_2| 0 0)) InVars {#valid=|v_#valid_2|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [276] L3774-->L3774-1: Formula: (and (= (select |v_#valid_4| |v_~#t1~0.base_1|) 0) (not (= |v_~#t1~0.base_1| 0)) (= 0 |v_~#t1~0.offset_1|) (= |v_#length_1| (store |v_#length_2| |v_~#t1~0.base_1| 4)) (= (store |v_#valid_4| |v_~#t1~0.base_1| 1) |v_#valid_3|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_4|} OutVars{~#t1~0.offset=|v_~#t1~0.offset_1|, #length=|v_#length_1|, ~#t1~0.base=|v_~#t1~0.base_1|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[~#t1~0.base, #valid, ~#t1~0.offset, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0] [?] -1 [272] L3774-1-->L3774-2: Formula: (= 0 (select (select |v_#memory_int_1| |v_~#t1~0.base_2|) |v_~#t1~0.offset_2|)) InVars {#memory_int=|v_#memory_int_1|, ~#t1~0.offset=|v_~#t1~0.offset_2|, ~#t1~0.base=|v_~#t1~0.base_2|} OutVars{#memory_int=|v_#memory_int_1|, ~#t1~0.offset=|v_~#t1~0.offset_2|, ~#t1~0.base=|v_~#t1~0.base_2|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0] [?] -1 [278] L3774-2-->L3774-3: Formula: (and (= 0 (select |v_#valid_6| |v_~#t2~0.base_1|)) (= (store |v_#length_4| |v_~#t2~0.base_1| 4) |v_#length_3|) (not (= 0 |v_~#t2~0.base_1|)) (= 0 |v_~#t2~0.offset_1|) (= |v_#valid_5| (store |v_#valid_6| |v_~#t2~0.base_1| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_6|} OutVars{#length=|v_#length_3|, ~#t2~0.base=|v_~#t2~0.base_1|, ~#t2~0.offset=|v_~#t2~0.offset_1|, #valid=|v_#valid_5|} AuxVars[] AssignedVars[~#t2~0.offset, #valid, #length, ~#t2~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0] [?] -1 [280] L3774-3-->L3774-4: Formula: (= (select (select |v_#memory_int_2| |v_~#t2~0.base_2|) |v_~#t2~0.offset_2|) 0) InVars {#memory_int=|v_#memory_int_2|, ~#t2~0.base=|v_~#t2~0.base_2|, ~#t2~0.offset=|v_~#t2~0.offset_2|} OutVars{#memory_int=|v_#memory_int_2|, ~#t2~0.base=|v_~#t2~0.base_2|, ~#t2~0.offset=|v_~#t2~0.offset_2|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0] [?] -1 [277] L3774-4-->L-1-1: Formula: (and (= v_~my_dev~0.base_1 0) (= v_~my_dev~0.offset_1 0)) InVars {} OutVars{~my_dev~0.offset=v_~my_dev~0.offset_1, ~my_dev~0.base=v_~my_dev~0.base_1} AuxVars[] AssignedVars[~my_dev~0.base, ~my_dev~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [308] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [307] L-1-2-->L3847: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~mem45=|v_ULTIMATE.start_main_#t~mem45_1|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_1|, ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_1, ULTIMATE.start_main_#t~mem44=|v_ULTIMATE.start_main_#t~mem44_1|, ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_1|, ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_1|, ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_1|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_1|, ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_1, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem45, ULTIMATE.start_main_#t~mem43, ULTIMATE.start_main_~ret~0, ULTIMATE.start_main_#t~mem44, ULTIMATE.start_main_#t~ret40, ULTIMATE.start_main_#t~mem42, ULTIMATE.start_main_#t~ret41, ULTIMATE.start_main_~#data~1.offset, ULTIMATE.start_main_~probe_ret~0, ULTIMATE.start_main_~#data~1.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [204] L3847-->L3839: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_init_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [195] L3839-->L3839-1: Formula: (= |v_ULTIMATE.start_my_drv_init_#res_2| 0) InVars {} OutVars{ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_init_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [318] L3839-1-->L3847-1: Formula: (= |v_ULTIMATE.start_main_#t~ret40_2| |v_ULTIMATE.start_my_drv_init_#res_3|) InVars {ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_3|} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_2|, ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret40] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [214] L3847-1-->L3847-2: Formula: (and (<= 0 (+ |v_ULTIMATE.start_main_#t~ret40_3| 2147483648)) (<= |v_ULTIMATE.start_main_#t~ret40_3| 2147483647)) InVars {ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_3|} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_3|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [209] L3847-2-->L3847-3: Formula: (= v_ULTIMATE.start_main_~ret~0_2 |v_ULTIMATE.start_main_#t~ret40_4|) InVars {ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_4|} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_4|, ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_~ret~0] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [191] L3847-3-->L3848: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret40] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [285] L3848-->L3849: Formula: (= v_ULTIMATE.start_main_~ret~0_3 0) InVars {ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_3} OutVars{ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_3} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [253] L3849-->L3850: Formula: true InVars {} OutVars{ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_~probe_ret~0] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [196] L3850-->L3850-1: Formula: (and (= 0 |v_ULTIMATE.start_main_~#data~1.offset_2|) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#data~1.base_2|) 0) (not (= |v_ULTIMATE.start_main_~#data~1.base_2| 0)) (= (store |v_#length_6| |v_ULTIMATE.start_main_~#data~1.base_2| 48) |v_#length_5|) (= (store |v_#valid_8| |v_ULTIMATE.start_main_~#data~1.base_2| 1) |v_#valid_7|)) InVars {#length=|v_#length_6|, #valid=|v_#valid_8|} OutVars{ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_2|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[#valid, ULTIMATE.start_main_~#data~1.offset, #length, ULTIMATE.start_main_~#data~1.base] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [314] L3850-1-->L3851: Formula: (and (= |v_ULTIMATE.start_my_drv_probe_#in~data.base_1| |v_ULTIMATE.start_main_~#data~1.base_3|) (= |v_ULTIMATE.start_my_drv_probe_#in~data.offset_1| |v_ULTIMATE.start_main_~#data~1.offset_3|)) InVars {ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_3|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_3|} OutVars{ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_1|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_3|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_3|, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#in~data.base, ULTIMATE.start_my_drv_probe_#in~data.offset] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [284] L3851-->L3851-1: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#res] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [283] L3851-1-->L3805: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_1|, ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_1, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_1, ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_1|, ULTIMATE.start_my_drv_probe_#t~nondet35=|v_ULTIMATE.start_my_drv_probe_#t~nondet35_1|, ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_1, ULTIMATE.start_my_drv_probe_#t~nondet34=|v_ULTIMATE.start_my_drv_probe_#t~nondet34_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem31, ULTIMATE.start_my_drv_probe_#t~mem32, ULTIMATE.start_my_drv_probe_~data.base, ULTIMATE.start_my_drv_probe_~data.offset, ULTIMATE.start_my_drv_probe_#t~nondet33, ULTIMATE.start_my_drv_probe_#t~nondet35, ULTIMATE.start_my_drv_probe_~res~0, ULTIMATE.start_my_drv_probe_#t~nondet34] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [252] L3805-->L3808: Formula: (and (= v_ULTIMATE.start_my_drv_probe_~data.offset_2 |v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|) (= v_ULTIMATE.start_my_drv_probe_~data.base_2 |v_ULTIMATE.start_my_drv_probe_#in~data.base_2|)) InVars {ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_2|, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|} OutVars{ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_2, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_2, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~data.base, ULTIMATE.start_my_drv_probe_~data.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [242] L3808-->L3809: Formula: (= |v_#pthreadsMutex_1| (store |v_#pthreadsMutex_2| v_ULTIMATE.start_my_drv_probe_~data.base_3 (store (select |v_#pthreadsMutex_2| v_ULTIMATE.start_my_drv_probe_~data.base_3) v_ULTIMATE.start_my_drv_probe_~data.offset_3 0))) InVars {#pthreadsMutex=|v_#pthreadsMutex_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_3, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_3} OutVars{#pthreadsMutex=|v_#pthreadsMutex_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_3, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_3} AuxVars[] AssignedVars[#pthreadsMutex] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [309] L3809-->L3809-1: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_4 40))) (and (= |v_#memory_$Pointer$.offset_1| (store |v_#memory_$Pointer$.offset_2| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#memory_$Pointer$.offset_2| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0 (select (select |v_#memory_$Pointer$.offset_1| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0)))) (= |v_#memory_int_3| (store |v_#memory_int_4| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#memory_int_4| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0 0))) (= (store |v_#memory_$Pointer$.base_2| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#memory_$Pointer$.base_2| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0 (select (select |v_#memory_$Pointer$.base_1| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0))) |v_#memory_$Pointer$.base_1|))) InVars {#memory_int=|v_#memory_int_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_4, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_2|} OutVars{#memory_int=|v_#memory_int_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_4, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_1|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [306] L3809-1-->L3810: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_5 44))) (and (= |v_#memory_$Pointer$.base_3| (store |v_#memory_$Pointer$.base_4| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_$Pointer$.base_4| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_3| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0)))) (= |v_#memory_int_5| (store |v_#memory_int_6| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_int_6| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 0))) (= |v_#memory_$Pointer$.offset_3| (store |v_#memory_$Pointer$.offset_4| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_$Pointer$.offset_4| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_3| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0)))))) InVars {#memory_int=|v_#memory_int_6|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_4|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_5, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_4|} OutVars{#memory_int=|v_#memory_int_5|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_3|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_5, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_3|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [267] L3810-->L3811: Formula: (= (select (select |v_#memory_int_7| v_ULTIMATE.start_my_drv_probe_~data.base_6) (+ v_ULTIMATE.start_my_drv_probe_~data.offset_6 40)) |v_ULTIMATE.start_my_drv_probe_#t~mem31_2|) InVars {#memory_int=|v_#memory_int_7|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_6, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_6} OutVars{#memory_int=|v_#memory_int_7|, ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_6, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_6} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem31] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [224] L3811-->L3811-1: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_1| (ite (= 0 |v_ULTIMATE.start_my_drv_probe_#t~mem31_3|) 1 0)) InVars {ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [219] L3811-1-->L3772: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [259] L3772-->L3772-1: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_2 |v_ULTIMATE.start_ldv_assert_#in~expression_2|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_2|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_2|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_2} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [262] L3772-1-->L3772-4: Formula: (not (= 0 v_ULTIMATE.start_ldv_assert_~expression_4)) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_4} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_4} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [239] L3772-4-->L3812: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem31] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [296] L3812-->L3812-1: Formula: (= (select (select |v_#memory_int_8| v_ULTIMATE.start_my_drv_probe_~data.base_7) (+ v_ULTIMATE.start_my_drv_probe_~data.offset_7 44)) |v_ULTIMATE.start_my_drv_probe_#t~mem32_2|) InVars {#memory_int=|v_#memory_int_8|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_7, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_7} OutVars{#memory_int=|v_#memory_int_8|, ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_7, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_7} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem32] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [299] L3812-1-->L3812-2: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_3| (ite (= 0 |v_ULTIMATE.start_my_drv_probe_#t~mem32_3|) 1 0)) InVars {ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_3|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [294] L3812-2-->L3772-5: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_5} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [241] L3772-5-->L3772-6: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_6 |v_ULTIMATE.start_ldv_assert_#in~expression_4|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_4|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_4|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_6} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [249] L3772-6-->L3772-9: Formula: (not (= 0 v_ULTIMATE.start_ldv_assert_~expression_8)) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_8} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_8} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [233] L3772-9-->L3814: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem32] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [211] L3814-->L3814-1: Formula: (and (<= 0 (+ |v_ULTIMATE.start_my_drv_probe_#t~nondet33_2| 2147483648)) (<= |v_ULTIMATE.start_my_drv_probe_#t~nondet33_2| 2147483647)) InVars {ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_2|} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_2|} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [210] L3814-1-->L3814-2: Formula: (= v_ULTIMATE.start_my_drv_probe_~res~0_2 |v_ULTIMATE.start_my_drv_probe_#t~nondet33_3|) InVars {ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_3|, ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_2} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~res~0] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [189] L3814-2-->L3815: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet33] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [289] L3815-->L3819: Formula: (= v_ULTIMATE.start_my_drv_probe_~res~0_4 0) InVars {ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_4} OutVars{ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_4} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [250] L3819-->L3822: Formula: (and (= v_~my_dev~0.base_2 v_ULTIMATE.start_my_drv_probe_~data.base_8) (= v_~my_dev~0.offset_2 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_8 40))) InVars {ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_8, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_8} OutVars{~my_dev~0.offset=v_~my_dev~0.offset_2, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_8, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_8, ~my_dev~0.base=v_~my_dev~0.base_2} AuxVars[] AssignedVars[~my_dev~0.base, ~my_dev~0.offset] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [222] L3822-->L3822-1: Formula: (and (= (store |v_#memory_int_10| |v_~#t1~0.base_3| (store (select |v_#memory_int_10| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| 0)) |v_#memory_int_9|) (= |v_#memory_$Pointer$.offset_5| (store |v_#memory_$Pointer$.offset_6| |v_~#t1~0.base_3| (store (select |v_#memory_$Pointer$.offset_6| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| (select (select |v_#memory_$Pointer$.offset_5| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3|)))) (= (store |v_#memory_$Pointer$.base_6| |v_~#t1~0.base_3| (store (select |v_#memory_$Pointer$.base_6| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| (select (select |v_#memory_$Pointer$.base_5| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3|))) |v_#memory_$Pointer$.base_5|)) InVars {#memory_int=|v_#memory_int_10|, ~#t1~0.offset=|v_~#t1~0.offset_3|, ~#t1~0.base=|v_~#t1~0.base_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_6|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_6|} OutVars{#memory_int=|v_#memory_int_9|, ~#t1~0.offset=|v_~#t1~0.offset_3|, ~#t1~0.base=|v_~#t1~0.base_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_5|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_5|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] FORK -1 [340] L3822-1-->my_callbackENTRY: Formula: (and (= 0 |v_Thread0_my_callback_#in~arg.offset_3|) (= 0 |v_Thread0_my_callback_#in~arg.base_3|) (= v_Thread0_my_callback_thidvar0_2 0)) InVars {} OutVars{Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_3|, Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_2, Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_my_callback_#in~arg.base, Thread0_my_callback_thidvar0, Thread0_my_callback_#in~arg.offset] VAL [Thread0_my_callback_thidvar0=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [320] my_callbackENTRY-->L3794: Formula: (and (= v_Thread0_my_callback_~arg.offset_1 |v_Thread0_my_callback_#in~arg.offset_1|) (= v_Thread0_my_callback_~arg.base_1 |v_Thread0_my_callback_#in~arg.base_1|)) InVars {Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_1|, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_1|} OutVars{Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_1|, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_1|, Thread0_my_callback_~arg.offset=v_Thread0_my_callback_~arg.offset_1, Thread0_my_callback_~arg.base=v_Thread0_my_callback_~arg.base_1} AuxVars[] AssignedVars[Thread0_my_callback_~arg.offset, Thread0_my_callback_~arg.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [321] L3794-->L3795: Formula: true InVars {} OutVars{Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_1, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_1} AuxVars[] AssignedVars[Thread0_my_callback_~data~0.offset, Thread0_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [226] L3822-2-->L3823: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet34=|v_ULTIMATE.start_my_drv_probe_#t~nondet34_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet34] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [322] L3795-->L3795-1: Formula: (and (= v_Thread0_my_callback_~__mptr~0.offset_1 v_~my_dev~0.offset_3) (= v_Thread0_my_callback_~__mptr~0.base_1 v_~my_dev~0.base_3)) InVars {~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3} OutVars{Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_1, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_1, ~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3} AuxVars[] AssignedVars[Thread0_my_callback_~__mptr~0.base, Thread0_my_callback_~__mptr~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [323] L3795-1-->L3799: Formula: (and (= v_Thread0_my_callback_~data~0.base_2 v_Thread0_my_callback_~__mptr~0.base_2) (= v_Thread0_my_callback_~data~0.offset_2 (+ v_Thread0_my_callback_~__mptr~0.offset_2 (- 40)))) InVars {Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_2, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_2} OutVars{Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_2, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_2, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_2, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_2} AuxVars[] AssignedVars[Thread0_my_callback_~data~0.offset, Thread0_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [324] L3799-->L3799-1: Formula: (let ((.cse0 (+ v_Thread0_my_callback_~data~0.offset_3 40))) (and (= |v_#memory_$Pointer$.base_17| (store |v_#memory_$Pointer$.base_18| v_Thread0_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.base_18| v_Thread0_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.base_17| v_Thread0_my_callback_~data~0.base_3) .cse0)))) (= (store |v_#memory_$Pointer$.offset_18| v_Thread0_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.offset_18| v_Thread0_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.offset_17| v_Thread0_my_callback_~data~0.base_3) .cse0))) |v_#memory_$Pointer$.offset_17|) (= (store |v_#memory_int_28| v_Thread0_my_callback_~data~0.base_3 (store (select |v_#memory_int_28| v_Thread0_my_callback_~data~0.base_3) .cse0 1)) |v_#memory_int_27|))) InVars {#memory_int=|v_#memory_int_28|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_18|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_18|} OutVars{#memory_int=|v_#memory_int_27|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_17|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_17|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [325] L3799-1-->L3800: Formula: (= |v_Thread0_my_callback_#t~mem30_1| (select (select |v_#memory_int_29| v_Thread0_my_callback_~data~0.base_4) (+ v_Thread0_my_callback_~data~0.offset_4 44))) InVars {#memory_int=|v_#memory_int_29|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_4, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_4} OutVars{#memory_int=|v_#memory_int_29|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_4, Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_1|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_4} AuxVars[] AssignedVars[Thread0_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [302] L3823-->L3823-1: Formula: (and (= (store |v_#memory_$Pointer$.base_8| |v_~#t2~0.base_3| (store (select |v_#memory_$Pointer$.base_8| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| (select (select |v_#memory_$Pointer$.base_7| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3|))) |v_#memory_$Pointer$.base_7|) (= (store |v_#memory_$Pointer$.offset_8| |v_~#t2~0.base_3| (store (select |v_#memory_$Pointer$.offset_8| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| (select (select |v_#memory_$Pointer$.offset_7| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3|))) |v_#memory_$Pointer$.offset_7|) (= |v_#memory_int_11| (store |v_#memory_int_12| |v_~#t2~0.base_3| (store (select |v_#memory_int_12| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| 1)))) InVars {#memory_int=|v_#memory_int_12|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_8|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_8|, ~#t2~0.base=|v_~#t2~0.base_3|, ~#t2~0.offset=|v_~#t2~0.offset_3|} OutVars{#memory_int=|v_#memory_int_11|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_7|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_7|, ~#t2~0.base=|v_~#t2~0.base_3|, ~#t2~0.offset=|v_~#t2~0.offset_3|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] FORK -1 [341] L3823-1-->my_callbackENTRY: Formula: (and (= |v_Thread1_my_callback_#in~arg.base_3| 0) (= 0 |v_Thread1_my_callback_#in~arg.offset_3|) (= v_Thread1_my_callback_thidvar0_2 1)) InVars {} OutVars{Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_2, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_3|, Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_my_callback_thidvar0, Thread1_my_callback_#in~arg.base, Thread1_my_callback_#in~arg.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [292] L3823-2-->L3824: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet35=|v_ULTIMATE.start_my_drv_probe_#t~nondet35_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet35] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [264] L3824-->L3828: Formula: (= |v_ULTIMATE.start_my_drv_probe_#res_2| 0) InVars {} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#res] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [330] my_callbackENTRY-->L3794: Formula: (and (= v_Thread1_my_callback_~arg.offset_1 |v_Thread1_my_callback_#in~arg.offset_1|) (= v_Thread1_my_callback_~arg.base_1 |v_Thread1_my_callback_#in~arg.base_1|)) InVars {Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_1|, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_1|} OutVars{Thread1_my_callback_~arg.base=v_Thread1_my_callback_~arg.base_1, Thread1_my_callback_~arg.offset=v_Thread1_my_callback_~arg.offset_1, Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_1|, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_1|} AuxVars[] AssignedVars[Thread1_my_callback_~arg.base, Thread1_my_callback_~arg.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [315] L3828-->L3851-2: Formula: (= |v_ULTIMATE.start_main_#t~ret41_2| |v_ULTIMATE.start_my_drv_probe_#res_4|) InVars {ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_4|} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_4|, ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret41] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [275] L3851-2-->L3851-3: Formula: (and (<= |v_ULTIMATE.start_main_#t~ret41_3| 2147483647) (<= 0 (+ |v_ULTIMATE.start_main_#t~ret41_3| 2147483648))) InVars {ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_3|} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_3|} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [273] L3851-3-->L3851-4: Formula: (= v_ULTIMATE.start_main_~probe_ret~0_3 |v_ULTIMATE.start_main_#t~ret41_4|) InVars {ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_4|} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_4|, ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_~probe_ret~0] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [274] L3851-4-->L3852: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret41] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [246] L3852-->L3853: Formula: (= v_ULTIMATE.start_main_~probe_ret~0_4 0) InVars {ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_4} OutVars{ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_4} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [304] L3853-->L3853-1: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#in~data.base_1| |v_ULTIMATE.start_main_~#data~1.base_4|) (= |v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_1| |v_ULTIMATE.start_main_~#data~1.offset_4|)) InVars {ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_4|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_4|} OutVars{ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_4|, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_1|, ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_1|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#in~data.offset, ULTIMATE.start_my_drv_disconnect_#in~data.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [310] L3853-1-->L3831: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_1|, ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_1, ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_1|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_1|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_1, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_1|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38, ULTIMATE.start_my_drv_disconnect_~data.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~data.base, ULTIMATE.start_my_drv_disconnect_~#status~0.base, ULTIMATE.start_my_drv_disconnect_#t~mem36, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [305] L3831-->L3832: Formula: (and (= v_ULTIMATE.start_my_drv_disconnect_~data.base_2 |v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|) (= v_ULTIMATE.start_my_drv_disconnect_~data.offset_2 |v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|)) InVars {ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|} OutVars{ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_2, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_2, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|, ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~data.offset, ULTIMATE.start_my_drv_disconnect_~data.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [266] L3832-->L3832-1: Formula: (and (= |v_#length_7| (store |v_#length_8| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2| 4)) (= (store |v_#valid_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2| 1) |v_#valid_9|) (= 0 (select |v_#valid_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|)) (= |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|))) InVars {#length=|v_#length_8|, #valid=|v_#valid_10|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_2|, #length=|v_#length_7|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.base, #valid, #length] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [331] L3794-->L3795: Formula: true InVars {} OutVars{Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_1, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_1} AuxVars[] AssignedVars[Thread1_my_callback_~data~0.offset, Thread1_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [332] L3795-->L3795-1: Formula: (and (= v_Thread1_my_callback_~__mptr~0.offset_1 v_~my_dev~0.offset_3) (= v_Thread1_my_callback_~__mptr~0.base_1 v_~my_dev~0.base_3)) InVars {~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3} OutVars{~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3, Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_1, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_1} AuxVars[] AssignedVars[Thread1_my_callback_~__mptr~0.base, Thread1_my_callback_~__mptr~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [268] L3832-1-->L3833: Formula: (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem36_2| (select (select |v_#memory_int_13| |v_~#t1~0.base_4|) |v_~#t1~0.offset_4|)) InVars {#memory_int=|v_#memory_int_13|, ~#t1~0.offset=|v_~#t1~0.offset_4|, ~#t1~0.base=|v_~#t1~0.base_4|} OutVars{#memory_int=|v_#memory_int_13|, ~#t1~0.offset=|v_~#t1~0.offset_4|, ~#t1~0.base=|v_~#t1~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem36] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [333] L3795-1-->L3799: Formula: (and (= v_Thread1_my_callback_~data~0.base_2 v_Thread1_my_callback_~__mptr~0.base_2) (= v_Thread1_my_callback_~data~0.offset_2 (+ v_Thread1_my_callback_~__mptr~0.offset_2 (- 40)))) InVars {Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_2, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_2} OutVars{Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_2, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_2, Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_2, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_2} AuxVars[] AssignedVars[Thread1_my_callback_~data~0.offset, Thread1_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [334] L3799-->L3799-1: Formula: (let ((.cse0 (+ v_Thread1_my_callback_~data~0.offset_3 40))) (and (= |v_#memory_$Pointer$.base_17| (store |v_#memory_$Pointer$.base_18| v_Thread1_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.base_18| v_Thread1_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.base_17| v_Thread1_my_callback_~data~0.base_3) .cse0)))) (= (store |v_#memory_$Pointer$.offset_18| v_Thread1_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.offset_18| v_Thread1_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.offset_17| v_Thread1_my_callback_~data~0.base_3) .cse0))) |v_#memory_$Pointer$.offset_17|) (= (store |v_#memory_int_28| v_Thread1_my_callback_~data~0.base_3 (store (select |v_#memory_int_28| v_Thread1_my_callback_~data~0.base_3) .cse0 1)) |v_#memory_int_27|))) InVars {#memory_int=|v_#memory_int_28|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_18|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_18|} OutVars{#memory_int=|v_#memory_int_27|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_17|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_17|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [335] L3799-1-->L3800: Formula: (= |v_Thread1_my_callback_#t~mem30_1| (select (select |v_#memory_int_29| v_Thread1_my_callback_~data~0.base_4) (+ v_Thread1_my_callback_~data~0.offset_4 44))) InVars {#memory_int=|v_#memory_int_29|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_4, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_4} OutVars{#memory_int=|v_#memory_int_29|, Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_1|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_4, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_4} AuxVars[] AssignedVars[Thread1_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [336] L3800-->L3800-1: Formula: (let ((.cse0 (+ v_Thread1_my_callback_~data~0.offset_5 44))) (and (= |v_#memory_$Pointer$.offset_19| (store |v_#memory_$Pointer$.offset_20| v_Thread1_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.offset_20| v_Thread1_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_19| v_Thread1_my_callback_~data~0.base_5) .cse0)))) (= |v_#memory_$Pointer$.base_19| (store |v_#memory_$Pointer$.base_20| v_Thread1_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.base_20| v_Thread1_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_19| v_Thread1_my_callback_~data~0.base_5) .cse0)))) (= (store |v_#memory_int_31| v_Thread1_my_callback_~data~0.base_5 (store (select |v_#memory_int_31| v_Thread1_my_callback_~data~0.base_5) .cse0 (+ |v_Thread1_my_callback_#t~mem30_2| 1))) |v_#memory_int_30|))) InVars {#memory_$Pointer$.base=|v_#memory_$Pointer$.base_20|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_31|, Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_2|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_20|} OutVars{#memory_$Pointer$.base=|v_#memory_$Pointer$.base_19|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_30|, Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_2|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_19|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [337] L3800-1-->L3802: Formula: true InVars {} OutVars{Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_3|} AuxVars[] AssignedVars[Thread1_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [338] L3802-->my_callbackFINAL: Formula: (and (= |v_Thread1_my_callback_#res.offset_1| 0) (= |v_Thread1_my_callback_#res.base_1| 0)) InVars {} OutVars{Thread1_my_callback_#res.offset=|v_Thread1_my_callback_#res.offset_1|, Thread1_my_callback_#res.base=|v_Thread1_my_callback_#res.base_1|} AuxVars[] AssignedVars[Thread1_my_callback_#res.offset, Thread1_my_callback_#res.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 [339] my_callbackFINAL-->my_callbackEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [326] L3800-->L3800-1: Formula: (let ((.cse0 (+ v_Thread0_my_callback_~data~0.offset_5 44))) (and (= |v_#memory_$Pointer$.offset_19| (store |v_#memory_$Pointer$.offset_20| v_Thread0_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.offset_20| v_Thread0_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_19| v_Thread0_my_callback_~data~0.base_5) .cse0)))) (= |v_#memory_$Pointer$.base_19| (store |v_#memory_$Pointer$.base_20| v_Thread0_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.base_20| v_Thread0_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_19| v_Thread0_my_callback_~data~0.base_5) .cse0)))) (= (store |v_#memory_int_31| v_Thread0_my_callback_~data~0.base_5 (store (select |v_#memory_int_31| v_Thread0_my_callback_~data~0.base_5) .cse0 (+ |v_Thread0_my_callback_#t~mem30_2| 1))) |v_#memory_int_30|))) InVars {#memory_$Pointer$.base=|v_#memory_$Pointer$.base_20|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_31|, Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_2|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_20|} OutVars{#memory_$Pointer$.base=|v_#memory_$Pointer$.base_19|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_30|, Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_2|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_19|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [327] L3800-1-->L3802: Formula: true InVars {} OutVars{Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_3|} AuxVars[] AssignedVars[Thread0_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [328] L3802-->my_callbackFINAL: Formula: (and (= |v_Thread0_my_callback_#res.offset_1| 0) (= |v_Thread0_my_callback_#res.base_1| 0)) InVars {} OutVars{Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_1|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_1|} AuxVars[] AssignedVars[Thread0_my_callback_#res.base, Thread0_my_callback_#res.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 [329] my_callbackFINAL-->my_callbackEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] JOIN 0 [342] my_callbackEXIT-->L3833-1: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem36_5| v_Thread0_my_callback_thidvar0_4) (= |v_Thread0_my_callback_#res.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_5|) (= |v_Thread0_my_callback_#res.base_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_5|)) InVars {Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_4, Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_3|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_5|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_3|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_5|, Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_4, Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_3|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_5|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_5|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [217] L3833-1-->L3833-2: Formula: (and (= |v_#memory_$Pointer$.offset_9| (store |v_#memory_$Pointer$.offset_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_$Pointer$.offset_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_2|))) (= (store |v_#memory_$Pointer$.base_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_$Pointer$.base_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_2|)) |v_#memory_$Pointer$.base_9|) (= (store |v_#memory_int_15| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_int_15| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| (select (select |v_#memory_int_14| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|))) |v_#memory_int_14|)) InVars {ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_2|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_10|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_2|, #memory_int=|v_#memory_int_15|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_10|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_2|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_9|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_2|, #memory_int=|v_#memory_int_14|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_9|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [220] L3833-2-->L3833-3: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem36] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [229] L3833-3-->L3834: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [303] L3834-->L3834-1: Formula: (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem38_2| (select (select |v_#memory_int_16| |v_~#t2~0.base_4|) |v_~#t2~0.offset_4|)) InVars {#memory_int=|v_#memory_int_16|, ~#t2~0.base=|v_~#t2~0.base_4|, ~#t2~0.offset=|v_~#t2~0.offset_4|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_2|, #memory_int=|v_#memory_int_16|, ~#t2~0.base=|v_~#t2~0.base_4|, ~#t2~0.offset=|v_~#t2~0.offset_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] JOIN 1 [345] my_callbackEXIT-->L3834-2: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_7| |v_Thread1_my_callback_#res.offset_5|) (= |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_7| |v_Thread1_my_callback_#res.base_5|) (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem38_7| v_Thread1_my_callback_thidvar0_6)) InVars {ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_7|, Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_6, Thread1_my_callback_#res.offset=|v_Thread1_my_callback_#res.offset_5|, Thread1_my_callback_#res.base=|v_Thread1_my_callback_#res.base_5|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_7|, Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_6, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_7|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_7|, Thread1_my_callback_#res.offset=|v_Thread1_my_callback_#res.offset_5|, Thread1_my_callback_#res.base=|v_Thread1_my_callback_#res.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [293] L3834-2-->L3834-3: Formula: (and (= (store |v_#memory_$Pointer$.base_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4| (store (select |v_#memory_$Pointer$.base_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_2|)) |v_#memory_$Pointer$.base_11|) (= |v_#memory_$Pointer$.offset_11| (store |v_#memory_$Pointer$.offset_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4| (store (select |v_#memory_$Pointer$.offset_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_2|))) (= (store |v_#memory_int_18| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4| (store (select |v_#memory_int_18| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4| (select (select |v_#memory_int_17| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4|))) |v_#memory_int_17|)) InVars {ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_12|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_2|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_2|, #memory_int=|v_#memory_int_18|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_12|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_11|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_2|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_2|, #memory_int=|v_#memory_int_17|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_11|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [295] L3834-3-->L3834-4: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [300] L3834-4-->L3832-2: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [271] L3832-2-->L3832-3: Formula: (= (store |v_#valid_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_5| 0) |v_#valid_11|) InVars {ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_5|, #valid=|v_#valid_12|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_5|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [270] L3832-3-->L3831-1: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_6|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_6|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [311] L3831-1-->L3854: Formula: (= (select (select |v_#memory_int_19| |v_ULTIMATE.start_main_~#data~1.base_5|) (+ |v_ULTIMATE.start_main_~#data~1.offset_5| 40)) |v_ULTIMATE.start_main_#t~mem42_2|) InVars {#memory_int=|v_#memory_int_19|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_5|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_5|} OutVars{#memory_int=|v_#memory_int_19|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_5|, ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_2|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem42] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [269] L3854-->L3854-1: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_5| (ite (= |v_ULTIMATE.start_main_#t~mem42_3| 1) 1 0)) InVars {ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_3|} OutVars{ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [265] L3854-1-->L3772-10: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_9} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [232] L3772-10-->L3772-11: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_10 |v_ULTIMATE.start_ldv_assert_#in~expression_6|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_6|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_6|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_10} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [238] L3772-11-->L3772-14: Formula: (not (= v_ULTIMATE.start_ldv_assert_~expression_12 0)) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_12} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_12} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [223] L3772-14-->L3855: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem42] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [236] L3855-->L3855-1: Formula: (= |v_ULTIMATE.start_main_#t~mem43_2| (select (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#data~1.base_6|) (+ |v_ULTIMATE.start_main_~#data~1.offset_6| 44))) InVars {#memory_int=|v_#memory_int_20|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_6|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_6|} OutVars{#memory_int=|v_#memory_int_20|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_2|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_6|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem43] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [225] L3855-1-->L3855-2: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_7| (ite (= |v_ULTIMATE.start_main_#t~mem43_3| 2) 1 0)) InVars {ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_3|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_7|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_3|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [215] L3855-2-->L3772-15: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_13} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [218] L3772-15-->L3772-16: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_14 |v_ULTIMATE.start_ldv_assert_#in~expression_8|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_8|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_8|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_14} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [227] L3772-16-->L3772-17: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_15 0) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_15} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_15} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 [230] L3772-17-->ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=64, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=64, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=64, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=64, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 SUMMARY for call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); srcloc: L3774 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3774-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0] [?] -1 SUMMARY for call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); srcloc: L3774-2 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3774-3 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_init_#res := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_#t~ret40 := my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_~ret~0 := main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume 0 == main_~ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_~probe_ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); srcloc: L3850 VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#res; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3809 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3809-1 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3810 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3812 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem32; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 != my_drv_probe_~res~0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3822 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] FORK -1 fork 0 my_callback(0, 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet34; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3823 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] FORK -1 fork 1 my_callback(0, 0); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet35; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 my_drv_probe_#res := 0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 main_#t~ret41 := my_drv_probe_#res; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 main_~probe_ret~0 := main_#t~ret41; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc main_#t~ret41; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume 0 == main_~probe_ret~0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); srcloc: L3832 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3832-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 assume true; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 assume true; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3833-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3834 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3834-2 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem38; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); srcloc: L3832-2 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); srcloc: L3831-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume !(0 == ldv_assert_~expression); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc main_#t~mem42; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); srcloc: L3855 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume 0 == ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume !false; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 SUMMARY for call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); srcloc: L3774 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3774-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0] [?] -1 SUMMARY for call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); srcloc: L3774-2 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3774-3 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_init_#res := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_#t~ret40 := my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_~ret~0 := main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume 0 == main_~ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_~probe_ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); srcloc: L3850 VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#res; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3809 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3809-1 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3810 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3812 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem32; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 != my_drv_probe_~res~0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3822 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] FORK -1 fork 0 my_callback(0, 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet34; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3823 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] FORK -1 fork 1 my_callback(0, 0); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet35; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 my_drv_probe_#res := 0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 main_#t~ret41 := my_drv_probe_#res; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 main_~probe_ret~0 := main_#t~ret41; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc main_#t~ret41; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume 0 == main_~probe_ret~0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); srcloc: L3832 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3832-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 1 assume true; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] 0 assume true; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3833-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3834 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3834-2 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem38; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); srcloc: L3832-2 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); srcloc: L3831-1 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume !(0 == ldv_assert_~expression); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc main_#t~mem42; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); srcloc: L3855 VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume 0 == ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 assume !false; VAL [my_callback_~__mptr~0.base=64, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=64, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=64, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=64, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=64, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=64, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=64, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=70, |~#t1~0.offset|=0, |~#t2~0.base|=61, |~#t2~0.offset|=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L3774] -1 call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0] [L3774] -1 call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0] [L3774] -1 call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0] [L3774] -1 call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0] [L3791] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL.base=0, #NULL.offset=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3848-L3862] -1 assume 0 == main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3850] -1 call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3805-L3829] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3808] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3809] -1 call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3810] -1 call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3815-L3816] -1 assume !(0 != my_drv_probe_~res~0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3819] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3822] -1 call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3822] FORK -1 fork 0 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3794] 0 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3799] 0 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 0 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3823] -1 call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3823] FORK -1 fork 1 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3852-L3856] -1 assume 0 == main_~probe_ret~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3853] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3831-L3836] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3832] -1 call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3794] 1 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3799] 1 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 1 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 1 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3802] 1 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 1 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 0 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3802] 0 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 0 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3832] -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3855] -1 call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 assume 0 == ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 assert false; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L3774] -1 call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0] [L3774] -1 call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0] [L3774] -1 call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0] [L3774] -1 call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0] [L3791] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL.base=0, #NULL.offset=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3848-L3862] -1 assume 0 == main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3850] -1 call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3805-L3829] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3808] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3809] -1 call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3810] -1 call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3815-L3816] -1 assume !(0 != my_drv_probe_~res~0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3819] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3822] -1 call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3822] FORK -1 fork 0 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3794] 0 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3799] 0 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 0 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3823] -1 call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3823] FORK -1 fork 1 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3852-L3856] -1 assume 0 == main_~probe_ret~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3853] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3831-L3836] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3832] -1 call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3794] 1 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3795] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3799] 1 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 1 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 1 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3802] 1 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 1 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 0 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3802] 0 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3793-L3803] 0 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3832] -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3855] -1 call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 assume 0 == ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [L3772] -1 assert false; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=64, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=64, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=64, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=64, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=64, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=70, ~#t1~0.offset=0, ~#t2~0.base=61, ~#t2~0.offset=0, ~__mptr~0.base=64, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=64, ~data~0.offset=0, ~my_dev~0.base=64, ~my_dev~0.offset=40] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1, main_~ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL!base=0, #NULL!offset=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == main_~ret~0 VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call main_~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 my_drv_probe_#in~data := main_~#data~1; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data, my_drv_probe_~res~0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 my_drv_probe_~data := my_drv_probe_#in~data; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: my_drv_probe_~data!base, offset: my_drv_probe_~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call my_drv_probe_#t~mem31 := read~int({ base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call my_drv_probe_#t~mem32 := read~int({ base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != my_drv_probe_~res~0) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == main_~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3853] -1 my_drv_disconnect_#in~data := main_~#data~1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39, my_drv_disconnect_~data, my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3831-L3836] -1 my_drv_disconnect_~data := my_drv_disconnect_#in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call my_drv_disconnect_~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] FCALL -1 call main_#t~mem42 := read~int({ base: main_~#data~1!base, offset: 40 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] FCALL -1 call main_#t~mem43 := read~int({ base: main_~#data~1!base, offset: 44 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ldv_assert_~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1, main_~ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL!base=0, #NULL!offset=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == main_~ret~0 VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call main_~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 my_drv_probe_#in~data := main_~#data~1; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data, my_drv_probe_~res~0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 my_drv_probe_~data := my_drv_probe_#in~data; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: my_drv_probe_~data!base, offset: my_drv_probe_~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call my_drv_probe_#t~mem31 := read~int({ base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call my_drv_probe_#t~mem32 := read~int({ base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != my_drv_probe_~res~0) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == main_~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3853] -1 my_drv_disconnect_#in~data := main_~#data~1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39, my_drv_disconnect_~data, my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3831-L3836] -1 my_drv_disconnect_~data := my_drv_disconnect_#in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call my_drv_disconnect_~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] FCALL -1 call main_#t~mem42 := read~int({ base: main_~#data~1!base, offset: 40 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] FCALL -1 call main_#t~mem43 := read~int({ base: main_~#data~1!base, offset: 44 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ldv_assert_~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=64, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=64, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=64, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=64, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=64, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 #res := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= #t~ret40 && #t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 ~ret~0 := #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == ~ret~0 VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc ~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call ~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 ~data := #in~data; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: ~data!base, offset: ~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call #t~mem31 := read~int({ base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc #t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call #t~mem32 := read~int({ base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc #t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= #t~nondet33 && #t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 ~res~0 := #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != ~res~0) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: ~data!base, offset: 40 + ~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] -1 havoc #t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3824] -1 #res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= #t~ret41 && #t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 ~probe_ret~0 := #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 havoc #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == ~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3831-L3836] -1 ~data := #in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call ~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call #t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] JOIN 0 join #t~mem36 assign #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(#t~nondet37, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc #t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call #t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] JOIN 1 join #t~mem38 assign #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(#t~nondet39, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc #t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] -1 havoc ~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] FCALL -1 call #t~mem42 := read~int({ base: ~#data~1!base, offset: 40 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 havoc #t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] FCALL -1 call #t~mem43 := read~int({ base: ~#data~1!base, offset: 44 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 #res := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= #t~ret40 && #t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 ~ret~0 := #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == ~ret~0 VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc ~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call ~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 ~data := #in~data; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: ~data!base, offset: ~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call #t~mem31 := read~int({ base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc #t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call #t~mem32 := read~int({ base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc #t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= #t~nondet33 && #t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 ~res~0 := #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != ~res~0) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: ~data!base, offset: 40 + ~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3822] -1 havoc #t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3823] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3824] -1 #res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= #t~ret41 && #t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 ~probe_ret~0 := #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3851] -1 havoc #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == ~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3831-L3836] -1 ~data := #in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call ~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call #t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] JOIN 0 join #t~mem36 assign #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(#t~nondet37, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc #t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3833] -1 havoc #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call #t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] JOIN 1 join #t~mem38 assign #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(#t~nondet39, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc #t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3834] -1 havoc #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3832] -1 havoc ~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] FCALL -1 call #t~mem42 := read~int({ base: ~#data~1!base, offset: 40 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3854] -1 havoc #t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3855] FCALL -1 call #t~mem43 := read~int({ base: ~#data~1!base, offset: 44 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=70, ~#t1~0!offset=0, ~#t2~0!base=61, ~#t2~0!offset=0, ~__mptr~0!base=64, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=64, ~data~0!offset=0, ~my_dev~0!base=64, ~my_dev~0!offset=40] [L3774] -1 pthread_t t1,t2; VAL [t1={70:0}, t2={61:0}] [L3791] -1 struct device *my_dev; VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3839] -1 return 0; VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3847] -1 int ret = my_drv_init(); VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3848] COND TRUE -1 ret==0 VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3849] -1 int probe_ret; VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3850] -1 struct my_data data; VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3809] -1 data->shared.a = 0 VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3810] -1 data->shared.b = 0 VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3811] -1 data->shared.a VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3772] COND FALSE -1 !(!expression) VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3812] -1 data->shared.b VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3772] COND FALSE -1 !(!expression) VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3814] -1 int res = __VERIFIER_nondet_int(); VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3815] COND FALSE -1 !(\read(res)) VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3819] -1 my_dev = &data->dev VAL [my_dev={64:40}, t1={70:0}, t2={61:0}] [L3822] FCALL, FORK -1 pthread_create(&t1, ((void *)0), my_callback, ((void *)0)) VAL [arg={0:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3794] 0 struct my_data *data; VAL [arg={0:0}, arg={0:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3795] 0 const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3795] 0 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3799] 0 data->shared.a = 1 VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3800] 0 data->shared.b VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3823] FCALL, FORK -1 pthread_create(&t2, ((void *)0), my_callback, ((void *)0)) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3824] -1 return 0; VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3851] -1 probe_ret = my_drv_probe(&data) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3852] COND TRUE -1 probe_ret==0 VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3832] -1 void *status; VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3794] 1 struct my_data *data; VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3795] 1 const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3833] -1 \read(t1) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3795] 1 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3799] 1 data->shared.a = 1 VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3800] EXPR 1 data->shared.b VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3800] 1 data->shared.b = data->shared.b + 1 VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3802] 1 return 0; VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3800] 0 data->shared.b = data->shared.b + 1 VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3802] 0 return 0; VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3833] FCALL, JOIN 0 pthread_join(t1, &status) VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3834] -1 \read(t2) VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3834] FCALL, JOIN 1 pthread_join(t2, &status) VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3854] -1 data.shared.a VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3772] COND FALSE -1 !(!expression) VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3855] -1 data.shared.b VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3772] COND TRUE -1 !expression VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3772] -1 __VERIFIER_error() VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] ----- [2018-11-23 09:56:04,203 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_df74cd3e-d09c-4a29-9b26-2cf3848f56b2/bin-2019/uautomizer/witness.graphml [2018-11-23 09:56:04,203 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 09:56:04,204 INFO L168 Benchmark]: Toolchain (without parser) took 226374.59 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 179.8 MB). Free memory was 956.6 MB in the beginning and 838.8 MB in the end (delta: 117.8 MB). Peak memory consumption was 297.6 MB. Max. memory is 11.5 GB. [2018-11-23 09:56:04,204 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 09:56:04,204 INFO L168 Benchmark]: CACSL2BoogieTranslator took 913.95 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 146.8 MB). Free memory was 956.6 MB in the beginning and 1.0 GB in the end (delta: -60.5 MB). Peak memory consumption was 101.2 MB. Max. memory is 11.5 GB. [2018-11-23 09:56:04,263 INFO L168 Benchmark]: Boogie Procedure Inliner took 48.99 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. [2018-11-23 09:56:04,263 INFO L168 Benchmark]: Boogie Preprocessor took 30.76 ms. Allocated memory is still 1.2 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 09:56:04,263 INFO L168 Benchmark]: RCFGBuilder took 574.88 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 967.2 MB in the end (delta: 46.6 MB). Peak memory consumption was 46.6 MB. Max. memory is 11.5 GB. [2018-11-23 09:56:04,263 INFO L168 Benchmark]: TraceAbstraction took 220949.72 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 33.0 MB). Free memory was 967.2 MB in the beginning and 927.3 MB in the end (delta: 39.9 MB). Peak memory consumption was 72.9 MB. Max. memory is 11.5 GB. [2018-11-23 09:56:04,263 INFO L168 Benchmark]: Witness Printer took 3852.74 ms. Allocated memory is still 1.2 GB. Free memory was 920.0 MB in the beginning and 838.8 MB in the end (delta: 81.2 MB). Peak memory consumption was 81.2 MB. Max. memory is 11.5 GB. [2018-11-23 09:56:04,264 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 913.95 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 146.8 MB). Free memory was 956.6 MB in the beginning and 1.0 GB in the end (delta: -60.5 MB). Peak memory consumption was 101.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 48.99 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 30.76 ms. Allocated memory is still 1.2 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 574.88 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 967.2 MB in the end (delta: 46.6 MB). Peak memory consumption was 46.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 220949.72 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 33.0 MB). Free memory was 967.2 MB in the beginning and 927.3 MB in the end (delta: 39.9 MB). Peak memory consumption was 72.9 MB. Max. memory is 11.5 GB. * Witness Printer took 3852.74 ms. Allocated memory is still 1.2 GB. Free memory was 920.0 MB in the beginning and 838.8 MB in the end (delta: 81.2 MB). Peak memory consumption was 81.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 3772]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L3774] -1 pthread_t t1,t2; VAL [t1={70:0}, t2={61:0}] [L3791] -1 struct device *my_dev; VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3839] -1 return 0; VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3847] -1 int ret = my_drv_init(); VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3848] COND TRUE -1 ret==0 VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3849] -1 int probe_ret; VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3850] -1 struct my_data data; VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3809] -1 data->shared.a = 0 VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3810] -1 data->shared.b = 0 VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3811] -1 data->shared.a VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3772] COND FALSE -1 !(!expression) VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3812] -1 data->shared.b VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3772] COND FALSE -1 !(!expression) VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3814] -1 int res = __VERIFIER_nondet_int(); VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3815] COND FALSE -1 !(\read(res)) VAL [my_dev={0:0}, t1={70:0}, t2={61:0}] [L3819] -1 my_dev = &data->dev VAL [my_dev={64:40}, t1={70:0}, t2={61:0}] [L3822] FCALL, FORK -1 pthread_create(&t1, ((void *)0), my_callback, ((void *)0)) VAL [arg={0:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3794] 0 struct my_data *data; VAL [arg={0:0}, arg={0:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3795] 0 const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3795] 0 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3799] 0 data->shared.a = 1 VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3800] 0 data->shared.b VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3823] FCALL, FORK -1 pthread_create(&t2, ((void *)0), my_callback, ((void *)0)) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3824] -1 return 0; VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3851] -1 probe_ret = my_drv_probe(&data) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3852] COND TRUE -1 probe_ret==0 VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3832] -1 void *status; VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3794] 1 struct my_data *data; VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3795] 1 const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3833] -1 \read(t1) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3795] 1 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3799] 1 data->shared.a = 1 VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3800] EXPR 1 data->shared.b VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3800] 1 data->shared.b = data->shared.b + 1 VAL [__mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3802] 1 return 0; VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3800] 0 data->shared.b = data->shared.b + 1 VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, data->shared.b=0, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3802] 0 return 0; VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3833] FCALL, JOIN 0 pthread_join(t1, &status) VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3834] -1 \read(t2) VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3834] FCALL, JOIN 1 pthread_join(t2, &status) VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3854] -1 data.shared.a VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3772] COND FALSE -1 !(!expression) VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3855] -1 data.shared.b VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3772] COND TRUE -1 !expression VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] [L3772] -1 __VERIFIER_error() VAL [\result={0:0}, __mptr={64:40}, arg={0:0}, arg={0:0}, data={64:0}, my_dev={64:40}, t1={70:0}, t2={61:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 148 locations, 6 error locations. UNSAFE Result, 220.8s OverallTime, 48 OverallIterations, 1 TraceHistogramMax, 171.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 8471 SDtfs, 38556 SDslu, 70778 SDs, 0 SdLazy, 41833 SolverSat, 4589 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 39.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2197 GetRequests, 119 SyntacticMatches, 68 SemanticMatches, 2010 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16337 ImplicationChecksByTransitivity, 168.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=5125occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.3s AutomataMinimizationTime, 47 MinimizatonAttempts, 62616 StatesRemovedByMinimization, 46 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 43.8s InterpolantComputationTime, 4439 NumberOfCodeBlocks, 4439 NumberOfCodeBlocksAsserted, 48 NumberOfCheckSat, 4290 ConstructedInterpolants, 0 QuantifiedInterpolants, 6921114 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 47 InterpolantComputations, 47 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...