./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/rfi001_rmo.oepc_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/rfi001_rmo.oepc_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 47e0e2e2f593a1c2b5c24aa2d193465263bbddc3 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 06:10:08,408 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 06:10:08,409 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 06:10:08,416 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 06:10:08,417 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 06:10:08,417 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 06:10:08,418 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 06:10:08,419 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 06:10:08,420 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 06:10:08,421 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 06:10:08,422 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 06:10:08,422 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 06:10:08,423 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 06:10:08,423 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 06:10:08,424 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 06:10:08,425 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 06:10:08,425 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 06:10:08,427 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 06:10:08,428 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 06:10:08,429 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 06:10:08,430 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 06:10:08,430 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 06:10:08,432 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 06:10:08,432 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 06:10:08,432 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 06:10:08,433 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 06:10:08,434 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 06:10:08,434 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 06:10:08,435 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 06:10:08,436 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 06:10:08,436 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 06:10:08,436 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 06:10:08,436 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 06:10:08,437 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 06:10:08,437 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 06:10:08,438 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 06:10:08,438 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-23 06:10:08,448 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 06:10:08,448 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 06:10:08,449 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 06:10:08,449 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 06:10:08,449 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 06:10:08,450 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 06:10:08,450 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 06:10:08,450 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 06:10:08,450 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 06:10:08,450 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 06:10:08,450 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 06:10:08,450 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 06:10:08,451 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 06:10:08,451 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 06:10:08,451 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 06:10:08,451 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 06:10:08,451 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 06:10:08,451 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 06:10:08,451 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 06:10:08,452 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 06:10:08,452 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 06:10:08,452 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 06:10:08,452 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 06:10:08,452 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 06:10:08,452 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 06:10:08,453 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 06:10:08,453 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 06:10:08,453 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 06:10:08,453 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 06:10:08,453 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 06:10:08,453 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 47e0e2e2f593a1c2b5c24aa2d193465263bbddc3 [2018-11-23 06:10:08,476 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 06:10:08,486 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 06:10:08,488 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 06:10:08,489 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 06:10:08,490 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 06:10:08,490 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer/../../sv-benchmarks/c/pthread-wmm/rfi001_rmo.oepc_false-unreach-call.i [2018-11-23 06:10:08,531 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer/data/71ff209fc/08216e29a0f042da860ecca18f1ea1b9/FLAG798b24bae [2018-11-23 06:10:08,970 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 06:10:08,971 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/sv-benchmarks/c/pthread-wmm/rfi001_rmo.oepc_false-unreach-call.i [2018-11-23 06:10:08,978 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer/data/71ff209fc/08216e29a0f042da860ecca18f1ea1b9/FLAG798b24bae [2018-11-23 06:10:08,989 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer/data/71ff209fc/08216e29a0f042da860ecca18f1ea1b9 [2018-11-23 06:10:08,991 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 06:10:08,992 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 06:10:08,993 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 06:10:08,993 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 06:10:08,995 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 06:10:08,996 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 06:10:08" (1/1) ... [2018-11-23 06:10:08,998 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@60445fa0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:08, skipping insertion in model container [2018-11-23 06:10:08,998 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 06:10:08" (1/1) ... [2018-11-23 06:10:09,004 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 06:10:09,036 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 06:10:09,261 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 06:10:09,271 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 06:10:09,360 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 06:10:09,402 INFO L195 MainTranslator]: Completed translation [2018-11-23 06:10:09,403 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:09 WrapperNode [2018-11-23 06:10:09,403 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 06:10:09,404 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 06:10:09,404 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 06:10:09,404 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 06:10:09,411 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:09" (1/1) ... [2018-11-23 06:10:09,424 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:09" (1/1) ... [2018-11-23 06:10:09,445 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 06:10:09,446 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 06:10:09,446 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 06:10:09,446 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 06:10:09,453 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:09" (1/1) ... [2018-11-23 06:10:09,453 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:09" (1/1) ... [2018-11-23 06:10:09,456 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:09" (1/1) ... [2018-11-23 06:10:09,456 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:09" (1/1) ... [2018-11-23 06:10:09,462 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:09" (1/1) ... [2018-11-23 06:10:09,464 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:09" (1/1) ... [2018-11-23 06:10:09,465 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:09" (1/1) ... [2018-11-23 06:10:09,467 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 06:10:09,468 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 06:10:09,468 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 06:10:09,468 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 06:10:09,469 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:09" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 06:10:09,503 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 06:10:09,503 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 06:10:09,503 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2018-11-23 06:10:09,503 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 06:10:09,503 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2018-11-23 06:10:09,504 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2018-11-23 06:10:09,504 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2018-11-23 06:10:09,504 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2018-11-23 06:10:09,504 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2018-11-23 06:10:09,504 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 06:10:09,504 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 06:10:09,505 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-23 06:10:09,991 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 06:10:09,991 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-23 06:10:09,991 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 06:10:09 BoogieIcfgContainer [2018-11-23 06:10:09,991 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 06:10:09,992 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 06:10:09,992 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 06:10:09,995 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 06:10:09,996 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 06:10:08" (1/3) ... [2018-11-23 06:10:09,996 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@ec27bfc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 06:10:09, skipping insertion in model container [2018-11-23 06:10:09,996 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 06:10:09" (2/3) ... [2018-11-23 06:10:09,997 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@ec27bfc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 06:10:09, skipping insertion in model container [2018-11-23 06:10:09,997 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 06:10:09" (3/3) ... [2018-11-23 06:10:09,999 INFO L112 eAbstractionObserver]: Analyzing ICFG rfi001_rmo.oepc_false-unreach-call.i [2018-11-23 06:10:10,025 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,025 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,025 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,025 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,025 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,025 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,025 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,026 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,026 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,026 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,026 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,026 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,026 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,026 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,027 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,027 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,027 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,027 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,027 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,027 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,027 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,028 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,028 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,028 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,028 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,028 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,028 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,029 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,029 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,029 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,029 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,029 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,029 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,029 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,030 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,030 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,030 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,030 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,031 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,031 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,031 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,031 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,031 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,031 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,031 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,032 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,032 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,032 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,032 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,032 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,032 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,032 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,033 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,033 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,033 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,033 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,033 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,033 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,034 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,034 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,035 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,035 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,035 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,035 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,035 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,035 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,035 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,036 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,036 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,036 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,036 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,036 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,036 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,036 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,036 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,036 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,037 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,037 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,037 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,037 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,037 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,037 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,037 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,037 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,037 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,038 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,038 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,038 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,038 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,038 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,038 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,039 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,039 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,039 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,039 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,039 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,039 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,039 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,040 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,040 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,040 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,040 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,040 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,040 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,040 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,041 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,041 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,041 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,041 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,041 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,041 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,041 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,042 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,042 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,042 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,042 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,042 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,043 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,043 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,043 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,043 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,043 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,043 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,043 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,044 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,044 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,044 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,044 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,044 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,044 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,044 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,045 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,045 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,045 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,045 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,045 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,045 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,045 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,046 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,046 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,046 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,046 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,046 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,046 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,046 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,047 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,047 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,047 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,047 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,047 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,048 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,048 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,048 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,048 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,048 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,048 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,048 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,049 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,049 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet39.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,049 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet39.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,049 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,049 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,049 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet39.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,049 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet39.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 06:10:10,067 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-23 06:10:10,067 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 06:10:10,073 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2018-11-23 06:10:10,084 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2018-11-23 06:10:10,101 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 06:10:10,102 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 06:10:10,102 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 06:10:10,102 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 06:10:10,102 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 06:10:10,102 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 06:10:10,102 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 06:10:10,103 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 06:10:10,103 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 06:10:10,111 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 143places, 181 transitions [2018-11-23 06:10:12,037 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 34807 states. [2018-11-23 06:10:12,039 INFO L276 IsEmpty]: Start isEmpty. Operand 34807 states. [2018-11-23 06:10:12,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-23 06:10:12,044 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:12,045 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:12,046 INFO L423 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:12,051 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:12,051 INFO L82 PathProgramCache]: Analyzing trace with hash 314479455, now seen corresponding path program 1 times [2018-11-23 06:10:12,053 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:12,053 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:12,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:12,091 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:12,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:12,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:12,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:12,213 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:12,213 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 06:10:12,216 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 06:10:12,224 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 06:10:12,224 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 06:10:12,226 INFO L87 Difference]: Start difference. First operand 34807 states. Second operand 4 states. [2018-11-23 06:10:12,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:12,810 INFO L93 Difference]: Finished difference Result 60791 states and 234494 transitions. [2018-11-23 06:10:12,811 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 06:10:12,812 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2018-11-23 06:10:12,812 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:13,021 INFO L225 Difference]: With dead ends: 60791 [2018-11-23 06:10:13,021 INFO L226 Difference]: Without dead ends: 44271 [2018-11-23 06:10:13,023 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 06:10:13,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44271 states. [2018-11-23 06:10:13,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44271 to 27339. [2018-11-23 06:10:13,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27339 states. [2018-11-23 06:10:14,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27339 states to 27339 states and 105500 transitions. [2018-11-23 06:10:14,009 INFO L78 Accepts]: Start accepts. Automaton has 27339 states and 105500 transitions. Word has length 34 [2018-11-23 06:10:14,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:14,009 INFO L480 AbstractCegarLoop]: Abstraction has 27339 states and 105500 transitions. [2018-11-23 06:10:14,009 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 06:10:14,010 INFO L276 IsEmpty]: Start isEmpty. Operand 27339 states and 105500 transitions. [2018-11-23 06:10:14,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-23 06:10:14,016 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:14,017 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:14,017 INFO L423 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:14,018 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:14,018 INFO L82 PathProgramCache]: Analyzing trace with hash -494436635, now seen corresponding path program 1 times [2018-11-23 06:10:14,018 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:14,018 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:14,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:14,022 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:14,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:14,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:14,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:14,087 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:14,087 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 06:10:14,088 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 06:10:14,088 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 06:10:14,088 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 06:10:14,089 INFO L87 Difference]: Start difference. First operand 27339 states and 105500 transitions. Second operand 3 states. [2018-11-23 06:10:14,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:14,308 INFO L93 Difference]: Finished difference Result 27339 states and 105223 transitions. [2018-11-23 06:10:14,308 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 06:10:14,308 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2018-11-23 06:10:14,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:14,382 INFO L225 Difference]: With dead ends: 27339 [2018-11-23 06:10:14,382 INFO L226 Difference]: Without dead ends: 27339 [2018-11-23 06:10:14,382 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 06:10:14,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27339 states. [2018-11-23 06:10:14,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27339 to 27339. [2018-11-23 06:10:14,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27339 states. [2018-11-23 06:10:15,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27339 states to 27339 states and 105223 transitions. [2018-11-23 06:10:15,001 INFO L78 Accepts]: Start accepts. Automaton has 27339 states and 105223 transitions. Word has length 46 [2018-11-23 06:10:15,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:15,002 INFO L480 AbstractCegarLoop]: Abstraction has 27339 states and 105223 transitions. [2018-11-23 06:10:15,002 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 06:10:15,002 INFO L276 IsEmpty]: Start isEmpty. Operand 27339 states and 105223 transitions. [2018-11-23 06:10:15,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-23 06:10:15,005 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:15,005 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:15,005 INFO L423 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:15,005 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:15,006 INFO L82 PathProgramCache]: Analyzing trace with hash 1248373700, now seen corresponding path program 1 times [2018-11-23 06:10:15,006 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:15,006 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:15,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:15,008 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:15,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:15,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:15,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:15,082 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:15,082 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 06:10:15,082 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 06:10:15,082 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 06:10:15,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 06:10:15,082 INFO L87 Difference]: Start difference. First operand 27339 states and 105223 transitions. Second operand 5 states. [2018-11-23 06:10:15,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:15,621 INFO L93 Difference]: Finished difference Result 64005 states and 235022 transitions. [2018-11-23 06:10:15,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 06:10:15,621 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 46 [2018-11-23 06:10:15,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:15,805 INFO L225 Difference]: With dead ends: 64005 [2018-11-23 06:10:15,805 INFO L226 Difference]: Without dead ends: 63453 [2018-11-23 06:10:15,805 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 06:10:16,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63453 states. [2018-11-23 06:10:16,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63453 to 41421. [2018-11-23 06:10:16,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41421 states. [2018-11-23 06:10:16,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41421 states to 41421 states and 152053 transitions. [2018-11-23 06:10:16,845 INFO L78 Accepts]: Start accepts. Automaton has 41421 states and 152053 transitions. Word has length 46 [2018-11-23 06:10:16,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:16,846 INFO L480 AbstractCegarLoop]: Abstraction has 41421 states and 152053 transitions. [2018-11-23 06:10:16,846 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 06:10:16,846 INFO L276 IsEmpty]: Start isEmpty. Operand 41421 states and 152053 transitions. [2018-11-23 06:10:16,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-23 06:10:16,849 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:16,849 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:16,849 INFO L423 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:16,849 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:16,849 INFO L82 PathProgramCache]: Analyzing trace with hash 1026875031, now seen corresponding path program 1 times [2018-11-23 06:10:16,850 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:16,850 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:16,851 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:16,851 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:16,852 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:16,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:16,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:16,921 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:16,921 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 06:10:16,921 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 06:10:16,922 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 06:10:16,922 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 06:10:16,922 INFO L87 Difference]: Start difference. First operand 41421 states and 152053 transitions. Second operand 5 states. [2018-11-23 06:10:17,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:17,368 INFO L93 Difference]: Finished difference Result 81367 states and 297636 transitions. [2018-11-23 06:10:17,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 06:10:17,369 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 47 [2018-11-23 06:10:17,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:17,819 INFO L225 Difference]: With dead ends: 81367 [2018-11-23 06:10:17,819 INFO L226 Difference]: Without dead ends: 80855 [2018-11-23 06:10:17,819 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 06:10:18,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80855 states. [2018-11-23 06:10:18,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80855 to 45375. [2018-11-23 06:10:18,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45375 states. [2018-11-23 06:10:18,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45375 states to 45375 states and 165678 transitions. [2018-11-23 06:10:18,677 INFO L78 Accepts]: Start accepts. Automaton has 45375 states and 165678 transitions. Word has length 47 [2018-11-23 06:10:18,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:18,677 INFO L480 AbstractCegarLoop]: Abstraction has 45375 states and 165678 transitions. [2018-11-23 06:10:18,677 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 06:10:18,677 INFO L276 IsEmpty]: Start isEmpty. Operand 45375 states and 165678 transitions. [2018-11-23 06:10:18,683 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-23 06:10:18,683 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:18,683 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:18,684 INFO L423 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:18,684 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:18,684 INFO L82 PathProgramCache]: Analyzing trace with hash -43389411, now seen corresponding path program 1 times [2018-11-23 06:10:18,684 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:18,684 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:18,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:18,686 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:18,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:18,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:18,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:18,733 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:18,733 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 06:10:18,733 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 06:10:18,733 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 06:10:18,733 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 06:10:18,734 INFO L87 Difference]: Start difference. First operand 45375 states and 165678 transitions. Second operand 3 states. [2018-11-23 06:10:18,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:18,952 INFO L93 Difference]: Finished difference Result 65251 states and 235338 transitions. [2018-11-23 06:10:18,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 06:10:18,952 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2018-11-23 06:10:18,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:19,064 INFO L225 Difference]: With dead ends: 65251 [2018-11-23 06:10:19,064 INFO L226 Difference]: Without dead ends: 65251 [2018-11-23 06:10:19,064 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 06:10:19,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65251 states. [2018-11-23 06:10:20,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65251 to 50945. [2018-11-23 06:10:20,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50945 states. [2018-11-23 06:10:20,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50945 states to 50945 states and 183963 transitions. [2018-11-23 06:10:20,197 INFO L78 Accepts]: Start accepts. Automaton has 50945 states and 183963 transitions. Word has length 49 [2018-11-23 06:10:20,197 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:20,197 INFO L480 AbstractCegarLoop]: Abstraction has 50945 states and 183963 transitions. [2018-11-23 06:10:20,197 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 06:10:20,197 INFO L276 IsEmpty]: Start isEmpty. Operand 50945 states and 183963 transitions. [2018-11-23 06:10:20,207 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-11-23 06:10:20,207 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:20,207 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:20,207 INFO L423 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:20,208 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:20,208 INFO L82 PathProgramCache]: Analyzing trace with hash -860096332, now seen corresponding path program 1 times [2018-11-23 06:10:20,208 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:20,208 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:20,209 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:20,209 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:20,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:20,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:20,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:20,296 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:20,296 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 06:10:20,297 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 06:10:20,297 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 06:10:20,297 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-23 06:10:20,297 INFO L87 Difference]: Start difference. First operand 50945 states and 183963 transitions. Second operand 6 states. [2018-11-23 06:10:20,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:20,799 INFO L93 Difference]: Finished difference Result 67511 states and 241920 transitions. [2018-11-23 06:10:20,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 06:10:20,800 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 53 [2018-11-23 06:10:20,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:20,921 INFO L225 Difference]: With dead ends: 67511 [2018-11-23 06:10:20,921 INFO L226 Difference]: Without dead ends: 67511 [2018-11-23 06:10:20,921 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 06:10:21,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67511 states. [2018-11-23 06:10:21,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67511 to 63436. [2018-11-23 06:10:21,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63436 states. [2018-11-23 06:10:22,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63436 states to 63436 states and 227319 transitions. [2018-11-23 06:10:22,069 INFO L78 Accepts]: Start accepts. Automaton has 63436 states and 227319 transitions. Word has length 53 [2018-11-23 06:10:22,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:22,069 INFO L480 AbstractCegarLoop]: Abstraction has 63436 states and 227319 transitions. [2018-11-23 06:10:22,069 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 06:10:22,070 INFO L276 IsEmpty]: Start isEmpty. Operand 63436 states and 227319 transitions. [2018-11-23 06:10:22,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-11-23 06:10:22,078 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:22,078 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:22,079 INFO L423 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:22,079 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:22,079 INFO L82 PathProgramCache]: Analyzing trace with hash 1637919605, now seen corresponding path program 1 times [2018-11-23 06:10:22,079 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:22,079 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:22,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:22,081 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:22,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:22,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:22,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:22,146 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:22,146 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 06:10:22,146 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 06:10:22,146 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 06:10:22,146 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:22,146 INFO L87 Difference]: Start difference. First operand 63436 states and 227319 transitions. Second operand 7 states. [2018-11-23 06:10:22,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:22,876 INFO L93 Difference]: Finished difference Result 88528 states and 305936 transitions. [2018-11-23 06:10:22,876 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-23 06:10:22,876 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 53 [2018-11-23 06:10:22,876 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:23,031 INFO L225 Difference]: With dead ends: 88528 [2018-11-23 06:10:23,031 INFO L226 Difference]: Without dead ends: 88528 [2018-11-23 06:10:23,031 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-11-23 06:10:23,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88528 states. [2018-11-23 06:10:24,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88528 to 74881. [2018-11-23 06:10:24,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74881 states. [2018-11-23 06:10:24,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74881 states to 74881 states and 262722 transitions. [2018-11-23 06:10:24,250 INFO L78 Accepts]: Start accepts. Automaton has 74881 states and 262722 transitions. Word has length 53 [2018-11-23 06:10:24,250 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:24,251 INFO L480 AbstractCegarLoop]: Abstraction has 74881 states and 262722 transitions. [2018-11-23 06:10:24,251 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 06:10:24,251 INFO L276 IsEmpty]: Start isEmpty. Operand 74881 states and 262722 transitions. [2018-11-23 06:10:24,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-11-23 06:10:24,549 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:24,550 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:24,550 INFO L423 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:24,550 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:24,550 INFO L82 PathProgramCache]: Analyzing trace with hash -1769544010, now seen corresponding path program 1 times [2018-11-23 06:10:24,550 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:24,550 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:24,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:24,552 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:24,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:24,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:24,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:24,586 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:24,586 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 06:10:24,586 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 06:10:24,586 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 06:10:24,587 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 06:10:24,587 INFO L87 Difference]: Start difference. First operand 74881 states and 262722 transitions. Second operand 4 states. [2018-11-23 06:10:24,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:24,654 INFO L93 Difference]: Finished difference Result 15375 states and 48802 transitions. [2018-11-23 06:10:24,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 06:10:24,654 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 53 [2018-11-23 06:10:24,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:24,671 INFO L225 Difference]: With dead ends: 15375 [2018-11-23 06:10:24,671 INFO L226 Difference]: Without dead ends: 13789 [2018-11-23 06:10:24,671 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 06:10:24,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13789 states. [2018-11-23 06:10:24,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13789 to 13740. [2018-11-23 06:10:24,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13740 states. [2018-11-23 06:10:24,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13740 states to 13740 states and 43328 transitions. [2018-11-23 06:10:24,817 INFO L78 Accepts]: Start accepts. Automaton has 13740 states and 43328 transitions. Word has length 53 [2018-11-23 06:10:24,817 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:24,817 INFO L480 AbstractCegarLoop]: Abstraction has 13740 states and 43328 transitions. [2018-11-23 06:10:24,817 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 06:10:24,817 INFO L276 IsEmpty]: Start isEmpty. Operand 13740 states and 43328 transitions. [2018-11-23 06:10:24,818 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-11-23 06:10:24,818 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:24,818 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:24,818 INFO L423 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:24,818 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:24,818 INFO L82 PathProgramCache]: Analyzing trace with hash -431668952, now seen corresponding path program 1 times [2018-11-23 06:10:24,819 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:24,819 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:24,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:24,820 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:24,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:24,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:24,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:24,899 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:24,899 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 06:10:24,899 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 06:10:24,900 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 06:10:24,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 06:10:24,900 INFO L87 Difference]: Start difference. First operand 13740 states and 43328 transitions. Second operand 6 states. [2018-11-23 06:10:25,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:25,209 INFO L93 Difference]: Finished difference Result 19970 states and 62557 transitions. [2018-11-23 06:10:25,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 06:10:25,209 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 53 [2018-11-23 06:10:25,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:25,232 INFO L225 Difference]: With dead ends: 19970 [2018-11-23 06:10:25,233 INFO L226 Difference]: Without dead ends: 19898 [2018-11-23 06:10:25,233 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2018-11-23 06:10:25,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19898 states. [2018-11-23 06:10:25,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19898 to 14314. [2018-11-23 06:10:25,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14314 states. [2018-11-23 06:10:25,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14314 states to 14314 states and 45025 transitions. [2018-11-23 06:10:25,416 INFO L78 Accepts]: Start accepts. Automaton has 14314 states and 45025 transitions. Word has length 53 [2018-11-23 06:10:25,417 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:25,417 INFO L480 AbstractCegarLoop]: Abstraction has 14314 states and 45025 transitions. [2018-11-23 06:10:25,417 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 06:10:25,417 INFO L276 IsEmpty]: Start isEmpty. Operand 14314 states and 45025 transitions. [2018-11-23 06:10:25,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-11-23 06:10:25,420 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:25,420 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:25,420 INFO L423 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:25,421 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:25,421 INFO L82 PathProgramCache]: Analyzing trace with hash -488484476, now seen corresponding path program 1 times [2018-11-23 06:10:25,421 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:25,421 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:25,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:25,422 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:25,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:25,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:25,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:25,471 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:25,471 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 06:10:25,472 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 06:10:25,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 06:10:25,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 06:10:25,472 INFO L87 Difference]: Start difference. First operand 14314 states and 45025 transitions. Second operand 4 states. [2018-11-23 06:10:25,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:25,562 INFO L93 Difference]: Finished difference Result 16617 states and 52353 transitions. [2018-11-23 06:10:25,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 06:10:25,562 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 61 [2018-11-23 06:10:25,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:25,582 INFO L225 Difference]: With dead ends: 16617 [2018-11-23 06:10:25,582 INFO L226 Difference]: Without dead ends: 16617 [2018-11-23 06:10:25,583 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 06:10:25,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16617 states. [2018-11-23 06:10:25,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16617 to 15134. [2018-11-23 06:10:25,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15134 states. [2018-11-23 06:10:25,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15134 states to 15134 states and 47615 transitions. [2018-11-23 06:10:25,757 INFO L78 Accepts]: Start accepts. Automaton has 15134 states and 47615 transitions. Word has length 61 [2018-11-23 06:10:25,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:25,758 INFO L480 AbstractCegarLoop]: Abstraction has 15134 states and 47615 transitions. [2018-11-23 06:10:25,758 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 06:10:25,758 INFO L276 IsEmpty]: Start isEmpty. Operand 15134 states and 47615 transitions. [2018-11-23 06:10:25,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-11-23 06:10:25,760 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:25,760 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:25,760 INFO L423 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:25,761 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:25,761 INFO L82 PathProgramCache]: Analyzing trace with hash 1254325859, now seen corresponding path program 1 times [2018-11-23 06:10:25,761 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:25,761 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:25,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:25,762 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:25,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:25,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:25,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:25,841 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:25,842 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 06:10:25,842 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 06:10:25,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 06:10:25,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 06:10:25,842 INFO L87 Difference]: Start difference. First operand 15134 states and 47615 transitions. Second operand 6 states. [2018-11-23 06:10:26,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:26,149 INFO L93 Difference]: Finished difference Result 28106 states and 88091 transitions. [2018-11-23 06:10:26,150 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 06:10:26,150 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 61 [2018-11-23 06:10:26,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:26,189 INFO L225 Difference]: With dead ends: 28106 [2018-11-23 06:10:26,189 INFO L226 Difference]: Without dead ends: 28035 [2018-11-23 06:10:26,189 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2018-11-23 06:10:26,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28035 states. [2018-11-23 06:10:26,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28035 to 17412. [2018-11-23 06:10:26,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17412 states. [2018-11-23 06:10:26,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17412 states to 17412 states and 54277 transitions. [2018-11-23 06:10:26,447 INFO L78 Accepts]: Start accepts. Automaton has 17412 states and 54277 transitions. Word has length 61 [2018-11-23 06:10:26,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:26,447 INFO L480 AbstractCegarLoop]: Abstraction has 17412 states and 54277 transitions. [2018-11-23 06:10:26,447 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 06:10:26,447 INFO L276 IsEmpty]: Start isEmpty. Operand 17412 states and 54277 transitions. [2018-11-23 06:10:26,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-11-23 06:10:26,451 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:26,451 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:26,452 INFO L423 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:26,452 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:26,452 INFO L82 PathProgramCache]: Analyzing trace with hash -1214039529, now seen corresponding path program 1 times [2018-11-23 06:10:26,452 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:26,452 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:26,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:26,453 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:26,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:26,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:26,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:26,501 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:26,501 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 06:10:26,502 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 06:10:26,502 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 06:10:26,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 06:10:26,502 INFO L87 Difference]: Start difference. First operand 17412 states and 54277 transitions. Second operand 3 states. [2018-11-23 06:10:26,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:26,652 INFO L93 Difference]: Finished difference Result 18092 states and 56109 transitions. [2018-11-23 06:10:26,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 06:10:26,653 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2018-11-23 06:10:26,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:26,673 INFO L225 Difference]: With dead ends: 18092 [2018-11-23 06:10:26,673 INFO L226 Difference]: Without dead ends: 18092 [2018-11-23 06:10:26,673 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 06:10:26,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18092 states. [2018-11-23 06:10:26,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18092 to 17752. [2018-11-23 06:10:26,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17752 states. [2018-11-23 06:10:26,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17752 states to 17752 states and 55193 transitions. [2018-11-23 06:10:26,857 INFO L78 Accepts]: Start accepts. Automaton has 17752 states and 55193 transitions. Word has length 65 [2018-11-23 06:10:26,857 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:26,857 INFO L480 AbstractCegarLoop]: Abstraction has 17752 states and 55193 transitions. [2018-11-23 06:10:26,857 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 06:10:26,857 INFO L276 IsEmpty]: Start isEmpty. Operand 17752 states and 55193 transitions. [2018-11-23 06:10:26,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-11-23 06:10:26,861 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:26,861 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:26,862 INFO L423 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:26,862 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:26,862 INFO L82 PathProgramCache]: Analyzing trace with hash 863169814, now seen corresponding path program 1 times [2018-11-23 06:10:26,862 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:26,862 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:26,863 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:26,863 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:26,863 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:26,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:26,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:26,905 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:26,905 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 06:10:26,905 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 06:10:26,905 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 06:10:26,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 06:10:26,906 INFO L87 Difference]: Start difference. First operand 17752 states and 55193 transitions. Second operand 4 states. [2018-11-23 06:10:27,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:27,075 INFO L93 Difference]: Finished difference Result 21696 states and 66682 transitions. [2018-11-23 06:10:27,075 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 06:10:27,075 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 65 [2018-11-23 06:10:27,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:27,099 INFO L225 Difference]: With dead ends: 21696 [2018-11-23 06:10:27,099 INFO L226 Difference]: Without dead ends: 21696 [2018-11-23 06:10:27,099 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 06:10:27,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21696 states. [2018-11-23 06:10:27,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21696 to 19646. [2018-11-23 06:10:27,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19646 states. [2018-11-23 06:10:27,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19646 states to 19646 states and 60572 transitions. [2018-11-23 06:10:27,320 INFO L78 Accepts]: Start accepts. Automaton has 19646 states and 60572 transitions. Word has length 65 [2018-11-23 06:10:27,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:27,321 INFO L480 AbstractCegarLoop]: Abstraction has 19646 states and 60572 transitions. [2018-11-23 06:10:27,321 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 06:10:27,321 INFO L276 IsEmpty]: Start isEmpty. Operand 19646 states and 60572 transitions. [2018-11-23 06:10:27,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-23 06:10:27,327 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:27,327 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:27,327 INFO L423 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:27,327 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:27,327 INFO L82 PathProgramCache]: Analyzing trace with hash 1085072735, now seen corresponding path program 1 times [2018-11-23 06:10:27,327 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:27,327 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:27,328 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:27,329 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:27,329 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:27,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:27,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:27,409 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:27,409 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 06:10:27,409 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 06:10:27,409 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 06:10:27,410 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 06:10:27,410 INFO L87 Difference]: Start difference. First operand 19646 states and 60572 transitions. Second operand 6 states. [2018-11-23 06:10:27,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:27,992 INFO L93 Difference]: Finished difference Result 23814 states and 72270 transitions. [2018-11-23 06:10:27,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 06:10:27,992 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 67 [2018-11-23 06:10:27,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:28,018 INFO L225 Difference]: With dead ends: 23814 [2018-11-23 06:10:28,018 INFO L226 Difference]: Without dead ends: 23814 [2018-11-23 06:10:28,018 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:28,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23814 states. [2018-11-23 06:10:28,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23814 to 22474. [2018-11-23 06:10:28,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22474 states. [2018-11-23 06:10:28,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22474 states to 22474 states and 68700 transitions. [2018-11-23 06:10:28,261 INFO L78 Accepts]: Start accepts. Automaton has 22474 states and 68700 transitions. Word has length 67 [2018-11-23 06:10:28,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:28,261 INFO L480 AbstractCegarLoop]: Abstraction has 22474 states and 68700 transitions. [2018-11-23 06:10:28,261 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 06:10:28,261 INFO L276 IsEmpty]: Start isEmpty. Operand 22474 states and 68700 transitions. [2018-11-23 06:10:28,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-23 06:10:28,268 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:28,268 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:28,269 INFO L423 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:28,269 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:28,269 INFO L82 PathProgramCache]: Analyzing trace with hash -992136608, now seen corresponding path program 1 times [2018-11-23 06:10:28,269 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:28,269 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:28,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:28,271 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:28,271 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:28,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:28,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:28,346 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:28,347 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 06:10:28,347 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 06:10:28,347 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 06:10:28,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 06:10:28,347 INFO L87 Difference]: Start difference. First operand 22474 states and 68700 transitions. Second operand 6 states. [2018-11-23 06:10:28,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:28,644 INFO L93 Difference]: Finished difference Result 25702 states and 76160 transitions. [2018-11-23 06:10:28,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 06:10:28,644 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 67 [2018-11-23 06:10:28,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:28,673 INFO L225 Difference]: With dead ends: 25702 [2018-11-23 06:10:28,673 INFO L226 Difference]: Without dead ends: 25702 [2018-11-23 06:10:28,674 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-11-23 06:10:28,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25702 states. [2018-11-23 06:10:28,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25702 to 22858. [2018-11-23 06:10:28,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22858 states. [2018-11-23 06:10:28,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22858 states to 22858 states and 68806 transitions. [2018-11-23 06:10:28,924 INFO L78 Accepts]: Start accepts. Automaton has 22858 states and 68806 transitions. Word has length 67 [2018-11-23 06:10:28,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:28,925 INFO L480 AbstractCegarLoop]: Abstraction has 22858 states and 68806 transitions. [2018-11-23 06:10:28,925 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 06:10:28,925 INFO L276 IsEmpty]: Start isEmpty. Operand 22858 states and 68806 transitions. [2018-11-23 06:10:28,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-23 06:10:28,932 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:28,932 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:28,932 INFO L423 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:28,932 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:28,932 INFO L82 PathProgramCache]: Analyzing trace with hash -780785695, now seen corresponding path program 1 times [2018-11-23 06:10:28,932 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:28,932 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:28,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:28,933 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:28,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:28,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:28,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:28,990 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:28,990 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 06:10:28,990 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 06:10:28,990 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 06:10:28,990 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 06:10:28,991 INFO L87 Difference]: Start difference. First operand 22858 states and 68806 transitions. Second operand 5 states. [2018-11-23 06:10:29,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:29,219 INFO L93 Difference]: Finished difference Result 29793 states and 89371 transitions. [2018-11-23 06:10:29,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 06:10:29,219 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 67 [2018-11-23 06:10:29,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:29,252 INFO L225 Difference]: With dead ends: 29793 [2018-11-23 06:10:29,252 INFO L226 Difference]: Without dead ends: 29793 [2018-11-23 06:10:29,252 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:29,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29793 states. [2018-11-23 06:10:29,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29793 to 26814. [2018-11-23 06:10:29,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26814 states. [2018-11-23 06:10:29,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26814 states to 26814 states and 80315 transitions. [2018-11-23 06:10:29,555 INFO L78 Accepts]: Start accepts. Automaton has 26814 states and 80315 transitions. Word has length 67 [2018-11-23 06:10:29,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:29,556 INFO L480 AbstractCegarLoop]: Abstraction has 26814 states and 80315 transitions. [2018-11-23 06:10:29,556 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 06:10:29,556 INFO L276 IsEmpty]: Start isEmpty. Operand 26814 states and 80315 transitions. [2018-11-23 06:10:29,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-23 06:10:29,565 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:29,565 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:29,566 INFO L423 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:29,566 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:29,566 INFO L82 PathProgramCache]: Analyzing trace with hash -1291319872, now seen corresponding path program 1 times [2018-11-23 06:10:29,566 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:29,566 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:29,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:29,567 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:29,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:29,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:29,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:29,622 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:29,623 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 06:10:29,623 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 06:10:29,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 06:10:29,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 06:10:29,623 INFO L87 Difference]: Start difference. First operand 26814 states and 80315 transitions. Second operand 5 states. [2018-11-23 06:10:29,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:29,970 INFO L93 Difference]: Finished difference Result 36420 states and 108385 transitions. [2018-11-23 06:10:29,970 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 06:10:29,970 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 67 [2018-11-23 06:10:29,971 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:30,013 INFO L225 Difference]: With dead ends: 36420 [2018-11-23 06:10:30,013 INFO L226 Difference]: Without dead ends: 36420 [2018-11-23 06:10:30,013 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 06:10:30,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36420 states. [2018-11-23 06:10:30,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36420 to 29428. [2018-11-23 06:10:30,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29428 states. [2018-11-23 06:10:30,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29428 states to 29428 states and 87791 transitions. [2018-11-23 06:10:30,372 INFO L78 Accepts]: Start accepts. Automaton has 29428 states and 87791 transitions. Word has length 67 [2018-11-23 06:10:30,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:30,372 INFO L480 AbstractCegarLoop]: Abstraction has 29428 states and 87791 transitions. [2018-11-23 06:10:30,372 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 06:10:30,373 INFO L276 IsEmpty]: Start isEmpty. Operand 29428 states and 87791 transitions. [2018-11-23 06:10:30,380 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-23 06:10:30,380 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:30,380 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:30,380 INFO L423 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:30,381 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:30,381 INFO L82 PathProgramCache]: Analyzing trace with hash 1196192961, now seen corresponding path program 1 times [2018-11-23 06:10:30,381 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:30,381 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:30,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:30,382 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:30,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:30,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:30,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:30,430 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:30,430 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 06:10:30,430 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 06:10:30,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 06:10:30,430 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 06:10:30,430 INFO L87 Difference]: Start difference. First operand 29428 states and 87791 transitions. Second operand 4 states. [2018-11-23 06:10:30,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:30,840 INFO L93 Difference]: Finished difference Result 38892 states and 116477 transitions. [2018-11-23 06:10:30,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 06:10:30,840 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 67 [2018-11-23 06:10:30,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:30,890 INFO L225 Difference]: With dead ends: 38892 [2018-11-23 06:10:30,890 INFO L226 Difference]: Without dead ends: 38660 [2018-11-23 06:10:30,890 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 06:10:30,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38660 states. [2018-11-23 06:10:31,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38660 to 35784. [2018-11-23 06:10:31,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35784 states. [2018-11-23 06:10:31,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35784 states to 35784 states and 107258 transitions. [2018-11-23 06:10:31,297 INFO L78 Accepts]: Start accepts. Automaton has 35784 states and 107258 transitions. Word has length 67 [2018-11-23 06:10:31,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:31,297 INFO L480 AbstractCegarLoop]: Abstraction has 35784 states and 107258 transitions. [2018-11-23 06:10:31,297 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 06:10:31,297 INFO L276 IsEmpty]: Start isEmpty. Operand 35784 states and 107258 transitions. [2018-11-23 06:10:31,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-23 06:10:31,305 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:31,305 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:31,305 INFO L423 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:31,305 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:31,305 INFO L82 PathProgramCache]: Analyzing trace with hash -600758398, now seen corresponding path program 1 times [2018-11-23 06:10:31,305 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:31,305 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:31,307 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:31,307 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:31,307 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:31,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:31,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:31,368 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:31,368 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 06:10:31,369 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 06:10:31,369 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 06:10:31,369 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 06:10:31,369 INFO L87 Difference]: Start difference. First operand 35784 states and 107258 transitions. Second operand 5 states. [2018-11-23 06:10:31,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:31,412 INFO L93 Difference]: Finished difference Result 9316 states and 22547 transitions. [2018-11-23 06:10:31,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 06:10:31,413 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 67 [2018-11-23 06:10:31,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:31,419 INFO L225 Difference]: With dead ends: 9316 [2018-11-23 06:10:31,419 INFO L226 Difference]: Without dead ends: 7464 [2018-11-23 06:10:31,419 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:31,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7464 states. [2018-11-23 06:10:31,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7464 to 6361. [2018-11-23 06:10:31,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6361 states. [2018-11-23 06:10:31,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6361 states to 6361 states and 15018 transitions. [2018-11-23 06:10:31,480 INFO L78 Accepts]: Start accepts. Automaton has 6361 states and 15018 transitions. Word has length 67 [2018-11-23 06:10:31,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:31,481 INFO L480 AbstractCegarLoop]: Abstraction has 6361 states and 15018 transitions. [2018-11-23 06:10:31,481 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 06:10:31,481 INFO L276 IsEmpty]: Start isEmpty. Operand 6361 states and 15018 transitions. [2018-11-23 06:10:31,484 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-23 06:10:31,484 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:31,485 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:31,485 INFO L423 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:31,485 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:31,485 INFO L82 PathProgramCache]: Analyzing trace with hash -1144549580, now seen corresponding path program 1 times [2018-11-23 06:10:31,485 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:31,485 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:31,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:31,487 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:31,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:31,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:31,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:31,521 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:31,521 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 06:10:31,521 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 06:10:31,521 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 06:10:31,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 06:10:31,521 INFO L87 Difference]: Start difference. First operand 6361 states and 15018 transitions. Second operand 3 states. [2018-11-23 06:10:31,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:31,548 INFO L93 Difference]: Finished difference Result 8820 states and 20757 transitions. [2018-11-23 06:10:31,549 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 06:10:31,549 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2018-11-23 06:10:31,549 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:31,555 INFO L225 Difference]: With dead ends: 8820 [2018-11-23 06:10:31,556 INFO L226 Difference]: Without dead ends: 8820 [2018-11-23 06:10:31,556 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 06:10:31,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8820 states. [2018-11-23 06:10:31,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8820 to 6300. [2018-11-23 06:10:31,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6300 states. [2018-11-23 06:10:31,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6300 states to 6300 states and 14558 transitions. [2018-11-23 06:10:31,615 INFO L78 Accepts]: Start accepts. Automaton has 6300 states and 14558 transitions. Word has length 67 [2018-11-23 06:10:31,615 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:31,615 INFO L480 AbstractCegarLoop]: Abstraction has 6300 states and 14558 transitions. [2018-11-23 06:10:31,615 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 06:10:31,615 INFO L276 IsEmpty]: Start isEmpty. Operand 6300 states and 14558 transitions. [2018-11-23 06:10:31,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-23 06:10:31,619 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:31,619 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:31,619 INFO L423 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:31,619 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:31,619 INFO L82 PathProgramCache]: Analyzing trace with hash 1467487719, now seen corresponding path program 1 times [2018-11-23 06:10:31,619 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:31,619 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:31,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:31,621 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:31,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:31,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:31,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:31,665 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:31,665 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 06:10:31,665 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 06:10:31,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 06:10:31,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 06:10:31,666 INFO L87 Difference]: Start difference. First operand 6300 states and 14558 transitions. Second operand 5 states. [2018-11-23 06:10:31,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:31,807 INFO L93 Difference]: Finished difference Result 7470 states and 17199 transitions. [2018-11-23 06:10:31,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 06:10:31,807 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2018-11-23 06:10:31,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:31,815 INFO L225 Difference]: With dead ends: 7470 [2018-11-23 06:10:31,815 INFO L226 Difference]: Without dead ends: 7470 [2018-11-23 06:10:31,815 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-23 06:10:31,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7470 states. [2018-11-23 06:10:31,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7470 to 6744. [2018-11-23 06:10:31,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6744 states. [2018-11-23 06:10:31,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6744 states to 6744 states and 15562 transitions. [2018-11-23 06:10:31,893 INFO L78 Accepts]: Start accepts. Automaton has 6744 states and 15562 transitions. Word has length 73 [2018-11-23 06:10:31,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:31,894 INFO L480 AbstractCegarLoop]: Abstraction has 6744 states and 15562 transitions. [2018-11-23 06:10:31,894 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 06:10:31,894 INFO L276 IsEmpty]: Start isEmpty. Operand 6744 states and 15562 transitions. [2018-11-23 06:10:31,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-23 06:10:31,899 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:31,899 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:31,899 INFO L423 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:31,900 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:31,900 INFO L82 PathProgramCache]: Analyzing trace with hash -1084669242, now seen corresponding path program 1 times [2018-11-23 06:10:31,900 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:31,900 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:31,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:31,901 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:31,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:31,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:31,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:31,952 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:31,953 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 06:10:31,953 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 06:10:31,953 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 06:10:31,953 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:31,953 INFO L87 Difference]: Start difference. First operand 6744 states and 15562 transitions. Second operand 7 states. [2018-11-23 06:10:32,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:32,266 INFO L93 Difference]: Finished difference Result 7881 states and 17984 transitions. [2018-11-23 06:10:32,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 06:10:32,267 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 73 [2018-11-23 06:10:32,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:32,274 INFO L225 Difference]: With dead ends: 7881 [2018-11-23 06:10:32,274 INFO L226 Difference]: Without dead ends: 7762 [2018-11-23 06:10:32,275 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=211, Unknown=0, NotChecked=0, Total=272 [2018-11-23 06:10:32,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7762 states. [2018-11-23 06:10:32,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7762 to 6841. [2018-11-23 06:10:32,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6841 states. [2018-11-23 06:10:32,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6841 states to 6841 states and 15655 transitions. [2018-11-23 06:10:32,381 INFO L78 Accepts]: Start accepts. Automaton has 6841 states and 15655 transitions. Word has length 73 [2018-11-23 06:10:32,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:32,381 INFO L480 AbstractCegarLoop]: Abstraction has 6841 states and 15655 transitions. [2018-11-23 06:10:32,381 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 06:10:32,381 INFO L276 IsEmpty]: Start isEmpty. Operand 6841 states and 15655 transitions. [2018-11-23 06:10:32,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-23 06:10:32,387 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:32,387 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:32,387 INFO L423 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:32,387 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:32,387 INFO L82 PathProgramCache]: Analyzing trace with hash -604903176, now seen corresponding path program 1 times [2018-11-23 06:10:32,387 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:32,388 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:32,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:32,389 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:32,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:32,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:32,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:32,434 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:32,434 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 06:10:32,434 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 06:10:32,435 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 06:10:32,435 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 06:10:32,435 INFO L87 Difference]: Start difference. First operand 6841 states and 15655 transitions. Second operand 4 states. [2018-11-23 06:10:32,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:32,608 INFO L93 Difference]: Finished difference Result 10608 states and 24142 transitions. [2018-11-23 06:10:32,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 06:10:32,609 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 92 [2018-11-23 06:10:32,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:32,616 INFO L225 Difference]: With dead ends: 10608 [2018-11-23 06:10:32,616 INFO L226 Difference]: Without dead ends: 10608 [2018-11-23 06:10:32,616 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 06:10:32,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10608 states. [2018-11-23 06:10:32,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10608 to 7961. [2018-11-23 06:10:32,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7961 states. [2018-11-23 06:10:32,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7961 states to 7961 states and 17989 transitions. [2018-11-23 06:10:32,689 INFO L78 Accepts]: Start accepts. Automaton has 7961 states and 17989 transitions. Word has length 92 [2018-11-23 06:10:32,689 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:32,689 INFO L480 AbstractCegarLoop]: Abstraction has 7961 states and 17989 transitions. [2018-11-23 06:10:32,689 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 06:10:32,690 INFO L276 IsEmpty]: Start isEmpty. Operand 7961 states and 17989 transitions. [2018-11-23 06:10:32,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-23 06:10:32,696 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:32,696 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:32,696 INFO L423 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:32,696 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:32,696 INFO L82 PathProgramCache]: Analyzing trace with hash 1910246266, now seen corresponding path program 2 times [2018-11-23 06:10:32,696 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:32,696 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:32,697 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:32,697 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:32,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:32,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:32,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:32,745 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:32,745 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 06:10:32,745 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 06:10:32,745 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 06:10:32,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 06:10:32,746 INFO L87 Difference]: Start difference. First operand 7961 states and 17989 transitions. Second operand 4 states. [2018-11-23 06:10:32,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:32,809 INFO L93 Difference]: Finished difference Result 8526 states and 19282 transitions. [2018-11-23 06:10:32,809 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 06:10:32,809 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 92 [2018-11-23 06:10:32,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:32,815 INFO L225 Difference]: With dead ends: 8526 [2018-11-23 06:10:32,815 INFO L226 Difference]: Without dead ends: 8526 [2018-11-23 06:10:32,815 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 06:10:32,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8526 states. [2018-11-23 06:10:32,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8526 to 7867. [2018-11-23 06:10:32,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7867 states. [2018-11-23 06:10:32,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7867 states to 7867 states and 17884 transitions. [2018-11-23 06:10:32,879 INFO L78 Accepts]: Start accepts. Automaton has 7867 states and 17884 transitions. Word has length 92 [2018-11-23 06:10:32,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:32,879 INFO L480 AbstractCegarLoop]: Abstraction has 7867 states and 17884 transitions. [2018-11-23 06:10:32,879 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 06:10:32,879 INFO L276 IsEmpty]: Start isEmpty. Operand 7867 states and 17884 transitions. [2018-11-23 06:10:32,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 06:10:32,885 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:32,885 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:32,885 INFO L423 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:32,885 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:32,886 INFO L82 PathProgramCache]: Analyzing trace with hash 1465486910, now seen corresponding path program 1 times [2018-11-23 06:10:32,886 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:32,886 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:32,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:32,887 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 06:10:32,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:32,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:32,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:32,986 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:32,986 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 06:10:32,986 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 06:10:32,986 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 06:10:32,987 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:32,987 INFO L87 Difference]: Start difference. First operand 7867 states and 17884 transitions. Second operand 7 states. [2018-11-23 06:10:33,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:33,577 INFO L93 Difference]: Finished difference Result 9705 states and 21992 transitions. [2018-11-23 06:10:33,577 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 06:10:33,577 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 94 [2018-11-23 06:10:33,578 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:33,587 INFO L225 Difference]: With dead ends: 9705 [2018-11-23 06:10:33,587 INFO L226 Difference]: Without dead ends: 9705 [2018-11-23 06:10:33,587 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:33,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9705 states. [2018-11-23 06:10:33,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9705 to 7979. [2018-11-23 06:10:33,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7979 states. [2018-11-23 06:10:33,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7979 states to 7979 states and 18204 transitions. [2018-11-23 06:10:33,684 INFO L78 Accepts]: Start accepts. Automaton has 7979 states and 18204 transitions. Word has length 94 [2018-11-23 06:10:33,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:33,684 INFO L480 AbstractCegarLoop]: Abstraction has 7979 states and 18204 transitions. [2018-11-23 06:10:33,684 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 06:10:33,684 INFO L276 IsEmpty]: Start isEmpty. Operand 7979 states and 18204 transitions. [2018-11-23 06:10:33,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 06:10:33,692 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:33,692 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:33,692 INFO L423 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:33,693 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:33,693 INFO L82 PathProgramCache]: Analyzing trace with hash 631244515, now seen corresponding path program 1 times [2018-11-23 06:10:33,693 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:33,693 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:33,694 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:33,694 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:33,694 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:33,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:33,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:33,740 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:33,740 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 06:10:33,741 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 06:10:33,742 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 06:10:33,742 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 06:10:33,742 INFO L87 Difference]: Start difference. First operand 7979 states and 18204 transitions. Second operand 5 states. [2018-11-23 06:10:33,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:33,861 INFO L93 Difference]: Finished difference Result 8886 states and 20162 transitions. [2018-11-23 06:10:33,862 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 06:10:33,863 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 94 [2018-11-23 06:10:33,863 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:33,872 INFO L225 Difference]: With dead ends: 8886 [2018-11-23 06:10:33,873 INFO L226 Difference]: Without dead ends: 8886 [2018-11-23 06:10:33,873 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:33,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8886 states. [2018-11-23 06:10:33,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8886 to 6875. [2018-11-23 06:10:33,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6875 states. [2018-11-23 06:10:33,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6875 states to 6875 states and 15723 transitions. [2018-11-23 06:10:33,962 INFO L78 Accepts]: Start accepts. Automaton has 6875 states and 15723 transitions. Word has length 94 [2018-11-23 06:10:33,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:33,962 INFO L480 AbstractCegarLoop]: Abstraction has 6875 states and 15723 transitions. [2018-11-23 06:10:33,962 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 06:10:33,962 INFO L276 IsEmpty]: Start isEmpty. Operand 6875 states and 15723 transitions. [2018-11-23 06:10:33,972 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 06:10:33,972 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:33,972 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:33,974 INFO L423 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:33,974 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:33,974 INFO L82 PathProgramCache]: Analyzing trace with hash 376507970, now seen corresponding path program 1 times [2018-11-23 06:10:33,974 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:33,974 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:33,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:33,975 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:33,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:33,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:34,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:34,039 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:34,039 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 06:10:34,039 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 06:10:34,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 06:10:34,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 06:10:34,040 INFO L87 Difference]: Start difference. First operand 6875 states and 15723 transitions. Second operand 5 states. [2018-11-23 06:10:34,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:34,237 INFO L93 Difference]: Finished difference Result 8123 states and 18363 transitions. [2018-11-23 06:10:34,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 06:10:34,237 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 94 [2018-11-23 06:10:34,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:34,243 INFO L225 Difference]: With dead ends: 8123 [2018-11-23 06:10:34,244 INFO L226 Difference]: Without dead ends: 7992 [2018-11-23 06:10:34,244 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:34,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7992 states. [2018-11-23 06:10:34,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7992 to 7614. [2018-11-23 06:10:34,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7614 states. [2018-11-23 06:10:34,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7614 states to 7614 states and 17342 transitions. [2018-11-23 06:10:34,303 INFO L78 Accepts]: Start accepts. Automaton has 7614 states and 17342 transitions. Word has length 94 [2018-11-23 06:10:34,303 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:34,303 INFO L480 AbstractCegarLoop]: Abstraction has 7614 states and 17342 transitions. [2018-11-23 06:10:34,303 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 06:10:34,303 INFO L276 IsEmpty]: Start isEmpty. Operand 7614 states and 17342 transitions. [2018-11-23 06:10:34,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 06:10:34,308 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:34,308 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:34,308 INFO L423 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:34,308 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:34,308 INFO L82 PathProgramCache]: Analyzing trace with hash 1621272451, now seen corresponding path program 1 times [2018-11-23 06:10:34,309 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:34,309 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:34,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:34,310 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:34,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:34,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:34,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:34,390 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:34,390 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 06:10:34,391 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 06:10:34,391 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 06:10:34,391 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 06:10:34,391 INFO L87 Difference]: Start difference. First operand 7614 states and 17342 transitions. Second operand 6 states. [2018-11-23 06:10:34,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:34,649 INFO L93 Difference]: Finished difference Result 9775 states and 22056 transitions. [2018-11-23 06:10:34,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 06:10:34,650 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 94 [2018-11-23 06:10:34,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:34,657 INFO L225 Difference]: With dead ends: 9775 [2018-11-23 06:10:34,657 INFO L226 Difference]: Without dead ends: 9667 [2018-11-23 06:10:34,657 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2018-11-23 06:10:34,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9667 states. [2018-11-23 06:10:34,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9667 to 7441. [2018-11-23 06:10:34,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7441 states. [2018-11-23 06:10:34,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7441 states to 7441 states and 16948 transitions. [2018-11-23 06:10:34,724 INFO L78 Accepts]: Start accepts. Automaton has 7441 states and 16948 transitions. Word has length 94 [2018-11-23 06:10:34,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:34,724 INFO L480 AbstractCegarLoop]: Abstraction has 7441 states and 16948 transitions. [2018-11-23 06:10:34,724 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 06:10:34,724 INFO L276 IsEmpty]: Start isEmpty. Operand 7441 states and 16948 transitions. [2018-11-23 06:10:34,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 06:10:34,730 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:34,730 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:34,730 INFO L423 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:34,730 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:34,730 INFO L82 PathProgramCache]: Analyzing trace with hash 383295530, now seen corresponding path program 1 times [2018-11-23 06:10:34,731 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:34,731 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:34,732 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:34,732 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:34,732 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:34,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:34,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:34,824 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:34,824 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-23 06:10:34,824 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 06:10:34,824 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 06:10:34,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2018-11-23 06:10:34,825 INFO L87 Difference]: Start difference. First operand 7441 states and 16948 transitions. Second operand 9 states. [2018-11-23 06:10:35,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:35,178 INFO L93 Difference]: Finished difference Result 10480 states and 23807 transitions. [2018-11-23 06:10:35,178 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-23 06:10:35,178 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 94 [2018-11-23 06:10:35,178 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:35,185 INFO L225 Difference]: With dead ends: 10480 [2018-11-23 06:10:35,185 INFO L226 Difference]: Without dead ends: 10448 [2018-11-23 06:10:35,186 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=245, Unknown=0, NotChecked=0, Total=306 [2018-11-23 06:10:35,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10448 states. [2018-11-23 06:10:35,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10448 to 9009. [2018-11-23 06:10:35,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9009 states. [2018-11-23 06:10:35,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9009 states to 9009 states and 20408 transitions. [2018-11-23 06:10:35,265 INFO L78 Accepts]: Start accepts. Automaton has 9009 states and 20408 transitions. Word has length 94 [2018-11-23 06:10:35,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:35,265 INFO L480 AbstractCegarLoop]: Abstraction has 9009 states and 20408 transitions. [2018-11-23 06:10:35,265 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 06:10:35,265 INFO L276 IsEmpty]: Start isEmpty. Operand 9009 states and 20408 transitions. [2018-11-23 06:10:35,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 06:10:35,271 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:35,271 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:35,272 INFO L423 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:35,272 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:35,272 INFO L82 PathProgramCache]: Analyzing trace with hash -1413655829, now seen corresponding path program 1 times [2018-11-23 06:10:35,272 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:35,272 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:35,273 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:35,273 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:35,273 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:35,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:35,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:35,373 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:35,374 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 06:10:35,374 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 06:10:35,374 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 06:10:35,374 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-11-23 06:10:35,374 INFO L87 Difference]: Start difference. First operand 9009 states and 20408 transitions. Second operand 8 states. [2018-11-23 06:10:35,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:35,616 INFO L93 Difference]: Finished difference Result 14006 states and 32226 transitions. [2018-11-23 06:10:35,616 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 06:10:35,617 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 94 [2018-11-23 06:10:35,617 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:35,626 INFO L225 Difference]: With dead ends: 14006 [2018-11-23 06:10:35,626 INFO L226 Difference]: Without dead ends: 14006 [2018-11-23 06:10:35,626 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2018-11-23 06:10:35,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14006 states. [2018-11-23 06:10:35,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14006 to 9587. [2018-11-23 06:10:35,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9587 states. [2018-11-23 06:10:35,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9587 states to 9587 states and 21909 transitions. [2018-11-23 06:10:35,721 INFO L78 Accepts]: Start accepts. Automaton has 9587 states and 21909 transitions. Word has length 94 [2018-11-23 06:10:35,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:35,722 INFO L480 AbstractCegarLoop]: Abstraction has 9587 states and 21909 transitions. [2018-11-23 06:10:35,722 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 06:10:35,722 INFO L276 IsEmpty]: Start isEmpty. Operand 9587 states and 21909 transitions. [2018-11-23 06:10:35,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 06:10:35,728 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:35,729 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:35,729 INFO L423 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:35,729 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:35,729 INFO L82 PathProgramCache]: Analyzing trace with hash -526152148, now seen corresponding path program 1 times [2018-11-23 06:10:35,729 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:35,729 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:35,730 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:35,730 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:35,730 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:35,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:35,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:35,779 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:35,779 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 06:10:35,779 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 06:10:35,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 06:10:35,779 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 06:10:35,779 INFO L87 Difference]: Start difference. First operand 9587 states and 21909 transitions. Second operand 3 states. [2018-11-23 06:10:35,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:35,803 INFO L93 Difference]: Finished difference Result 9331 states and 21109 transitions. [2018-11-23 06:10:35,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 06:10:35,803 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 94 [2018-11-23 06:10:35,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:35,810 INFO L225 Difference]: With dead ends: 9331 [2018-11-23 06:10:35,810 INFO L226 Difference]: Without dead ends: 9299 [2018-11-23 06:10:35,810 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 06:10:35,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9299 states. [2018-11-23 06:10:35,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9299 to 7512. [2018-11-23 06:10:35,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7512 states. [2018-11-23 06:10:35,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7512 states to 7512 states and 16864 transitions. [2018-11-23 06:10:35,876 INFO L78 Accepts]: Start accepts. Automaton has 7512 states and 16864 transitions. Word has length 94 [2018-11-23 06:10:35,876 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:35,876 INFO L480 AbstractCegarLoop]: Abstraction has 7512 states and 16864 transitions. [2018-11-23 06:10:35,876 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 06:10:35,876 INFO L276 IsEmpty]: Start isEmpty. Operand 7512 states and 16864 transitions. [2018-11-23 06:10:35,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:35,882 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:35,882 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:35,882 INFO L423 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:35,882 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:35,883 INFO L82 PathProgramCache]: Analyzing trace with hash -1587470612, now seen corresponding path program 1 times [2018-11-23 06:10:35,883 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:35,883 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:35,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:35,884 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:35,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:35,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:35,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:35,996 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:35,997 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-23 06:10:35,997 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 06:10:35,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 06:10:35,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-11-23 06:10:35,997 INFO L87 Difference]: Start difference. First operand 7512 states and 16864 transitions. Second operand 9 states. [2018-11-23 06:10:36,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:36,325 INFO L93 Difference]: Finished difference Result 9618 states and 21293 transitions. [2018-11-23 06:10:36,325 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-23 06:10:36,326 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 96 [2018-11-23 06:10:36,326 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:36,332 INFO L225 Difference]: With dead ends: 9618 [2018-11-23 06:10:36,332 INFO L226 Difference]: Without dead ends: 9618 [2018-11-23 06:10:36,332 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 3 SyntacticMatches, 5 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 54 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=100, Invalid=320, Unknown=0, NotChecked=0, Total=420 [2018-11-23 06:10:36,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9618 states. [2018-11-23 06:10:36,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9618 to 8157. [2018-11-23 06:10:36,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8157 states. [2018-11-23 06:10:36,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8157 states to 8157 states and 18196 transitions. [2018-11-23 06:10:36,400 INFO L78 Accepts]: Start accepts. Automaton has 8157 states and 18196 transitions. Word has length 96 [2018-11-23 06:10:36,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:36,400 INFO L480 AbstractCegarLoop]: Abstraction has 8157 states and 18196 transitions. [2018-11-23 06:10:36,400 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 06:10:36,400 INFO L276 IsEmpty]: Start isEmpty. Operand 8157 states and 18196 transitions. [2018-11-23 06:10:36,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:36,405 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:36,405 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:36,405 INFO L423 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:36,406 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:36,406 INFO L82 PathProgramCache]: Analyzing trace with hash -1376119699, now seen corresponding path program 1 times [2018-11-23 06:10:36,406 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:36,406 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:36,407 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:36,407 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:36,407 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:36,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:36,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:36,535 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:36,536 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-11-23 06:10:36,536 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 06:10:36,536 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 06:10:36,536 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2018-11-23 06:10:36,536 INFO L87 Difference]: Start difference. First operand 8157 states and 18196 transitions. Second operand 13 states. [2018-11-23 06:10:37,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:37,131 INFO L93 Difference]: Finished difference Result 11618 states and 25550 transitions. [2018-11-23 06:10:37,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-23 06:10:37,131 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 96 [2018-11-23 06:10:37,132 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:37,139 INFO L225 Difference]: With dead ends: 11618 [2018-11-23 06:10:37,139 INFO L226 Difference]: Without dead ends: 11618 [2018-11-23 06:10:37,139 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 7 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 155 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=155, Invalid=715, Unknown=0, NotChecked=0, Total=870 [2018-11-23 06:10:37,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11618 states. [2018-11-23 06:10:37,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11618 to 8808. [2018-11-23 06:10:37,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8808 states. [2018-11-23 06:10:37,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8808 states to 8808 states and 19682 transitions. [2018-11-23 06:10:37,219 INFO L78 Accepts]: Start accepts. Automaton has 8808 states and 19682 transitions. Word has length 96 [2018-11-23 06:10:37,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:37,219 INFO L480 AbstractCegarLoop]: Abstraction has 8808 states and 19682 transitions. [2018-11-23 06:10:37,219 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 06:10:37,219 INFO L276 IsEmpty]: Start isEmpty. Operand 8808 states and 19682 transitions. [2018-11-23 06:10:37,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:37,226 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:37,226 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:37,226 INFO L423 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:37,227 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:37,227 INFO L82 PathProgramCache]: Analyzing trace with hash -488616018, now seen corresponding path program 1 times [2018-11-23 06:10:37,227 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:37,227 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:37,228 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:37,228 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:37,228 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:37,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:37,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:37,353 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:37,353 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-11-23 06:10:37,354 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 06:10:37,354 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 06:10:37,354 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-11-23 06:10:37,354 INFO L87 Difference]: Start difference. First operand 8808 states and 19682 transitions. Second operand 11 states. [2018-11-23 06:10:38,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:38,157 INFO L93 Difference]: Finished difference Result 16128 states and 36229 transitions. [2018-11-23 06:10:38,157 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 06:10:38,157 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 96 [2018-11-23 06:10:38,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:38,165 INFO L225 Difference]: With dead ends: 16128 [2018-11-23 06:10:38,165 INFO L226 Difference]: Without dead ends: 11177 [2018-11-23 06:10:38,165 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=86, Invalid=376, Unknown=0, NotChecked=0, Total=462 [2018-11-23 06:10:38,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11177 states. [2018-11-23 06:10:38,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11177 to 8540. [2018-11-23 06:10:38,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8540 states. [2018-11-23 06:10:38,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8540 states to 8540 states and 19067 transitions. [2018-11-23 06:10:38,237 INFO L78 Accepts]: Start accepts. Automaton has 8540 states and 19067 transitions. Word has length 96 [2018-11-23 06:10:38,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:38,237 INFO L480 AbstractCegarLoop]: Abstraction has 8540 states and 19067 transitions. [2018-11-23 06:10:38,237 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 06:10:38,238 INFO L276 IsEmpty]: Start isEmpty. Operand 8540 states and 19067 transitions. [2018-11-23 06:10:38,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:38,243 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:38,243 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:38,243 INFO L423 AbstractCegarLoop]: === Iteration 35 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:38,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:38,243 INFO L82 PathProgramCache]: Analyzing trace with hash 537589784, now seen corresponding path program 1 times [2018-11-23 06:10:38,243 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:38,243 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:38,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:38,245 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:38,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:38,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:38,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:38,331 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:38,331 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 06:10:38,331 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 06:10:38,331 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 06:10:38,331 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 06:10:38,331 INFO L87 Difference]: Start difference. First operand 8540 states and 19067 transitions. Second operand 6 states. [2018-11-23 06:10:38,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:38,501 INFO L93 Difference]: Finished difference Result 7622 states and 16741 transitions. [2018-11-23 06:10:38,501 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 06:10:38,501 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 96 [2018-11-23 06:10:38,501 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:38,506 INFO L225 Difference]: With dead ends: 7622 [2018-11-23 06:10:38,506 INFO L226 Difference]: Without dead ends: 7622 [2018-11-23 06:10:38,506 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:38,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7622 states. [2018-11-23 06:10:38,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7622 to 7143. [2018-11-23 06:10:38,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7143 states. [2018-11-23 06:10:38,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7143 states to 7143 states and 15734 transitions. [2018-11-23 06:10:38,563 INFO L78 Accepts]: Start accepts. Automaton has 7143 states and 15734 transitions. Word has length 96 [2018-11-23 06:10:38,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:38,563 INFO L480 AbstractCegarLoop]: Abstraction has 7143 states and 15734 transitions. [2018-11-23 06:10:38,563 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 06:10:38,563 INFO L276 IsEmpty]: Start isEmpty. Operand 7143 states and 15734 transitions. [2018-11-23 06:10:38,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:38,569 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:38,569 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:38,569 INFO L423 AbstractCegarLoop]: === Iteration 36 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:38,569 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:38,569 INFO L82 PathProgramCache]: Analyzing trace with hash -1552227223, now seen corresponding path program 1 times [2018-11-23 06:10:38,569 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:38,569 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:38,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:38,570 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:38,571 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:38,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:38,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:38,676 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:38,676 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 06:10:38,677 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 06:10:38,677 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 06:10:38,677 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:38,677 INFO L87 Difference]: Start difference. First operand 7143 states and 15734 transitions. Second operand 7 states. [2018-11-23 06:10:38,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:38,886 INFO L93 Difference]: Finished difference Result 9361 states and 20510 transitions. [2018-11-23 06:10:38,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-23 06:10:38,887 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 96 [2018-11-23 06:10:38,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:38,893 INFO L225 Difference]: With dead ends: 9361 [2018-11-23 06:10:38,893 INFO L226 Difference]: Without dead ends: 9337 [2018-11-23 06:10:38,893 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2018-11-23 06:10:38,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9337 states. [2018-11-23 06:10:38,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9337 to 7491. [2018-11-23 06:10:38,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7491 states. [2018-11-23 06:10:38,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7491 states to 7491 states and 16504 transitions. [2018-11-23 06:10:38,955 INFO L78 Accepts]: Start accepts. Automaton has 7491 states and 16504 transitions. Word has length 96 [2018-11-23 06:10:38,955 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:38,955 INFO L480 AbstractCegarLoop]: Abstraction has 7491 states and 16504 transitions. [2018-11-23 06:10:38,955 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 06:10:38,955 INFO L276 IsEmpty]: Start isEmpty. Operand 7491 states and 16504 transitions. [2018-11-23 06:10:38,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:38,961 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:38,961 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:38,961 INFO L423 AbstractCegarLoop]: === Iteration 37 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:38,961 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:38,961 INFO L82 PathProgramCache]: Analyzing trace with hash -2066816054, now seen corresponding path program 2 times [2018-11-23 06:10:38,961 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:38,961 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:38,962 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:38,962 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:38,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:38,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:39,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:39,039 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:39,040 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 06:10:39,040 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 06:10:39,040 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 06:10:39,040 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:39,040 INFO L87 Difference]: Start difference. First operand 7491 states and 16504 transitions. Second operand 7 states. [2018-11-23 06:10:39,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:39,236 INFO L93 Difference]: Finished difference Result 8688 states and 19201 transitions. [2018-11-23 06:10:39,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 06:10:39,236 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 96 [2018-11-23 06:10:39,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:39,241 INFO L225 Difference]: With dead ends: 8688 [2018-11-23 06:10:39,241 INFO L226 Difference]: Without dead ends: 8688 [2018-11-23 06:10:39,242 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2018-11-23 06:10:39,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8688 states. [2018-11-23 06:10:39,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8688 to 7708. [2018-11-23 06:10:39,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7708 states. [2018-11-23 06:10:39,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7708 states to 7708 states and 16946 transitions. [2018-11-23 06:10:39,301 INFO L78 Accepts]: Start accepts. Automaton has 7708 states and 16946 transitions. Word has length 96 [2018-11-23 06:10:39,302 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:39,302 INFO L480 AbstractCegarLoop]: Abstraction has 7708 states and 16946 transitions. [2018-11-23 06:10:39,302 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 06:10:39,302 INFO L276 IsEmpty]: Start isEmpty. Operand 7708 states and 16946 transitions. [2018-11-23 06:10:39,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:39,307 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:39,308 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:39,308 INFO L423 AbstractCegarLoop]: === Iteration 38 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:39,308 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:39,308 INFO L82 PathProgramCache]: Analyzing trace with hash 1184419848, now seen corresponding path program 1 times [2018-11-23 06:10:39,308 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:39,308 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:39,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:39,309 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 06:10:39,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:39,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:39,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:39,370 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:39,370 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 06:10:39,370 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 06:10:39,370 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 06:10:39,370 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-23 06:10:39,370 INFO L87 Difference]: Start difference. First operand 7708 states and 16946 transitions. Second operand 6 states. [2018-11-23 06:10:39,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:39,654 INFO L93 Difference]: Finished difference Result 10649 states and 23221 transitions. [2018-11-23 06:10:39,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 06:10:39,654 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 96 [2018-11-23 06:10:39,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:39,661 INFO L225 Difference]: With dead ends: 10649 [2018-11-23 06:10:39,661 INFO L226 Difference]: Without dead ends: 10487 [2018-11-23 06:10:39,661 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=34, Invalid=56, Unknown=0, NotChecked=0, Total=90 [2018-11-23 06:10:39,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10487 states. [2018-11-23 06:10:39,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10487 to 8465. [2018-11-23 06:10:39,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8465 states. [2018-11-23 06:10:39,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8465 states to 8465 states and 18676 transitions. [2018-11-23 06:10:39,730 INFO L78 Accepts]: Start accepts. Automaton has 8465 states and 18676 transitions. Word has length 96 [2018-11-23 06:10:39,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:39,731 INFO L480 AbstractCegarLoop]: Abstraction has 8465 states and 18676 transitions. [2018-11-23 06:10:39,731 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 06:10:39,731 INFO L276 IsEmpty]: Start isEmpty. Operand 8465 states and 18676 transitions. [2018-11-23 06:10:39,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:39,737 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:39,737 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:39,737 INFO L423 AbstractCegarLoop]: === Iteration 39 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:39,738 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:39,738 INFO L82 PathProgramCache]: Analyzing trace with hash 1395770761, now seen corresponding path program 1 times [2018-11-23 06:10:39,738 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:39,738 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:39,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:39,739 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:39,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:39,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:39,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:39,811 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:39,811 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 06:10:39,811 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 06:10:39,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 06:10:39,812 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 06:10:39,812 INFO L87 Difference]: Start difference. First operand 8465 states and 18676 transitions. Second operand 6 states. [2018-11-23 06:10:40,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:40,047 INFO L93 Difference]: Finished difference Result 9364 states and 20420 transitions. [2018-11-23 06:10:40,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 06:10:40,047 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 96 [2018-11-23 06:10:40,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:40,054 INFO L225 Difference]: With dead ends: 9364 [2018-11-23 06:10:40,054 INFO L226 Difference]: Without dead ends: 9257 [2018-11-23 06:10:40,054 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 06:10:40,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9257 states. [2018-11-23 06:10:40,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9257 to 8391. [2018-11-23 06:10:40,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8391 states. [2018-11-23 06:10:40,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8391 states to 8391 states and 18414 transitions. [2018-11-23 06:10:40,120 INFO L78 Accepts]: Start accepts. Automaton has 8391 states and 18414 transitions. Word has length 96 [2018-11-23 06:10:40,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:40,120 INFO L480 AbstractCegarLoop]: Abstraction has 8391 states and 18414 transitions. [2018-11-23 06:10:40,120 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 06:10:40,121 INFO L276 IsEmpty]: Start isEmpty. Operand 8391 states and 18414 transitions. [2018-11-23 06:10:40,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:40,127 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:40,127 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:40,127 INFO L423 AbstractCegarLoop]: === Iteration 40 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:40,127 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:40,127 INFO L82 PathProgramCache]: Analyzing trace with hash 1877521545, now seen corresponding path program 1 times [2018-11-23 06:10:40,127 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:40,128 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:40,128 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:40,129 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:40,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:40,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:40,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:40,274 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:40,274 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-23 06:10:40,274 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 06:10:40,274 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 06:10:40,274 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2018-11-23 06:10:40,274 INFO L87 Difference]: Start difference. First operand 8391 states and 18414 transitions. Second operand 9 states. [2018-11-23 06:10:40,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:40,576 INFO L93 Difference]: Finished difference Result 10294 states and 22323 transitions. [2018-11-23 06:10:40,576 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 06:10:40,576 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 96 [2018-11-23 06:10:40,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:40,583 INFO L225 Difference]: With dead ends: 10294 [2018-11-23 06:10:40,583 INFO L226 Difference]: Without dead ends: 10294 [2018-11-23 06:10:40,583 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=99, Unknown=0, NotChecked=0, Total=156 [2018-11-23 06:10:40,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10294 states. [2018-11-23 06:10:40,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10294 to 8718. [2018-11-23 06:10:40,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8718 states. [2018-11-23 06:10:40,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8718 states to 8718 states and 19083 transitions. [2018-11-23 06:10:40,655 INFO L78 Accepts]: Start accepts. Automaton has 8718 states and 19083 transitions. Word has length 96 [2018-11-23 06:10:40,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:40,656 INFO L480 AbstractCegarLoop]: Abstraction has 8718 states and 19083 transitions. [2018-11-23 06:10:40,656 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 06:10:40,656 INFO L276 IsEmpty]: Start isEmpty. Operand 8718 states and 19083 transitions. [2018-11-23 06:10:40,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:40,663 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:40,663 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:40,663 INFO L423 AbstractCegarLoop]: === Iteration 41 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:40,663 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:40,663 INFO L82 PathProgramCache]: Analyzing trace with hash 827237257, now seen corresponding path program 1 times [2018-11-23 06:10:40,664 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:40,664 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:40,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:40,665 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:40,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:40,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:40,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:40,758 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:40,758 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 06:10:40,758 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 06:10:40,758 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 06:10:40,758 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-11-23 06:10:40,759 INFO L87 Difference]: Start difference. First operand 8718 states and 19083 transitions. Second operand 8 states. [2018-11-23 06:10:41,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:41,192 INFO L93 Difference]: Finished difference Result 11773 states and 25703 transitions. [2018-11-23 06:10:41,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 06:10:41,192 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 96 [2018-11-23 06:10:41,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:41,200 INFO L225 Difference]: With dead ends: 11773 [2018-11-23 06:10:41,200 INFO L226 Difference]: Without dead ends: 11705 [2018-11-23 06:10:41,200 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=59, Invalid=181, Unknown=0, NotChecked=0, Total=240 [2018-11-23 06:10:41,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11705 states. [2018-11-23 06:10:41,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11705 to 8959. [2018-11-23 06:10:41,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8959 states. [2018-11-23 06:10:41,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8959 states to 8959 states and 19610 transitions. [2018-11-23 06:10:41,282 INFO L78 Accepts]: Start accepts. Automaton has 8959 states and 19610 transitions. Word has length 96 [2018-11-23 06:10:41,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:41,282 INFO L480 AbstractCegarLoop]: Abstraction has 8959 states and 19610 transitions. [2018-11-23 06:10:41,282 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 06:10:41,282 INFO L276 IsEmpty]: Start isEmpty. Operand 8959 states and 19610 transitions. [2018-11-23 06:10:41,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:41,289 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:41,289 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:41,289 INFO L423 AbstractCegarLoop]: === Iteration 42 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:41,290 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:41,290 INFO L82 PathProgramCache]: Analyzing trace with hash -1249972086, now seen corresponding path program 2 times [2018-11-23 06:10:41,290 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:41,290 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:41,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:41,291 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 06:10:41,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:41,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:41,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:41,345 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:41,345 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 06:10:41,346 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 06:10:41,346 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 06:10:41,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:41,346 INFO L87 Difference]: Start difference. First operand 8959 states and 19610 transitions. Second operand 7 states. [2018-11-23 06:10:41,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:41,452 INFO L93 Difference]: Finished difference Result 11470 states and 25260 transitions. [2018-11-23 06:10:41,452 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 06:10:41,452 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 96 [2018-11-23 06:10:41,453 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:41,459 INFO L225 Difference]: With dead ends: 11470 [2018-11-23 06:10:41,460 INFO L226 Difference]: Without dead ends: 11470 [2018-11-23 06:10:41,460 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-11-23 06:10:41,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11470 states. [2018-11-23 06:10:41,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11470 to 7965. [2018-11-23 06:10:41,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7965 states. [2018-11-23 06:10:41,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7965 states to 7965 states and 17356 transitions. [2018-11-23 06:10:41,531 INFO L78 Accepts]: Start accepts. Automaton has 7965 states and 17356 transitions. Word has length 96 [2018-11-23 06:10:41,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:41,532 INFO L480 AbstractCegarLoop]: Abstraction has 7965 states and 17356 transitions. [2018-11-23 06:10:41,532 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 06:10:41,532 INFO L276 IsEmpty]: Start isEmpty. Operand 7965 states and 17356 transitions. [2018-11-23 06:10:41,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:41,537 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:41,537 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:41,538 INFO L423 AbstractCegarLoop]: === Iteration 43 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:41,538 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:41,538 INFO L82 PathProgramCache]: Analyzing trace with hash 578485643, now seen corresponding path program 2 times [2018-11-23 06:10:41,538 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:41,538 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:41,539 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:41,539 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 06:10:41,539 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:41,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 06:10:41,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 06:10:41,625 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 06:10:41,625 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 06:10:41,625 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 06:10:41,625 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 06:10:41,625 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-23 06:10:41,625 INFO L87 Difference]: Start difference. First operand 7965 states and 17356 transitions. Second operand 7 states. [2018-11-23 06:10:41,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 06:10:41,743 INFO L93 Difference]: Finished difference Result 9121 states and 19852 transitions. [2018-11-23 06:10:41,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 06:10:41,743 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 96 [2018-11-23 06:10:41,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 06:10:41,749 INFO L225 Difference]: With dead ends: 9121 [2018-11-23 06:10:41,749 INFO L226 Difference]: Without dead ends: 9121 [2018-11-23 06:10:41,749 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=72, Unknown=0, NotChecked=0, Total=110 [2018-11-23 06:10:41,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9121 states. [2018-11-23 06:10:41,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9121 to 6675. [2018-11-23 06:10:41,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6675 states. [2018-11-23 06:10:41,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6675 states to 6675 states and 14518 transitions. [2018-11-23 06:10:41,818 INFO L78 Accepts]: Start accepts. Automaton has 6675 states and 14518 transitions. Word has length 96 [2018-11-23 06:10:41,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 06:10:41,819 INFO L480 AbstractCegarLoop]: Abstraction has 6675 states and 14518 transitions. [2018-11-23 06:10:41,819 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 06:10:41,819 INFO L276 IsEmpty]: Start isEmpty. Operand 6675 states and 14518 transitions. [2018-11-23 06:10:41,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 06:10:41,823 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 06:10:41,823 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 06:10:41,823 INFO L423 AbstractCegarLoop]: === Iteration 44 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 06:10:41,823 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 06:10:41,823 INFO L82 PathProgramCache]: Analyzing trace with hash 1465989324, now seen corresponding path program 2 times [2018-11-23 06:10:41,823 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 06:10:41,824 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 06:10:41,824 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:41,825 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 06:10:41,825 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 06:10:41,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 06:10:41,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 06:10:41,871 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [479] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [362] L-1-->L671: Formula: (= |v_#valid_9| (store |v_#valid_10| 0 0)) InVars {#valid=|v_#valid_10|} OutVars{#valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [518] L671-->L673: Formula: (= v_~__unbuffered_cnt~0_6 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [386] L673-->L675: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [435] L675-->L676: Formula: (= v_~__unbuffered_p1_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 [351] L676-->L677: Formula: (= v_~main$tmp_guard0~0_3 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 [488] L677-->L679: Formula: (= v_~main$tmp_guard1~0_1 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_1} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [527] L679-->L680: Formula: (= v_~x~0_11 0) InVars {} OutVars{~x~0=v_~x~0_11} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [462] L680-->L681: Formula: (= v_~x$flush_delayed~0_5 0) InVars {} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_5} AuxVars[] AssignedVars[~x$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 [393] L681-->L682: Formula: (= v_~x$mem_tmp~0_3 0) InVars {} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_3} AuxVars[] AssignedVars[~x$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 [517] L682-->L683: Formula: (= v_~x$r_buff0_thd0~0_2 0) InVars {} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_2} AuxVars[] AssignedVars[~x$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 [455] L683-->L684: Formula: (= v_~x$r_buff0_thd1~0_14 0) InVars {} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_14} AuxVars[] AssignedVars[~x$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 [385] L684-->L685: Formula: (= v_~x$r_buff0_thd2~0_43 0) InVars {} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_43} AuxVars[] AssignedVars[~x$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 [497] L685-->L686: Formula: (= v_~x$r_buff1_thd0~0_2 0) InVars {} OutVars{~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_2} AuxVars[] AssignedVars[~x$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 [432] L686-->L687: Formula: (= v_~x$r_buff1_thd1~0_9 0) InVars {} OutVars{~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 [378] L687-->L688: Formula: (= v_~x$r_buff1_thd2~0_25 0) InVars {} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_25} AuxVars[] AssignedVars[~x$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 [487] L688-->L689: Formula: (= v_~x$read_delayed~0_1 0) InVars {} OutVars{~x$read_delayed~0=v_~x$read_delayed~0_1} AuxVars[] AssignedVars[~x$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [426] L689-->L690: Formula: (and (= v_~x$read_delayed_var~0.offset_1 0) (= v_~x$read_delayed_var~0.base_1 0)) InVars {} OutVars{~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_1, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~x$read_delayed_var~0.offset, ~x$read_delayed_var~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [524] L690-->L691: Formula: (= v_~x$w_buff0~0_11 0) InVars {} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_11} AuxVars[] AssignedVars[~x$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [461] L691-->L692: Formula: (= v_~x$w_buff0_used~0_55 0) InVars {} OutVars{~x$w_buff0_used~0=v_~x$w_buff0_used~0_55} AuxVars[] AssignedVars[~x$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [392] L692-->L693: Formula: (= v_~x$w_buff1~0_10 0) InVars {} OutVars{~x$w_buff1~0=v_~x$w_buff1~0_10} AuxVars[] AssignedVars[~x$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [515] L693-->L695: Formula: (= v_~x$w_buff1_used~0_32 0) InVars {} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_32} AuxVars[] AssignedVars[~x$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [384] L695-->L697: Formula: (= v_~y~0_3 0) InVars {} OutVars{~y~0=v_~y~0_3} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [431] L697-->L698: Formula: (= v_~z~0_2 0) InVars {} OutVars{~z~0=v_~z~0_2} AuxVars[] AssignedVars[~z~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [375] L698-->L699: Formula: (= v_~weak$$choice0~0_2 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [486] L699-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [516] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [514] L-1-2-->L778: Formula: true InVars {} OutVars{ULTIMATE.start_main_~#t1612~0.base=|v_ULTIMATE.start_main_~#t1612~0.base_1|, ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_1|, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_1|, ULTIMATE.start_main_~#t1611~0.offset=|v_ULTIMATE.start_main_~#t1611~0.offset_1|, ULTIMATE.start_main_~#t1612~0.offset=|v_ULTIMATE.start_main_~#t1612~0.offset_1|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_1|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_1|, ULTIMATE.start_main_~#t1611~0.base=|v_ULTIMATE.start_main_~#t1611~0.base_1|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_1|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_1|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_1|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1612~0.base, ULTIMATE.start_main_#t~nondet40, ULTIMATE.start_main_#t~nondet41, ULTIMATE.start_main_~#t1611~0.offset, ULTIMATE.start_main_~#t1612~0.offset, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_~#t1611~0.base, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [361] L778-->L778-1: Formula: (and (= |v_#length_1| (store |v_#length_2| |v_ULTIMATE.start_main_~#t1611~0.base_2| 4)) (not (= 0 |v_ULTIMATE.start_main_~#t1611~0.base_2|)) (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t1611~0.base_2| 1) |v_#valid_1|) (= 0 (select |v_#valid_2| |v_ULTIMATE.start_main_~#t1611~0.base_2|)) (= |v_ULTIMATE.start_main_~#t1611~0.offset_2| 0)) InVars {#length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{ULTIMATE.start_main_~#t1611~0.base=|v_ULTIMATE.start_main_~#t1611~0.base_2|, #length=|v_#length_1|, ULTIMATE.start_main_~#t1611~0.offset=|v_ULTIMATE.start_main_~#t1611~0.offset_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1611~0.offset, #valid, ULTIMATE.start_main_~#t1611~0.base, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [521] L778-1-->L779: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1611~0.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1611~0.base_3|) |v_ULTIMATE.start_main_~#t1611~0.offset_3| 0))) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t1611~0.base=|v_ULTIMATE.start_main_~#t1611~0.base_3|, ULTIMATE.start_main_~#t1611~0.offset=|v_ULTIMATE.start_main_~#t1611~0.offset_3|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t1611~0.base=|v_ULTIMATE.start_main_~#t1611~0.base_3|, ULTIMATE.start_main_~#t1611~0.offset=|v_ULTIMATE.start_main_~#t1611~0.offset_3|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 [644] L779-->P0ENTRY: Formula: (and (= 0 |v_Thread0_P0_#in~arg.offset_3|) (= 0 v_Thread0_P0_thidvar0_2) (= 0 |v_Thread0_P0_#in~arg.base_3|)) InVars {} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_3|, Thread0_P0_thidvar0=v_Thread0_P0_thidvar0_2, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P0_#in~arg.base, Thread0_P0_thidvar0, Thread0_P0_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 [532] P0ENTRY-->L4: Formula: (and (= v_Thread0_P0_~arg.base_1 |v_Thread0_P0_#in~arg.base_1|) (= v_Thread0_P0_~arg.offset_1 |v_Thread0_P0_#in~arg.offset_1|) (= v_~x$w_buff0~0_1 1) (= v_Thread0_P0___VERIFIER_assert_~expression_1 |v_Thread0_P0___VERIFIER_assert_#in~expression_1|) (= v_~x$w_buff1~0_1 v_~x$w_buff0~0_2) (= v_~x$w_buff1_used~0_1 v_~x$w_buff0_used~0_2) (= v_~x$w_buff0_used~0_1 1) (= |v_Thread0_P0___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~x$w_buff1_used~0_1 256))) (not (= (mod v_~x$w_buff0_used~0_1 256) 0)))) 1 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_2, Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_2} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_1, Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_1, Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_~arg.offset=v_Thread0_P0_~arg.offset_1, ~x$w_buff1~0=v_~x$w_buff1~0_1, Thread0_P0_~arg.base=v_Thread0_P0_~arg.base_1, Thread0_P0___VERIFIER_assert_#in~expression=|v_Thread0_P0___VERIFIER_assert_#in~expression_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_1, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1} AuxVars[] AssignedVars[~x$w_buff0~0, Thread0_P0___VERIFIER_assert_~expression, Thread0_P0_~arg.offset, ~x$w_buff1~0, Thread0_P0_~arg.base, Thread0_P0___VERIFIER_assert_#in~expression, ~x$w_buff1_used~0, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 [534] L4-->L4-3: Formula: (not (= 0 v_Thread0_P0___VERIFIER_assert_~expression_3)) InVars {Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_3} OutVars{Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 [537] L4-3-->L717: Formula: (and (= v_~x$r_buff0_thd1~0_1 1) (= v_~x$r_buff1_thd0~0_1 v_~x$r_buff0_thd0~0_1) (= v_~x$r_buff1_thd2~0_1 v_~x$r_buff0_thd2~0_1) (= v_~x$r_buff1_thd1~0_1 v_~x$r_buff0_thd1~0_2) (= v_~y~0_1 1)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_2, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_1, ~y~0=v_~y~0_1, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_1} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, ~x$r_buff1_thd2~0, ~x$r_buff1_thd1~0, ~y~0, ~x$r_buff1_thd0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] 0 [538] L717-->L717-5: Formula: (and (not (= 0 (mod v_~x$w_buff0_used~0_3 256))) (= |v_Thread0_P0_#t~ite4_1| v_~x$w_buff0~0_3) (not (= 0 (mod v_~x$r_buff0_thd1~0_3 256)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_3, Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} AuxVars[] AssignedVars[Thread0_P0_#t~ite4] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 [476] L779-1-->L780: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet40] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 [409] L780-->L780-1: Formula: (and (= 0 (select |v_#valid_4| |v_ULTIMATE.start_main_~#t1612~0.base_2|)) (= |v_#valid_3| (store |v_#valid_4| |v_ULTIMATE.start_main_~#t1612~0.base_2| 1)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t1612~0.base_2| 4)) (= |v_ULTIMATE.start_main_~#t1612~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_main_~#t1612~0.base_2|))) InVars {#length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{ULTIMATE.start_main_~#t1612~0.base=|v_ULTIMATE.start_main_~#t1612~0.base_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t1612~0.offset=|v_ULTIMATE.start_main_~#t1612~0.offset_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1612~0.base, ULTIMATE.start_main_~#t1612~0.offset, #valid, #length] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 [410] L780-1-->L781: Formula: (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1612~0.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1612~0.base_3|) |v_ULTIMATE.start_main_~#t1612~0.offset_3| 1)) |v_#memory_int_3|) InVars {ULTIMATE.start_main_~#t1612~0.base=|v_ULTIMATE.start_main_~#t1612~0.base_3|, #memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t1612~0.offset=|v_ULTIMATE.start_main_~#t1612~0.offset_3|} OutVars{ULTIMATE.start_main_~#t1612~0.base=|v_ULTIMATE.start_main_~#t1612~0.base_3|, #memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t1612~0.offset=|v_ULTIMATE.start_main_~#t1612~0.offset_3|} AuxVars[] AssignedVars[#memory_int] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] FORK -1 [645] L781-->P1ENTRY: Formula: (and (= 0 |v_Thread1_P1_#in~arg.base_3|) (= 0 |v_Thread1_P1_#in~arg.offset_3|) (= 1 v_Thread1_P1_thidvar0_2)) InVars {} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_3|, Thread1_P1_thidvar0=v_Thread1_P1_thidvar0_2, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_P1_#in~arg.base, Thread1_P1_thidvar0, Thread1_P1_#in~arg.offset] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] 1 [559] P1ENTRY-->L744: Formula: (and (= v_Thread1_P1_~arg.offset_1 |v_Thread1_P1_#in~arg.offset_1|) (= v_~z~0_1 1) (= v_Thread1_P1_~arg.base_1 |v_Thread1_P1_#in~arg.base_1|) (= v_~y~0_2 2) (= v_~x$flush_delayed~0_1 v_~weak$$choice2~0_7) (= v_~weak$$choice0~0_1 (ite (= 0 (+ |v_Thread1_P1_#t~nondet10.base_1| |v_Thread1_P1_#t~nondet10.offset_1|)) 0 1)) (= v_~__unbuffered_p1_EAX~0_1 v_~z~0_1) (= v_~x$mem_tmp~0_1 v_~x~0_3) (= v_~weak$$choice2~0_7 (ite (= (+ |v_Thread1_P1_#t~nondet11.offset_1| |v_Thread1_P1_#t~nondet11.base_1|) 0) 0 1))) InVars {Thread1_P1_#t~nondet10.offset=|v_Thread1_P1_#t~nondet10.offset_1|, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_#t~nondet10.base=|v_Thread1_P1_#t~nondet10.base_1|, Thread1_P1_#t~nondet11.base=|v_Thread1_P1_#t~nondet11.base_1|, Thread1_P1_#t~nondet11.offset=|v_Thread1_P1_#t~nondet11.offset_1|, ~x~0=v_~x~0_3, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_~arg.offset=v_Thread1_P1_~arg.offset_1, Thread1_P1_#t~nondet10.base=|v_Thread1_P1_#t~nondet10.base_2|, ~x$flush_delayed~0=v_~x$flush_delayed~0_1, ~x$mem_tmp~0=v_~x$mem_tmp~0_1, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, Thread1_P1_#t~nondet10.offset=|v_Thread1_P1_#t~nondet10.offset_2|, ~weak$$choice0~0=v_~weak$$choice0~0_1, Thread1_P1_~arg.base=v_Thread1_P1_~arg.base_1, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, Thread1_P1_#t~nondet11.base=|v_Thread1_P1_#t~nondet11.base_2|, ~z~0=v_~z~0_1, ~weak$$choice2~0=v_~weak$$choice2~0_7, ~y~0=v_~y~0_2, Thread1_P1_#t~nondet11.offset=|v_Thread1_P1_#t~nondet11.offset_2|, ~x~0=v_~x~0_3} AuxVars[] AssignedVars[Thread1_P1_~arg.offset, Thread1_P1_#t~nondet10.base, ~x$flush_delayed~0, ~x$mem_tmp~0, Thread1_P1_#t~nondet10.offset, ~weak$$choice0~0, Thread1_P1_~arg.base, ~__unbuffered_p1_EAX~0, Thread1_P1_#t~nondet11.base, ~z~0, ~weak$$choice2~0, ~y~0, Thread1_P1_#t~nondet11.offset] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [560] L744-->L744-5: Formula: (and (= |v_Thread1_P1_#t~ite13_1| v_~x~0_4) (let ((.cse0 (= (mod v_~x$r_buff0_thd2~0_15 256) 0))) (or (and .cse0 (= (mod v_~x$w_buff1_used~0_17 256) 0)) (= (mod v_~x$w_buff0_used~0_26 256) 0) (and (= 0 (mod v_~x$r_buff1_thd2~0_9 256)) .cse0)))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_17, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_9, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_15, ~x~0=v_~x~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_26} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_17, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_9, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_15, ~x~0=v_~x~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_26} AuxVars[] AssignedVars[Thread1_P1_#t~ite13] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite13|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [562] L744-5-->L745: Formula: (= v_~x~0_6 |v_Thread1_P1_#t~ite13_2|) InVars {Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_2|} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_1|, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_3|, ~x~0=v_~x~0_6} AuxVars[] AssignedVars[Thread1_P1_#t~ite12, Thread1_P1_#t~ite13, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [565] L745-->L745-8: Formula: (and (not (= (mod v_~weak$$choice2~0_8 256) 0)) (= |v_Thread1_P1_#t~ite16_1| v_~x$w_buff0~0_5)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_8} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_8, Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite16] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite16|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [568] L745-8-->L746: Formula: (= v_~x$w_buff0~0_10 |v_Thread1_P1_#t~ite16_2|) InVars {Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_2|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_10, Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_1|, Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_3|, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_1|} AuxVars[] AssignedVars[~x$w_buff0~0, Thread1_P1_#t~ite14, Thread1_P1_#t~ite16, Thread1_P1_#t~ite15] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [571] L746-->L746-8: Formula: (and (not (= (mod v_~weak$$choice2~0_10 256) 0)) (= |v_Thread1_P1_#t~ite19_1| v_~x$w_buff1~0_5)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_10, ~x$w_buff1~0=v_~x$w_buff1~0_5} OutVars{Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_1|, ~weak$$choice2~0=v_~weak$$choice2~0_10, ~x$w_buff1~0=v_~x$w_buff1~0_5} AuxVars[] AssignedVars[Thread1_P1_#t~ite19] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite19|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [576] L746-8-->L747: Formula: (= v_~x$w_buff1~0_9 |v_Thread1_P1_#t~ite19_2|) InVars {Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_2|} OutVars{Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_3|, Thread1_P1_#t~ite18=|v_Thread1_P1_#t~ite18_1|, ~x$w_buff1~0=v_~x$w_buff1~0_9, Thread1_P1_#t~ite17=|v_Thread1_P1_#t~ite17_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite19, ~x$w_buff1~0, Thread1_P1_#t~ite18, Thread1_P1_#t~ite17] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [580] L747-->L747-8: Formula: (and (not (= (mod v_~weak$$choice2~0_12 256) 0)) (= |v_Thread1_P1_#t~ite22_1| v_~x$w_buff0_used~0_50)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} OutVars{Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_1|, ~weak$$choice2~0=v_~weak$$choice2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} AuxVars[] AssignedVars[Thread1_P1_#t~ite22] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite22|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [585] L747-8-->L748: Formula: (= v_~x$w_buff0_used~0_15 |v_Thread1_P1_#t~ite22_2|) InVars {Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_2|} OutVars{Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_3|, Thread1_P1_#t~ite21=|v_Thread1_P1_#t~ite21_1|, Thread1_P1_#t~ite20=|v_Thread1_P1_#t~ite20_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_15} AuxVars[] AssignedVars[Thread1_P1_#t~ite21, Thread1_P1_#t~ite20, Thread1_P1_#t~ite22, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [589] L748-->L748-8: Formula: (and (= |v_Thread1_P1_#t~ite25_1| v_~x$w_buff1_used~0_9) (not (= (mod v_~weak$$choice2~0_1 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_1, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_9} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_9, Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_1|, ~weak$$choice2~0=v_~weak$$choice2~0_1} AuxVars[] AssignedVars[Thread1_P1_#t~ite25] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite25|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [594] L748-8-->L749: Formula: (= v_~x$w_buff1_used~0_12 |v_Thread1_P1_#t~ite25_2|) InVars {Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_2|} OutVars{Thread1_P1_#t~ite23=|v_Thread1_P1_#t~ite23_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_12, Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_3|, Thread1_P1_#t~ite24=|v_Thread1_P1_#t~ite24_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite23, ~x$w_buff1_used~0, Thread1_P1_#t~ite25, Thread1_P1_#t~ite24] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [598] L749-->L749-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_3 256))) (= |v_Thread1_P1_#t~ite28_1| v_~x$r_buff0_thd2~0_7)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_3} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_3, Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite28] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite28|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [603] L749-8-->L750: Formula: (= v_~x$r_buff0_thd2~0_12 |v_Thread1_P1_#t~ite28_2|) InVars {Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_2|} OutVars{Thread1_P1_#t~ite27=|v_Thread1_P1_#t~ite27_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_12, Thread1_P1_#t~ite26=|v_Thread1_P1_#t~ite26_1|, Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_3|} AuxVars[] AssignedVars[Thread1_P1_#t~ite27, ~x$r_buff0_thd2~0, Thread1_P1_#t~ite26, Thread1_P1_#t~ite28] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [607] L750-->L750-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_5 256))) (= |v_Thread1_P1_#t~ite31_1| v_~x$r_buff1_thd2~0_6)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_1|, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[Thread1_P1_#t~ite31] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite31|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [612] L750-8-->L752: Formula: (and (= v_~x$r_buff1_thd2~0_11 |v_Thread1_P1_#t~ite31_2|) (= v_~__unbuffered_p1_EBX~0_1 v_~x~0_5)) InVars {Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_2|, ~x~0=v_~x~0_5} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_1, Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_3|, Thread1_P1_#t~ite30=|v_Thread1_P1_#t~ite30_1|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_11, ~x~0=v_~x~0_5, Thread1_P1_#t~ite29=|v_Thread1_P1_#t~ite29_1|} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0, Thread1_P1_#t~ite31, Thread1_P1_#t~ite30, ~x$r_buff1_thd2~0, Thread1_P1_#t~ite29] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [616] L752-->L752-2: Formula: (and (= |v_Thread1_P1_#t~ite32_1| v_~x$mem_tmp~0_2) (not (= (mod v_~x$flush_delayed~0_2 256) 0))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_2, ~x$mem_tmp~0=v_~x$mem_tmp~0_2} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_2, ~x$flush_delayed~0=v_~x$flush_delayed~0_2, Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite32] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [540] L717-5-->L718: Formula: (= v_~x~0_2 |v_Thread0_P0_#t~ite4_2|) InVars {Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_2|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_3|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_1|, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[Thread0_P0_#t~ite4, Thread0_P0_#t~ite3, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [?] 1 [621] L752-2-->L756: Formula: (and (= v_~x~0_8 |v_Thread1_P1_#t~ite32_3|) (= v_~x$flush_delayed~0_4 0)) InVars {Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_3|} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_4, Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_4|, ~x~0=v_~x~0_8} AuxVars[] AssignedVars[~x$flush_delayed~0, Thread1_P1_#t~ite32, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [624] L756-->L756-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_35 256)) (= 0 (mod v_~x$r_buff0_thd2~0_24 256))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_24, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_35} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_24, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_35} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [627] L756-2-->L756-4: Formula: (and (= |v_Thread1_P1_#t~ite33_3| v_~x~0_9) (or (= 0 (mod v_~x$w_buff1_used~0_22 256)) (= (mod v_~x$r_buff1_thd2~0_15 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_22, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_15, ~x~0=v_~x~0_9} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_22, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_15, Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_3|, ~x~0=v_~x~0_9} AuxVars[] AssignedVars[Thread1_P1_#t~ite33] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite33|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [630] L756-4-->L756-5: Formula: (= |v_Thread1_P1_#t~ite34_4| |v_Thread1_P1_#t~ite33_4|) InVars {Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_4|} OutVars{Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_4|, Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_4|} AuxVars[] AssignedVars[Thread1_P1_#t~ite34] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite33|=0, |Thread1_P1_#t~ite34|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [625] L756-5-->L757: Formula: (= v_~x~0_10 |v_Thread1_P1_#t~ite34_2|) InVars {Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_2|} OutVars{Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_1|, Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_3|, ~x~0=v_~x~0_10} AuxVars[] AssignedVars[Thread1_P1_#t~ite33, Thread1_P1_#t~ite34, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [629] L757-->L757-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd2~0_28 256)) (= (mod v_~x$w_buff0_used~0_39 256) 0)) (= |v_Thread1_P1_#t~ite35_2| v_~x$w_buff0_used~0_39)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_28, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_39} OutVars{Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_28, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_39} AuxVars[] AssignedVars[Thread1_P1_#t~ite35] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite35|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [631] L757-2-->L758: Formula: (= v_~x$w_buff0_used~0_40 |v_Thread1_P1_#t~ite35_3|) InVars {Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_3|} OutVars{Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_40} AuxVars[] AssignedVars[Thread1_P1_#t~ite35, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [633] L758-->L758-2: Formula: (and (= |v_Thread1_P1_#t~ite36_2| v_~x$w_buff1_used~0_26) (or (= 0 (mod v_~x$r_buff0_thd2~0_32 256)) (= (mod v_~x$w_buff0_used~0_44 256) 0)) (or (= 0 (mod v_~x$r_buff1_thd2~0_19 256)) (= (mod v_~x$w_buff1_used~0_26 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_19, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_32, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_44} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_19, Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_32, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_44} AuxVars[] AssignedVars[Thread1_P1_#t~ite36] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite36|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [634] L758-2-->L759: Formula: (= v_~x$w_buff1_used~0_27 |v_Thread1_P1_#t~ite36_3|) InVars {Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_27, Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread1_P1_#t~ite36] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [636] L759-->L759-2: Formula: (and (= |v_Thread1_P1_#t~ite37_2| v_~x$r_buff0_thd2~0_36) (or (= (mod v_~x$w_buff0_used~0_48 256) 0) (= (mod v_~x$r_buff0_thd2~0_36 256) 0))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_36, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_48} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_36, Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_48} AuxVars[] AssignedVars[Thread1_P1_#t~ite37] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite37|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [637] L759-2-->L760: Formula: (= v_~x$r_buff0_thd2~0_37 |v_Thread1_P1_#t~ite37_3|) InVars {Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_3|} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_37, Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_4|} AuxVars[] AssignedVars[~x$r_buff0_thd2~0, Thread1_P1_#t~ite37] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [543] L718-->L718-2: Formula: (and (= |v_Thread0_P0_#t~ite5_1| 0) (not (= 0 (mod v_~x$r_buff0_thd1~0_5 256))) (not (= (mod v_~x$w_buff0_used~0_5 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} AuxVars[] AssignedVars[Thread0_P0_#t~ite5] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite5|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [546] L718-2-->L719: Formula: (= v_~x$w_buff0_used~0_7 |v_Thread0_P0_#t~ite5_3|) InVars {Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_3|} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} AuxVars[] AssignedVars[Thread0_P0_#t~ite5, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [548] L719-->L719-2: Formula: (and (= |v_Thread0_P0_#t~ite6_2| v_~x$w_buff1_used~0_5) (or (= 0 (mod v_~x$r_buff1_thd1~0_5 256)) (= 0 (mod v_~x$w_buff1_used~0_5 256))) (or (= (mod v_~x$w_buff0_used~0_9 256) 0) (= (mod v_~x$r_buff0_thd1~0_8 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_5, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_9} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_5, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_9} AuxVars[] AssignedVars[Thread0_P0_#t~ite6] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite6|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [549] L719-2-->L720: Formula: (= v_~x$w_buff1_used~0_6 |v_Thread0_P0_#t~ite6_3|) InVars {Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_6, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread0_P0_#t~ite6] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [551] L720-->L720-2: Formula: (and (= |v_Thread0_P0_#t~ite7_2| v_~x$r_buff0_thd1~0_10) (or (= (mod v_~x$w_buff0_used~0_11 256) 0) (= (mod v_~x$r_buff0_thd1~0_10 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_11} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_11} AuxVars[] AssignedVars[Thread0_P0_#t~ite7] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite7|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [552] L720-2-->L721: Formula: (= v_~x$r_buff0_thd1~0_11 |v_Thread0_P0_#t~ite7_3|) InVars {Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_3|} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_4|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_11} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, Thread0_P0_#t~ite7] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [554] L721-->L721-2: Formula: (and (or (= 0 (mod v_~x$w_buff0_used~0_13 256)) (= (mod v_~x$r_buff0_thd1~0_13 256) 0)) (= |v_Thread0_P0_#t~ite8_2| v_~x$r_buff1_thd1~0_7) (or (= (mod v_~x$r_buff1_thd1~0_7 256) 0) (= 0 (mod v_~x$w_buff1_used~0_8 256)))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_8, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_13} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_8, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_13} AuxVars[] AssignedVars[Thread0_P0_#t~ite8] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite8|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [555] L721-2-->L726: Formula: (and (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1)) (= v_~x$r_buff1_thd1~0_8 |v_Thread0_P0_#t~ite8_3|)) InVars {Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_8, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_4|} AuxVars[] AssignedVars[~__unbuffered_cnt~0, ~x$r_buff1_thd1~0, Thread0_P0_#t~ite8] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [639] L760-->L760-2: Formula: (and (= |v_Thread1_P1_#t~ite38_2| v_~x$r_buff1_thd2~0_21) (or (= (mod v_~x$r_buff0_thd2~0_39 256) 0) (= (mod v_~x$w_buff0_used~0_51 256) 0)) (or (= (mod v_~x$r_buff1_thd2~0_21 256) 0) (= (mod v_~x$w_buff1_used~0_29 256) 0))) InVars {~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_21, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_29, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_39, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_51} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_21, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_29, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_39, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_51} AuxVars[] AssignedVars[Thread1_P1_#t~ite38] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite38|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [640] L760-2-->L765: Formula: (and (= v_~x$r_buff1_thd2~0_22 |v_Thread1_P1_#t~ite38_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_3|} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_22, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_4|} AuxVars[] AssignedVars[~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, Thread1_P1_#t~ite38] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [513] L781-1-->L785: Formula: (= v_~main$tmp_guard0~0_1 (ite (= (ite (= v_~__unbuffered_cnt~0_5 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_2|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet41, ~main$tmp_guard0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [451] L785-->L787: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_2 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [481] L787-->L787-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_57 256)) (= (mod v_~x$r_buff0_thd0~0_4 256) 0)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_57} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_57} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [485] L787-2-->L787-4: Formula: (and (= |v_ULTIMATE.start_main_#t~ite42_3| v_~x~0_12) (or (= 0 (mod v_~x$w_buff1_used~0_34 256)) (= 0 (mod v_~x$r_buff1_thd0~0_4 256)))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_34, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_4, ~x~0=v_~x~0_12} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_34, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_4, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_3|, ~x~0=v_~x~0_12} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [491] L787-4-->L787-5: Formula: (= |v_ULTIMATE.start_main_#t~ite43_3| |v_ULTIMATE.start_main_#t~ite42_4|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [467] L787-5-->L788: Formula: (= v_~x~0_13 |v_ULTIMATE.start_main_#t~ite43_5|) InVars {ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|, ~x~0=v_~x~0_13} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [418] L788-->L788-2: Formula: (and (or (= (mod v_~x$r_buff0_thd0~0_6 256) 0) (= 0 (mod v_~x$w_buff0_used~0_59 256))) (= |v_ULTIMATE.start_main_#t~ite44_3| v_~x$w_buff0_used~0_59)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_59} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_59} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [423] L788-2-->L789: Formula: (= v_~x$w_buff0_used~0_60 |v_ULTIMATE.start_main_#t~ite44_5|) InVars {ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_5|} OutVars{ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_60} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [360] L789-->L789-2: Formula: (and (or (= (mod v_~x$r_buff0_thd0~0_8 256) 0) (= (mod v_~x$w_buff0_used~0_62 256) 0)) (= |v_ULTIMATE.start_main_#t~ite45_3| v_~x$w_buff1_used~0_36) (or (= (mod v_~x$r_buff1_thd0~0_6 256) 0) (= (mod v_~x$w_buff1_used~0_36 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_8, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_36, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_8, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_36, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite45] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [522] L789-2-->L790: Formula: (= v_~x$w_buff1_used~0_37 |v_ULTIMATE.start_main_#t~ite45_5|) InVars {ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_5|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_37, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite45] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [471] L790-->L790-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd0~0_10 256)) (= 0 (mod v_~x$w_buff0_used~0_64 256))) (= |v_ULTIMATE.start_main_#t~ite46_3| v_~x$r_buff0_thd0~0_10)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_64} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_10, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_64} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [458] L790-2-->L791: Formula: (= v_~x$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite46_5|) InVars {ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_5|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_11, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [408] L791-->L791-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite47_3| v_~x$r_buff1_thd0~0_8) (or (= 0 (mod v_~x$r_buff0_thd0~0_13 256)) (= (mod v_~x$w_buff0_used~0_66 256) 0)) (or (= 0 (mod v_~x$r_buff1_thd0~0_8 256)) (= 0 (mod v_~x$w_buff1_used~0_39 256)))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_13, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_39, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_66} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_3|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_13, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_39, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_66} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [415] L791-2-->L796: Formula: (and (= v_~x$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite47_5|) (= v_~main$tmp_guard1~0_2 (ite (= 0 (ite (not (and (= 2 v_~y~0_4) (= 0 v_~__unbuffered_p1_EBX~0_2) (= 1 v_~__unbuffered_p1_EAX~0_2))) 1 0)) 0 1))) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_5|, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~y~0=v_~y~0_4} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_4|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ~y~0=v_~y~0_4, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ~main$tmp_guard1~0, ~x$r_buff1_thd0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [450] L796-->L796-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_3 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [452] L796-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [406] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [404] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [402] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1611~0.base, main_~#t1611~0.offset, main_~#t1612~0.base, main_~#t1612~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t1611~0.base, main_~#t1611~0.offset := #Ultimate.alloc(4); srcloc: L778 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1611~0.base, main_~#t1611~0.offset, 4); srcloc: L778-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 1;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd1~0 := 1;~y~0 := 1; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite4 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 havoc main_#t~nondet40; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 SUMMARY for call main_~#t1612~0.base, main_~#t1612~0.offset := #Ultimate.alloc(4); srcloc: L780 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t1612~0.base, main_~#t1612~0.offset, 4); srcloc: L780-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 2;~z~0 := 1;~__unbuffered_p1_EAX~0 := ~z~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256);#t~ite13 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x~0 := #t~ite13;havoc #t~ite12;havoc #t~ite13; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff0~0 := #t~ite16;havoc #t~ite16;havoc #t~ite15;havoc #t~ite14; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~x$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff1~0 := #t~ite19;havoc #t~ite18;havoc #t~ite17;havoc #t~ite19; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite22;havoc #t~ite20;havoc #t~ite21;havoc #t~ite22; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite25;havoc #t~ite23;havoc #t~ite24;havoc #t~ite25; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff0_thd2~0 := #t~ite28;havoc #t~ite26;havoc #t~ite28;havoc #t~ite27; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff1_thd2~0 := #t~ite31;havoc #t~ite31;havoc #t~ite29;havoc #t~ite30;~__unbuffered_p1_EBX~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~x$flush_delayed~0 % 256;#t~ite32 := ~x$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x~0 := #t~ite4;havoc #t~ite4;havoc #t~ite3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [?] 1 ~x~0 := #t~ite32;havoc #t~ite32;~x$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256);#t~ite33 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x~0 := #t~ite34;havoc #t~ite34;havoc #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite35 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite36 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite37 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite38 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite42 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite44 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite45 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1611~0.base, main_~#t1611~0.offset, main_~#t1612~0.base, main_~#t1612~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t1611~0.base, main_~#t1611~0.offset := #Ultimate.alloc(4); srcloc: L778 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1611~0.base, main_~#t1611~0.offset, 4); srcloc: L778-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 1;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd1~0 := 1;~y~0 := 1; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite4 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 havoc main_#t~nondet40; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 SUMMARY for call main_~#t1612~0.base, main_~#t1612~0.offset := #Ultimate.alloc(4); srcloc: L780 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t1612~0.base, main_~#t1612~0.offset, 4); srcloc: L780-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 2;~z~0 := 1;~__unbuffered_p1_EAX~0 := ~z~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256);#t~ite13 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x~0 := #t~ite13;havoc #t~ite12;havoc #t~ite13; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff0~0 := #t~ite16;havoc #t~ite16;havoc #t~ite15;havoc #t~ite14; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~x$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff1~0 := #t~ite19;havoc #t~ite18;havoc #t~ite17;havoc #t~ite19; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite22;havoc #t~ite20;havoc #t~ite21;havoc #t~ite22; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite25;havoc #t~ite23;havoc #t~ite24;havoc #t~ite25; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff0_thd2~0 := #t~ite28;havoc #t~ite26;havoc #t~ite28;havoc #t~ite27; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff1_thd2~0 := #t~ite31;havoc #t~ite31;havoc #t~ite29;havoc #t~ite30;~__unbuffered_p1_EBX~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~x$flush_delayed~0 % 256;#t~ite32 := ~x$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x~0 := #t~ite4;havoc #t~ite4;havoc #t~ite3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [?] 1 ~x~0 := #t~ite32;havoc #t~ite32;~x$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256);#t~ite33 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x~0 := #t~ite34;havoc #t~ite34;havoc #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite35 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite36 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite37 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite38 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite42 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite44 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite45 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L698] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L699] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1611~0.base, main_~#t1611~0.offset, main_~#t1612~0.base, main_~#t1612~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L778] -1 call main_~#t1611~0.base, main_~#t1611~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] -1 call write~int(0, main_~#t1611~0.base, main_~#t1611~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L700-L727] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L703] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L704] 0 ~x$w_buff0~0 := 1; [L705] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L706] 0 ~x$w_buff0_used~0 := 1; [L707] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L707] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L708] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L709] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L710] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L711] 0 ~x$r_buff0_thd1~0 := 1; [L714] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L717] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L717] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L779] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L780] -1 call main_~#t1612~0.base, main_~#t1612~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] -1 call write~int(1, main_~#t1612~0.base, main_~#t1612~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L728-L766] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L731] 1 ~y~0 := 2; [L734] 1 ~z~0 := 1; [L737] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L740] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L740] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L741] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L741] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L742] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L743] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256); [L744] 1 #t~ite13 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 ~x~0 := #t~ite13; [L744] 1 havoc #t~ite12; [L744] 1 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 assume 0 != ~weak$$choice2~0 % 256; [L745] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 ~x$w_buff0~0 := #t~ite16; [L745] 1 havoc #t~ite16; [L745] 1 havoc #t~ite15; [L745] 1 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 assume 0 != ~weak$$choice2~0 % 256; [L746] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 ~x$w_buff1~0 := #t~ite19; [L746] 1 havoc #t~ite18; [L746] 1 havoc #t~ite17; [L746] 1 havoc #t~ite19; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 assume 0 != ~weak$$choice2~0 % 256; [L747] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 ~x$w_buff0_used~0 := #t~ite22; [L747] 1 havoc #t~ite20; [L747] 1 havoc #t~ite21; [L747] 1 havoc #t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 assume 0 != ~weak$$choice2~0 % 256; [L748] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 ~x$w_buff1_used~0 := #t~ite25; [L748] 1 havoc #t~ite23; [L748] 1 havoc #t~ite24; [L748] 1 havoc #t~ite25; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 assume 0 != ~weak$$choice2~0 % 256; [L749] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L749] 1 havoc #t~ite26; [L749] 1 havoc #t~ite28; [L749] 1 havoc #t~ite27; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 assume 0 != ~weak$$choice2~0 % 256; [L750] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L750] 1 havoc #t~ite31; [L750] 1 havoc #t~ite29; [L750] 1 havoc #t~ite30; [L751] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L752] 1 assume 0 != ~x$flush_delayed~0 % 256; [L752] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L717] 0 ~x~0 := #t~ite4; [L717] 0 havoc #t~ite4; [L717] 0 havoc #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [L752] 1 ~x~0 := #t~ite32; [L752] 1 havoc #t~ite32; [L753] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L756] 1 #t~ite33 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 ~x~0 := #t~ite34; [L756] 1 havoc #t~ite34; [L756] 1 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L757] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 ~x$w_buff0_used~0 := #t~ite35; [L757] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L758] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 ~x$w_buff1_used~0 := #t~ite36; [L758] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L759] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L759] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L718] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 ~x$w_buff0_used~0 := #t~ite5; [L718] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L719] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 ~x$w_buff1_used~0 := #t~ite6; [L719] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L720] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L720] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L721] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L721] 0 havoc #t~ite8; [L724] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L760] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L760] 1 havoc #t~ite38; [L763] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L781] -1 havoc main_#t~nondet41; [L783] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L785] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L787] -1 main_#t~ite42 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 ~x~0 := main_#t~ite43; [L787] -1 havoc main_#t~ite42; [L787] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L788] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L788] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L789] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L789] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L790] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L790] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L791] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L791] -1 havoc main_#t~ite47; [L794] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L698] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L699] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1611~0.base, main_~#t1611~0.offset, main_~#t1612~0.base, main_~#t1612~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L778] -1 call main_~#t1611~0.base, main_~#t1611~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] -1 call write~int(0, main_~#t1611~0.base, main_~#t1611~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L700-L727] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L703] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L704] 0 ~x$w_buff0~0 := 1; [L705] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L706] 0 ~x$w_buff0_used~0 := 1; [L707] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L707] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L708] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L709] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L710] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L711] 0 ~x$r_buff0_thd1~0 := 1; [L714] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L717] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L717] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L779] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L780] -1 call main_~#t1612~0.base, main_~#t1612~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] -1 call write~int(1, main_~#t1612~0.base, main_~#t1612~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L728-L766] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L731] 1 ~y~0 := 2; [L734] 1 ~z~0 := 1; [L737] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L740] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L740] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L741] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L741] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L742] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L743] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256); [L744] 1 #t~ite13 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 ~x~0 := #t~ite13; [L744] 1 havoc #t~ite12; [L744] 1 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 assume 0 != ~weak$$choice2~0 % 256; [L745] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 ~x$w_buff0~0 := #t~ite16; [L745] 1 havoc #t~ite16; [L745] 1 havoc #t~ite15; [L745] 1 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 assume 0 != ~weak$$choice2~0 % 256; [L746] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 ~x$w_buff1~0 := #t~ite19; [L746] 1 havoc #t~ite18; [L746] 1 havoc #t~ite17; [L746] 1 havoc #t~ite19; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 assume 0 != ~weak$$choice2~0 % 256; [L747] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 ~x$w_buff0_used~0 := #t~ite22; [L747] 1 havoc #t~ite20; [L747] 1 havoc #t~ite21; [L747] 1 havoc #t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 assume 0 != ~weak$$choice2~0 % 256; [L748] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 ~x$w_buff1_used~0 := #t~ite25; [L748] 1 havoc #t~ite23; [L748] 1 havoc #t~ite24; [L748] 1 havoc #t~ite25; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 assume 0 != ~weak$$choice2~0 % 256; [L749] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L749] 1 havoc #t~ite26; [L749] 1 havoc #t~ite28; [L749] 1 havoc #t~ite27; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 assume 0 != ~weak$$choice2~0 % 256; [L750] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L750] 1 havoc #t~ite31; [L750] 1 havoc #t~ite29; [L750] 1 havoc #t~ite30; [L751] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L752] 1 assume 0 != ~x$flush_delayed~0 % 256; [L752] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L717] 0 ~x~0 := #t~ite4; [L717] 0 havoc #t~ite4; [L717] 0 havoc #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [L752] 1 ~x~0 := #t~ite32; [L752] 1 havoc #t~ite32; [L753] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L756] 1 #t~ite33 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 ~x~0 := #t~ite34; [L756] 1 havoc #t~ite34; [L756] 1 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L757] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 ~x$w_buff0_used~0 := #t~ite35; [L757] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L758] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 ~x$w_buff1_used~0 := #t~ite36; [L758] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L759] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L759] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L718] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 ~x$w_buff0_used~0 := #t~ite5; [L718] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L719] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 ~x$w_buff1_used~0 := #t~ite6; [L719] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L720] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L720] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L721] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L721] 0 havoc #t~ite8; [L724] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L760] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L760] 1 havoc #t~ite38; [L763] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L781] -1 havoc main_#t~nondet41; [L783] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L785] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L787] -1 main_#t~ite42 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 ~x~0 := main_#t~ite43; [L787] -1 havoc main_#t~ite42; [L787] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L788] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L788] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L789] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L789] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L790] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L790] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L791] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L791] -1 havoc main_#t~ite47; [L794] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L698] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L699] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1611~0, main_~#t1612~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L778] FCALL -1 call main_~#t1611~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FCALL -1 call write~int(0, main_~#t1611~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L700-L727] 0 ~arg := #in~arg; [L703] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L704] 0 ~x$w_buff0~0 := 1; [L705] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L706] 0 ~x$w_buff0_used~0 := 1; [L707] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L707] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L708] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L709] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L710] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L711] 0 ~x$r_buff0_thd1~0 := 1; [L714] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L717] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L717] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L779] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L780] FCALL -1 call main_~#t1612~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FCALL -1 call write~int(1, main_~#t1612~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L728-L766] 1 ~arg := #in~arg; [L731] 1 ~y~0 := 2; [L734] 1 ~z~0 := 1; [L737] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L740] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L740] 1 havoc #t~nondet10; [L741] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L741] 1 havoc #t~nondet11; [L742] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L743] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L744] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 ~x~0 := #t~ite13; [L744] 1 havoc #t~ite12; [L744] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 ~x$w_buff0~0 := #t~ite16; [L745] 1 havoc #t~ite16; [L745] 1 havoc #t~ite15; [L745] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L746] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 ~x$w_buff1~0 := #t~ite19; [L746] 1 havoc #t~ite18; [L746] 1 havoc #t~ite17; [L746] 1 havoc #t~ite19; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 ~x$w_buff0_used~0 := #t~ite22; [L747] 1 havoc #t~ite20; [L747] 1 havoc #t~ite21; [L747] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 ~x$w_buff1_used~0 := #t~ite25; [L748] 1 havoc #t~ite23; [L748] 1 havoc #t~ite24; [L748] 1 havoc #t~ite25; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L749] 1 havoc #t~ite26; [L749] 1 havoc #t~ite28; [L749] 1 havoc #t~ite27; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L750] 1 havoc #t~ite31; [L750] 1 havoc #t~ite29; [L750] 1 havoc #t~ite30; [L751] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L752] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L752] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L717] 0 ~x~0 := #t~ite4; [L717] 0 havoc #t~ite4; [L717] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [L752] 1 ~x~0 := #t~ite32; [L752] 1 havoc #t~ite32; [L753] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L756] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 ~x~0 := #t~ite34; [L756] 1 havoc #t~ite34; [L756] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L757] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 ~x$w_buff0_used~0 := #t~ite35; [L757] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L758] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 ~x$w_buff1_used~0 := #t~ite36; [L758] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L759] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L759] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L718] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 ~x$w_buff0_used~0 := #t~ite5; [L718] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 ~x$w_buff1_used~0 := #t~ite6; [L719] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L720] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L720] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L721] 0 havoc #t~ite8; [L724] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L760] 1 havoc #t~ite38; [L763] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L781] -1 havoc main_#t~nondet41; [L783] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L785] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L787] -1 main_#t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 ~x~0 := main_#t~ite43; [L787] -1 havoc main_#t~ite42; [L787] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L788] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L788] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L789] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L789] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L790] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L790] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L791] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L791] -1 havoc main_#t~ite47; [L794] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L698] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L699] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1611~0, main_~#t1612~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L778] FCALL -1 call main_~#t1611~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FCALL -1 call write~int(0, main_~#t1611~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L700-L727] 0 ~arg := #in~arg; [L703] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L704] 0 ~x$w_buff0~0 := 1; [L705] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L706] 0 ~x$w_buff0_used~0 := 1; [L707] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L707] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L708] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L709] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L710] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L711] 0 ~x$r_buff0_thd1~0 := 1; [L714] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L717] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L717] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L779] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L780] FCALL -1 call main_~#t1612~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FCALL -1 call write~int(1, main_~#t1612~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L728-L766] 1 ~arg := #in~arg; [L731] 1 ~y~0 := 2; [L734] 1 ~z~0 := 1; [L737] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L740] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L740] 1 havoc #t~nondet10; [L741] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L741] 1 havoc #t~nondet11; [L742] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L743] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L744] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 ~x~0 := #t~ite13; [L744] 1 havoc #t~ite12; [L744] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 ~x$w_buff0~0 := #t~ite16; [L745] 1 havoc #t~ite16; [L745] 1 havoc #t~ite15; [L745] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L746] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 ~x$w_buff1~0 := #t~ite19; [L746] 1 havoc #t~ite18; [L746] 1 havoc #t~ite17; [L746] 1 havoc #t~ite19; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 ~x$w_buff0_used~0 := #t~ite22; [L747] 1 havoc #t~ite20; [L747] 1 havoc #t~ite21; [L747] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 ~x$w_buff1_used~0 := #t~ite25; [L748] 1 havoc #t~ite23; [L748] 1 havoc #t~ite24; [L748] 1 havoc #t~ite25; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L749] 1 havoc #t~ite26; [L749] 1 havoc #t~ite28; [L749] 1 havoc #t~ite27; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L750] 1 havoc #t~ite31; [L750] 1 havoc #t~ite29; [L750] 1 havoc #t~ite30; [L751] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L752] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L752] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L717] 0 ~x~0 := #t~ite4; [L717] 0 havoc #t~ite4; [L717] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [L752] 1 ~x~0 := #t~ite32; [L752] 1 havoc #t~ite32; [L753] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L756] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 ~x~0 := #t~ite34; [L756] 1 havoc #t~ite34; [L756] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L757] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 ~x$w_buff0_used~0 := #t~ite35; [L757] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L758] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 ~x$w_buff1_used~0 := #t~ite36; [L758] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L759] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L759] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L718] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 ~x$w_buff0_used~0 := #t~ite5; [L718] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 ~x$w_buff1_used~0 := #t~ite6; [L719] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L720] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L720] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L721] 0 havoc #t~ite8; [L724] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L760] 1 havoc #t~ite38; [L763] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L781] -1 havoc main_#t~nondet41; [L783] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L785] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L787] -1 main_#t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 ~x~0 := main_#t~ite43; [L787] -1 havoc main_#t~ite42; [L787] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L788] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L788] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L789] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L789] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L790] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L790] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L791] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L791] -1 havoc main_#t~ite47; [L794] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L698] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L699] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L778] FCALL -1 call ~#t1611~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FCALL -1 call write~int(0, ~#t1611~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L700-L727] 0 ~arg := #in~arg; [L703] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L704] 0 ~x$w_buff0~0 := 1; [L705] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L706] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L708] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L709] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L710] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L711] 0 ~x$r_buff0_thd1~0 := 1; [L714] 0 ~y~0 := 1; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L717] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L717] 0 #t~ite4 := ~x$w_buff0~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L779] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L780] FCALL -1 call ~#t1612~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FCALL -1 call write~int(1, ~#t1612~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L728-L766] 1 ~arg := #in~arg; [L731] 1 ~y~0 := 2; [L734] 1 ~z~0 := 1; [L737] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L740] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L740] 1 havoc #t~nondet10; [L741] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L741] 1 havoc #t~nondet11; [L742] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L743] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L744] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 ~x~0 := #t~ite13; [L744] 1 havoc #t~ite12; [L744] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 ~x$w_buff0~0 := #t~ite16; [L745] 1 havoc #t~ite16; [L745] 1 havoc #t~ite15; [L745] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L746] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 ~x$w_buff1~0 := #t~ite19; [L746] 1 havoc #t~ite18; [L746] 1 havoc #t~ite17; [L746] 1 havoc #t~ite19; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 ~x$w_buff0_used~0 := #t~ite22; [L747] 1 havoc #t~ite20; [L747] 1 havoc #t~ite21; [L747] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 ~x$w_buff1_used~0 := #t~ite25; [L748] 1 havoc #t~ite23; [L748] 1 havoc #t~ite24; [L748] 1 havoc #t~ite25; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L749] 1 havoc #t~ite26; [L749] 1 havoc #t~ite28; [L749] 1 havoc #t~ite27; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L750] 1 havoc #t~ite31; [L750] 1 havoc #t~ite29; [L750] 1 havoc #t~ite30; [L751] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L752] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L752] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L717] 0 ~x~0 := #t~ite4; [L717] 0 havoc #t~ite4; [L717] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [L752] 1 ~x~0 := #t~ite32; [L752] 1 havoc #t~ite32; [L753] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L756] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 ~x~0 := #t~ite34; [L756] 1 havoc #t~ite34; [L756] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L757] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 ~x$w_buff0_used~0 := #t~ite35; [L757] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L758] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 ~x$w_buff1_used~0 := #t~ite36; [L758] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L759] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L759] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L718] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 ~x$w_buff0_used~0 := #t~ite5; [L718] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 ~x$w_buff1_used~0 := #t~ite6; [L719] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L720] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L720] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L721] 0 havoc #t~ite8; [L724] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L760] 1 havoc #t~ite38; [L763] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L781] -1 havoc #t~nondet41; [L783] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L785] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L787] -1 #t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 ~x~0 := #t~ite43; [L787] -1 havoc #t~ite42; [L787] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L788] -1 #t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 ~x$w_buff0_used~0 := #t~ite44; [L788] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L789] -1 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 ~x$w_buff1_used~0 := #t~ite45; [L789] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L790] -1 #t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 ~x$r_buff0_thd0~0 := #t~ite46; [L790] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L791] -1 #t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 ~x$r_buff1_thd0~0 := #t~ite47; [L791] -1 havoc #t~ite47; [L794] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L698] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L699] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L778] FCALL -1 call ~#t1611~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FCALL -1 call write~int(0, ~#t1611~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L700-L727] 0 ~arg := #in~arg; [L703] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L704] 0 ~x$w_buff0~0 := 1; [L705] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L706] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L708] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L709] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L710] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L711] 0 ~x$r_buff0_thd1~0 := 1; [L714] 0 ~y~0 := 1; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L717] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L717] 0 #t~ite4 := ~x$w_buff0~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L779] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L780] FCALL -1 call ~#t1612~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FCALL -1 call write~int(1, ~#t1612~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L728-L766] 1 ~arg := #in~arg; [L731] 1 ~y~0 := 2; [L734] 1 ~z~0 := 1; [L737] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L740] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L740] 1 havoc #t~nondet10; [L741] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L741] 1 havoc #t~nondet11; [L742] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L743] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L744] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 ~x~0 := #t~ite13; [L744] 1 havoc #t~ite12; [L744] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 ~x$w_buff0~0 := #t~ite16; [L745] 1 havoc #t~ite16; [L745] 1 havoc #t~ite15; [L745] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L746] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 ~x$w_buff1~0 := #t~ite19; [L746] 1 havoc #t~ite18; [L746] 1 havoc #t~ite17; [L746] 1 havoc #t~ite19; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 ~x$w_buff0_used~0 := #t~ite22; [L747] 1 havoc #t~ite20; [L747] 1 havoc #t~ite21; [L747] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 ~x$w_buff1_used~0 := #t~ite25; [L748] 1 havoc #t~ite23; [L748] 1 havoc #t~ite24; [L748] 1 havoc #t~ite25; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L749] 1 havoc #t~ite26; [L749] 1 havoc #t~ite28; [L749] 1 havoc #t~ite27; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L750] 1 havoc #t~ite31; [L750] 1 havoc #t~ite29; [L750] 1 havoc #t~ite30; [L751] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L752] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L752] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L717] 0 ~x~0 := #t~ite4; [L717] 0 havoc #t~ite4; [L717] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [L752] 1 ~x~0 := #t~ite32; [L752] 1 havoc #t~ite32; [L753] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L756] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 ~x~0 := #t~ite34; [L756] 1 havoc #t~ite34; [L756] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L757] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 ~x$w_buff0_used~0 := #t~ite35; [L757] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L758] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 ~x$w_buff1_used~0 := #t~ite36; [L758] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L759] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L759] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L718] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 ~x$w_buff0_used~0 := #t~ite5; [L718] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 ~x$w_buff1_used~0 := #t~ite6; [L719] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L720] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L720] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L721] 0 havoc #t~ite8; [L724] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L760] 1 havoc #t~ite38; [L763] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L781] -1 havoc #t~nondet41; [L783] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L785] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L787] -1 #t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 ~x~0 := #t~ite43; [L787] -1 havoc #t~ite42; [L787] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L788] -1 #t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 ~x$w_buff0_used~0 := #t~ite44; [L788] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L789] -1 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 ~x$w_buff1_used~0 := #t~ite45; [L789] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L790] -1 #t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 ~x$r_buff0_thd0~0 := #t~ite46; [L790] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L791] -1 #t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 ~x$r_buff1_thd0~0 := #t~ite47; [L791] -1 havoc #t~ite47; [L794] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L675] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L676] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0] [L677] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L679] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L680] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0] [L681] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0] [L682] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L683] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L684] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L685] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L686] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L687] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L688] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L689] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L690] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L691] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L692] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L693] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L695] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L697] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L698] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L699] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L778] -1 pthread_t t1611; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L779] FCALL, FORK -1 pthread_create(&t1611, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L703] 0 x$w_buff1 = x$w_buff0 [L704] 0 x$w_buff0 = 1 [L705] 0 x$w_buff1_used = x$w_buff0_used [L706] 0 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L708] 0 x$r_buff1_thd0 = x$r_buff0_thd0 [L709] 0 x$r_buff1_thd1 = x$r_buff0_thd1 [L710] 0 x$r_buff1_thd2 = x$r_buff0_thd2 [L711] 0 x$r_buff0_thd1 = (_Bool)1 [L714] 0 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L717] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L780] -1 pthread_t t1612; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L781] FCALL, FORK -1 pthread_create(&t1612, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L731] 1 y = 2 [L734] 1 z = 1 [L737] 1 __unbuffered_p1_EAX = z [L740] 1 weak$$choice0 = __VERIFIER_nondet_pointer() [L741] 1 weak$$choice2 = __VERIFIER_nondet_pointer() [L742] 1 x$flush_delayed = weak$$choice2 [L743] 1 x$mem_tmp = x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L744] EXPR 1 !x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1) VAL [!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L744] 1 x = !x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1) [L745] EXPR 1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0))=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L745] 1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)) [L746] EXPR 1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L746] 1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)) [L747] EXPR 1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used))=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L747] 1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used)) [L748] EXPR 1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L748] 1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L749] EXPR 1 weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L749] 1 x$r_buff0_thd2 = weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2)) [L750] EXPR 1 weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L750] 1 x$r_buff1_thd2 = weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L751] 1 __unbuffered_p1_EBX = x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L752] EXPR 1 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=1, x$flush_delayed ? x$mem_tmp : x=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L717] 0 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L752] 1 x = x$flush_delayed ? x$mem_tmp : x [L753] 1 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L756] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L756] EXPR 1 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=2, z=1] [L756] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x)=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=2, z=1] [L756] 1 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L757] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L757] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L758] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L758] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L759] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L759] 1 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L718] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L718] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L719] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L719] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L720] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L720] 0 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L721] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L721] 0 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L724] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L760] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L760] 1 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L763] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L783] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L788] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L788] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L789] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L789] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L790] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L790] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L791] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L791] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L794] -1 main$tmp_guard1 = !(y == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] ----- [2018-11-23 06:10:44,079 INFO L305 ceAbstractionStarter]: Did not count any witness invariants because Icfg is not BoogieIcfg [2018-11-23 06:10:44,080 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 06:10:44 BasicIcfg [2018-11-23 06:10:44,080 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 06:10:44,081 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 06:10:44,100 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 06:10:44,100 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 06:10:44,100 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 06:10:09" (3/4) ... [2018-11-23 06:10:44,102 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [479] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [362] L-1-->L671: Formula: (= |v_#valid_9| (store |v_#valid_10| 0 0)) InVars {#valid=|v_#valid_10|} OutVars{#valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [518] L671-->L673: Formula: (= v_~__unbuffered_cnt~0_6 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [386] L673-->L675: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [435] L675-->L676: Formula: (= v_~__unbuffered_p1_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 [351] L676-->L677: Formula: (= v_~main$tmp_guard0~0_3 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 [488] L677-->L679: Formula: (= v_~main$tmp_guard1~0_1 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_1} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [527] L679-->L680: Formula: (= v_~x~0_11 0) InVars {} OutVars{~x~0=v_~x~0_11} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [462] L680-->L681: Formula: (= v_~x$flush_delayed~0_5 0) InVars {} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_5} AuxVars[] AssignedVars[~x$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 [393] L681-->L682: Formula: (= v_~x$mem_tmp~0_3 0) InVars {} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_3} AuxVars[] AssignedVars[~x$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 [517] L682-->L683: Formula: (= v_~x$r_buff0_thd0~0_2 0) InVars {} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_2} AuxVars[] AssignedVars[~x$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 [455] L683-->L684: Formula: (= v_~x$r_buff0_thd1~0_14 0) InVars {} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_14} AuxVars[] AssignedVars[~x$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 [385] L684-->L685: Formula: (= v_~x$r_buff0_thd2~0_43 0) InVars {} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_43} AuxVars[] AssignedVars[~x$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 [497] L685-->L686: Formula: (= v_~x$r_buff1_thd0~0_2 0) InVars {} OutVars{~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_2} AuxVars[] AssignedVars[~x$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 [432] L686-->L687: Formula: (= v_~x$r_buff1_thd1~0_9 0) InVars {} OutVars{~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 [378] L687-->L688: Formula: (= v_~x$r_buff1_thd2~0_25 0) InVars {} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_25} AuxVars[] AssignedVars[~x$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 [487] L688-->L689: Formula: (= v_~x$read_delayed~0_1 0) InVars {} OutVars{~x$read_delayed~0=v_~x$read_delayed~0_1} AuxVars[] AssignedVars[~x$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [426] L689-->L690: Formula: (and (= v_~x$read_delayed_var~0.offset_1 0) (= v_~x$read_delayed_var~0.base_1 0)) InVars {} OutVars{~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_1, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~x$read_delayed_var~0.offset, ~x$read_delayed_var~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [524] L690-->L691: Formula: (= v_~x$w_buff0~0_11 0) InVars {} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_11} AuxVars[] AssignedVars[~x$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [461] L691-->L692: Formula: (= v_~x$w_buff0_used~0_55 0) InVars {} OutVars{~x$w_buff0_used~0=v_~x$w_buff0_used~0_55} AuxVars[] AssignedVars[~x$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [392] L692-->L693: Formula: (= v_~x$w_buff1~0_10 0) InVars {} OutVars{~x$w_buff1~0=v_~x$w_buff1~0_10} AuxVars[] AssignedVars[~x$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [515] L693-->L695: Formula: (= v_~x$w_buff1_used~0_32 0) InVars {} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_32} AuxVars[] AssignedVars[~x$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [384] L695-->L697: Formula: (= v_~y~0_3 0) InVars {} OutVars{~y~0=v_~y~0_3} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [431] L697-->L698: Formula: (= v_~z~0_2 0) InVars {} OutVars{~z~0=v_~z~0_2} AuxVars[] AssignedVars[~z~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [375] L698-->L699: Formula: (= v_~weak$$choice0~0_2 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [486] L699-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [516] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [514] L-1-2-->L778: Formula: true InVars {} OutVars{ULTIMATE.start_main_~#t1612~0.base=|v_ULTIMATE.start_main_~#t1612~0.base_1|, ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_1|, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_1|, ULTIMATE.start_main_~#t1611~0.offset=|v_ULTIMATE.start_main_~#t1611~0.offset_1|, ULTIMATE.start_main_~#t1612~0.offset=|v_ULTIMATE.start_main_~#t1612~0.offset_1|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_1|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_1|, ULTIMATE.start_main_~#t1611~0.base=|v_ULTIMATE.start_main_~#t1611~0.base_1|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_1|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_1|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_1|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1612~0.base, ULTIMATE.start_main_#t~nondet40, ULTIMATE.start_main_#t~nondet41, ULTIMATE.start_main_~#t1611~0.offset, ULTIMATE.start_main_~#t1612~0.offset, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_~#t1611~0.base, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [361] L778-->L778-1: Formula: (and (= |v_#length_1| (store |v_#length_2| |v_ULTIMATE.start_main_~#t1611~0.base_2| 4)) (not (= 0 |v_ULTIMATE.start_main_~#t1611~0.base_2|)) (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t1611~0.base_2| 1) |v_#valid_1|) (= 0 (select |v_#valid_2| |v_ULTIMATE.start_main_~#t1611~0.base_2|)) (= |v_ULTIMATE.start_main_~#t1611~0.offset_2| 0)) InVars {#length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{ULTIMATE.start_main_~#t1611~0.base=|v_ULTIMATE.start_main_~#t1611~0.base_2|, #length=|v_#length_1|, ULTIMATE.start_main_~#t1611~0.offset=|v_ULTIMATE.start_main_~#t1611~0.offset_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1611~0.offset, #valid, ULTIMATE.start_main_~#t1611~0.base, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [521] L778-1-->L779: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1611~0.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1611~0.base_3|) |v_ULTIMATE.start_main_~#t1611~0.offset_3| 0))) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t1611~0.base=|v_ULTIMATE.start_main_~#t1611~0.base_3|, ULTIMATE.start_main_~#t1611~0.offset=|v_ULTIMATE.start_main_~#t1611~0.offset_3|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t1611~0.base=|v_ULTIMATE.start_main_~#t1611~0.base_3|, ULTIMATE.start_main_~#t1611~0.offset=|v_ULTIMATE.start_main_~#t1611~0.offset_3|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 [644] L779-->P0ENTRY: Formula: (and (= 0 |v_Thread0_P0_#in~arg.offset_3|) (= 0 v_Thread0_P0_thidvar0_2) (= 0 |v_Thread0_P0_#in~arg.base_3|)) InVars {} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_3|, Thread0_P0_thidvar0=v_Thread0_P0_thidvar0_2, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P0_#in~arg.base, Thread0_P0_thidvar0, Thread0_P0_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 [532] P0ENTRY-->L4: Formula: (and (= v_Thread0_P0_~arg.base_1 |v_Thread0_P0_#in~arg.base_1|) (= v_Thread0_P0_~arg.offset_1 |v_Thread0_P0_#in~arg.offset_1|) (= v_~x$w_buff0~0_1 1) (= v_Thread0_P0___VERIFIER_assert_~expression_1 |v_Thread0_P0___VERIFIER_assert_#in~expression_1|) (= v_~x$w_buff1~0_1 v_~x$w_buff0~0_2) (= v_~x$w_buff1_used~0_1 v_~x$w_buff0_used~0_2) (= v_~x$w_buff0_used~0_1 1) (= |v_Thread0_P0___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~x$w_buff1_used~0_1 256))) (not (= (mod v_~x$w_buff0_used~0_1 256) 0)))) 1 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_2, Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_2} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_1, Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_1, Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_~arg.offset=v_Thread0_P0_~arg.offset_1, ~x$w_buff1~0=v_~x$w_buff1~0_1, Thread0_P0_~arg.base=v_Thread0_P0_~arg.base_1, Thread0_P0___VERIFIER_assert_#in~expression=|v_Thread0_P0___VERIFIER_assert_#in~expression_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_1, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1} AuxVars[] AssignedVars[~x$w_buff0~0, Thread0_P0___VERIFIER_assert_~expression, Thread0_P0_~arg.offset, ~x$w_buff1~0, Thread0_P0_~arg.base, Thread0_P0___VERIFIER_assert_#in~expression, ~x$w_buff1_used~0, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 [534] L4-->L4-3: Formula: (not (= 0 v_Thread0_P0___VERIFIER_assert_~expression_3)) InVars {Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_3} OutVars{Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 [537] L4-3-->L717: Formula: (and (= v_~x$r_buff0_thd1~0_1 1) (= v_~x$r_buff1_thd0~0_1 v_~x$r_buff0_thd0~0_1) (= v_~x$r_buff1_thd2~0_1 v_~x$r_buff0_thd2~0_1) (= v_~x$r_buff1_thd1~0_1 v_~x$r_buff0_thd1~0_2) (= v_~y~0_1 1)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_2, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_1, ~y~0=v_~y~0_1, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_1} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, ~x$r_buff1_thd2~0, ~x$r_buff1_thd1~0, ~y~0, ~x$r_buff1_thd0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] 0 [538] L717-->L717-5: Formula: (and (not (= 0 (mod v_~x$w_buff0_used~0_3 256))) (= |v_Thread0_P0_#t~ite4_1| v_~x$w_buff0~0_3) (not (= 0 (mod v_~x$r_buff0_thd1~0_3 256)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_3, Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} AuxVars[] AssignedVars[Thread0_P0_#t~ite4] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 [476] L779-1-->L780: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet40] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 [409] L780-->L780-1: Formula: (and (= 0 (select |v_#valid_4| |v_ULTIMATE.start_main_~#t1612~0.base_2|)) (= |v_#valid_3| (store |v_#valid_4| |v_ULTIMATE.start_main_~#t1612~0.base_2| 1)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t1612~0.base_2| 4)) (= |v_ULTIMATE.start_main_~#t1612~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_main_~#t1612~0.base_2|))) InVars {#length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{ULTIMATE.start_main_~#t1612~0.base=|v_ULTIMATE.start_main_~#t1612~0.base_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t1612~0.offset=|v_ULTIMATE.start_main_~#t1612~0.offset_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1612~0.base, ULTIMATE.start_main_~#t1612~0.offset, #valid, #length] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 [410] L780-1-->L781: Formula: (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1612~0.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1612~0.base_3|) |v_ULTIMATE.start_main_~#t1612~0.offset_3| 1)) |v_#memory_int_3|) InVars {ULTIMATE.start_main_~#t1612~0.base=|v_ULTIMATE.start_main_~#t1612~0.base_3|, #memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t1612~0.offset=|v_ULTIMATE.start_main_~#t1612~0.offset_3|} OutVars{ULTIMATE.start_main_~#t1612~0.base=|v_ULTIMATE.start_main_~#t1612~0.base_3|, #memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t1612~0.offset=|v_ULTIMATE.start_main_~#t1612~0.offset_3|} AuxVars[] AssignedVars[#memory_int] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] FORK -1 [645] L781-->P1ENTRY: Formula: (and (= 0 |v_Thread1_P1_#in~arg.base_3|) (= 0 |v_Thread1_P1_#in~arg.offset_3|) (= 1 v_Thread1_P1_thidvar0_2)) InVars {} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_3|, Thread1_P1_thidvar0=v_Thread1_P1_thidvar0_2, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_P1_#in~arg.base, Thread1_P1_thidvar0, Thread1_P1_#in~arg.offset] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] 1 [559] P1ENTRY-->L744: Formula: (and (= v_Thread1_P1_~arg.offset_1 |v_Thread1_P1_#in~arg.offset_1|) (= v_~z~0_1 1) (= v_Thread1_P1_~arg.base_1 |v_Thread1_P1_#in~arg.base_1|) (= v_~y~0_2 2) (= v_~x$flush_delayed~0_1 v_~weak$$choice2~0_7) (= v_~weak$$choice0~0_1 (ite (= 0 (+ |v_Thread1_P1_#t~nondet10.base_1| |v_Thread1_P1_#t~nondet10.offset_1|)) 0 1)) (= v_~__unbuffered_p1_EAX~0_1 v_~z~0_1) (= v_~x$mem_tmp~0_1 v_~x~0_3) (= v_~weak$$choice2~0_7 (ite (= (+ |v_Thread1_P1_#t~nondet11.offset_1| |v_Thread1_P1_#t~nondet11.base_1|) 0) 0 1))) InVars {Thread1_P1_#t~nondet10.offset=|v_Thread1_P1_#t~nondet10.offset_1|, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_#t~nondet10.base=|v_Thread1_P1_#t~nondet10.base_1|, Thread1_P1_#t~nondet11.base=|v_Thread1_P1_#t~nondet11.base_1|, Thread1_P1_#t~nondet11.offset=|v_Thread1_P1_#t~nondet11.offset_1|, ~x~0=v_~x~0_3, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_~arg.offset=v_Thread1_P1_~arg.offset_1, Thread1_P1_#t~nondet10.base=|v_Thread1_P1_#t~nondet10.base_2|, ~x$flush_delayed~0=v_~x$flush_delayed~0_1, ~x$mem_tmp~0=v_~x$mem_tmp~0_1, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, Thread1_P1_#t~nondet10.offset=|v_Thread1_P1_#t~nondet10.offset_2|, ~weak$$choice0~0=v_~weak$$choice0~0_1, Thread1_P1_~arg.base=v_Thread1_P1_~arg.base_1, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, Thread1_P1_#t~nondet11.base=|v_Thread1_P1_#t~nondet11.base_2|, ~z~0=v_~z~0_1, ~weak$$choice2~0=v_~weak$$choice2~0_7, ~y~0=v_~y~0_2, Thread1_P1_#t~nondet11.offset=|v_Thread1_P1_#t~nondet11.offset_2|, ~x~0=v_~x~0_3} AuxVars[] AssignedVars[Thread1_P1_~arg.offset, Thread1_P1_#t~nondet10.base, ~x$flush_delayed~0, ~x$mem_tmp~0, Thread1_P1_#t~nondet10.offset, ~weak$$choice0~0, Thread1_P1_~arg.base, ~__unbuffered_p1_EAX~0, Thread1_P1_#t~nondet11.base, ~z~0, ~weak$$choice2~0, ~y~0, Thread1_P1_#t~nondet11.offset] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [560] L744-->L744-5: Formula: (and (= |v_Thread1_P1_#t~ite13_1| v_~x~0_4) (let ((.cse0 (= (mod v_~x$r_buff0_thd2~0_15 256) 0))) (or (and .cse0 (= (mod v_~x$w_buff1_used~0_17 256) 0)) (= (mod v_~x$w_buff0_used~0_26 256) 0) (and (= 0 (mod v_~x$r_buff1_thd2~0_9 256)) .cse0)))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_17, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_9, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_15, ~x~0=v_~x~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_26} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_17, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_9, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_15, ~x~0=v_~x~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_26} AuxVars[] AssignedVars[Thread1_P1_#t~ite13] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite13|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [562] L744-5-->L745: Formula: (= v_~x~0_6 |v_Thread1_P1_#t~ite13_2|) InVars {Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_2|} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_1|, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_3|, ~x~0=v_~x~0_6} AuxVars[] AssignedVars[Thread1_P1_#t~ite12, Thread1_P1_#t~ite13, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [565] L745-->L745-8: Formula: (and (not (= (mod v_~weak$$choice2~0_8 256) 0)) (= |v_Thread1_P1_#t~ite16_1| v_~x$w_buff0~0_5)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_8} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_8, Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite16] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite16|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [568] L745-8-->L746: Formula: (= v_~x$w_buff0~0_10 |v_Thread1_P1_#t~ite16_2|) InVars {Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_2|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_10, Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_1|, Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_3|, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_1|} AuxVars[] AssignedVars[~x$w_buff0~0, Thread1_P1_#t~ite14, Thread1_P1_#t~ite16, Thread1_P1_#t~ite15] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [571] L746-->L746-8: Formula: (and (not (= (mod v_~weak$$choice2~0_10 256) 0)) (= |v_Thread1_P1_#t~ite19_1| v_~x$w_buff1~0_5)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_10, ~x$w_buff1~0=v_~x$w_buff1~0_5} OutVars{Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_1|, ~weak$$choice2~0=v_~weak$$choice2~0_10, ~x$w_buff1~0=v_~x$w_buff1~0_5} AuxVars[] AssignedVars[Thread1_P1_#t~ite19] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite19|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [576] L746-8-->L747: Formula: (= v_~x$w_buff1~0_9 |v_Thread1_P1_#t~ite19_2|) InVars {Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_2|} OutVars{Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_3|, Thread1_P1_#t~ite18=|v_Thread1_P1_#t~ite18_1|, ~x$w_buff1~0=v_~x$w_buff1~0_9, Thread1_P1_#t~ite17=|v_Thread1_P1_#t~ite17_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite19, ~x$w_buff1~0, Thread1_P1_#t~ite18, Thread1_P1_#t~ite17] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [580] L747-->L747-8: Formula: (and (not (= (mod v_~weak$$choice2~0_12 256) 0)) (= |v_Thread1_P1_#t~ite22_1| v_~x$w_buff0_used~0_50)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} OutVars{Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_1|, ~weak$$choice2~0=v_~weak$$choice2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} AuxVars[] AssignedVars[Thread1_P1_#t~ite22] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite22|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [585] L747-8-->L748: Formula: (= v_~x$w_buff0_used~0_15 |v_Thread1_P1_#t~ite22_2|) InVars {Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_2|} OutVars{Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_3|, Thread1_P1_#t~ite21=|v_Thread1_P1_#t~ite21_1|, Thread1_P1_#t~ite20=|v_Thread1_P1_#t~ite20_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_15} AuxVars[] AssignedVars[Thread1_P1_#t~ite21, Thread1_P1_#t~ite20, Thread1_P1_#t~ite22, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [589] L748-->L748-8: Formula: (and (= |v_Thread1_P1_#t~ite25_1| v_~x$w_buff1_used~0_9) (not (= (mod v_~weak$$choice2~0_1 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_1, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_9} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_9, Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_1|, ~weak$$choice2~0=v_~weak$$choice2~0_1} AuxVars[] AssignedVars[Thread1_P1_#t~ite25] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite25|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [594] L748-8-->L749: Formula: (= v_~x$w_buff1_used~0_12 |v_Thread1_P1_#t~ite25_2|) InVars {Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_2|} OutVars{Thread1_P1_#t~ite23=|v_Thread1_P1_#t~ite23_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_12, Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_3|, Thread1_P1_#t~ite24=|v_Thread1_P1_#t~ite24_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite23, ~x$w_buff1_used~0, Thread1_P1_#t~ite25, Thread1_P1_#t~ite24] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [598] L749-->L749-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_3 256))) (= |v_Thread1_P1_#t~ite28_1| v_~x$r_buff0_thd2~0_7)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_3} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_7, ~weak$$choice2~0=v_~weak$$choice2~0_3, Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite28] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite28|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [603] L749-8-->L750: Formula: (= v_~x$r_buff0_thd2~0_12 |v_Thread1_P1_#t~ite28_2|) InVars {Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_2|} OutVars{Thread1_P1_#t~ite27=|v_Thread1_P1_#t~ite27_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_12, Thread1_P1_#t~ite26=|v_Thread1_P1_#t~ite26_1|, Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_3|} AuxVars[] AssignedVars[Thread1_P1_#t~ite27, ~x$r_buff0_thd2~0, Thread1_P1_#t~ite26, Thread1_P1_#t~ite28] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [607] L750-->L750-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_5 256))) (= |v_Thread1_P1_#t~ite31_1| v_~x$r_buff1_thd2~0_6)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_1|, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[Thread1_P1_#t~ite31] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite31|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [612] L750-8-->L752: Formula: (and (= v_~x$r_buff1_thd2~0_11 |v_Thread1_P1_#t~ite31_2|) (= v_~__unbuffered_p1_EBX~0_1 v_~x~0_5)) InVars {Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_2|, ~x~0=v_~x~0_5} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_1, Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_3|, Thread1_P1_#t~ite30=|v_Thread1_P1_#t~ite30_1|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_11, ~x~0=v_~x~0_5, Thread1_P1_#t~ite29=|v_Thread1_P1_#t~ite29_1|} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0, Thread1_P1_#t~ite31, Thread1_P1_#t~ite30, ~x$r_buff1_thd2~0, Thread1_P1_#t~ite29] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [616] L752-->L752-2: Formula: (and (= |v_Thread1_P1_#t~ite32_1| v_~x$mem_tmp~0_2) (not (= (mod v_~x$flush_delayed~0_2 256) 0))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_2, ~x$mem_tmp~0=v_~x$mem_tmp~0_2} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_2, ~x$flush_delayed~0=v_~x$flush_delayed~0_2, Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite32] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [540] L717-5-->L718: Formula: (= v_~x~0_2 |v_Thread0_P0_#t~ite4_2|) InVars {Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_2|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_3|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_1|, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[Thread0_P0_#t~ite4, Thread0_P0_#t~ite3, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [?] 1 [621] L752-2-->L756: Formula: (and (= v_~x~0_8 |v_Thread1_P1_#t~ite32_3|) (= v_~x$flush_delayed~0_4 0)) InVars {Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_3|} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_4, Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_4|, ~x~0=v_~x~0_8} AuxVars[] AssignedVars[~x$flush_delayed~0, Thread1_P1_#t~ite32, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [624] L756-->L756-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_35 256)) (= 0 (mod v_~x$r_buff0_thd2~0_24 256))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_24, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_35} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_24, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_35} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [627] L756-2-->L756-4: Formula: (and (= |v_Thread1_P1_#t~ite33_3| v_~x~0_9) (or (= 0 (mod v_~x$w_buff1_used~0_22 256)) (= (mod v_~x$r_buff1_thd2~0_15 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_22, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_15, ~x~0=v_~x~0_9} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_22, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_15, Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_3|, ~x~0=v_~x~0_9} AuxVars[] AssignedVars[Thread1_P1_#t~ite33] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite33|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [630] L756-4-->L756-5: Formula: (= |v_Thread1_P1_#t~ite34_4| |v_Thread1_P1_#t~ite33_4|) InVars {Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_4|} OutVars{Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_4|, Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_4|} AuxVars[] AssignedVars[Thread1_P1_#t~ite34] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite33|=0, |Thread1_P1_#t~ite34|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [625] L756-5-->L757: Formula: (= v_~x~0_10 |v_Thread1_P1_#t~ite34_2|) InVars {Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_2|} OutVars{Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_1|, Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_3|, ~x~0=v_~x~0_10} AuxVars[] AssignedVars[Thread1_P1_#t~ite33, Thread1_P1_#t~ite34, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [629] L757-->L757-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd2~0_28 256)) (= (mod v_~x$w_buff0_used~0_39 256) 0)) (= |v_Thread1_P1_#t~ite35_2| v_~x$w_buff0_used~0_39)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_28, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_39} OutVars{Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_28, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_39} AuxVars[] AssignedVars[Thread1_P1_#t~ite35] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite35|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [631] L757-2-->L758: Formula: (= v_~x$w_buff0_used~0_40 |v_Thread1_P1_#t~ite35_3|) InVars {Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_3|} OutVars{Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_40} AuxVars[] AssignedVars[Thread1_P1_#t~ite35, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [633] L758-->L758-2: Formula: (and (= |v_Thread1_P1_#t~ite36_2| v_~x$w_buff1_used~0_26) (or (= 0 (mod v_~x$r_buff0_thd2~0_32 256)) (= (mod v_~x$w_buff0_used~0_44 256) 0)) (or (= 0 (mod v_~x$r_buff1_thd2~0_19 256)) (= (mod v_~x$w_buff1_used~0_26 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_19, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_32, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_44} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_19, Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_32, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_44} AuxVars[] AssignedVars[Thread1_P1_#t~ite36] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite36|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [634] L758-2-->L759: Formula: (= v_~x$w_buff1_used~0_27 |v_Thread1_P1_#t~ite36_3|) InVars {Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_27, Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread1_P1_#t~ite36] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [636] L759-->L759-2: Formula: (and (= |v_Thread1_P1_#t~ite37_2| v_~x$r_buff0_thd2~0_36) (or (= (mod v_~x$w_buff0_used~0_48 256) 0) (= (mod v_~x$r_buff0_thd2~0_36 256) 0))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_36, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_48} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_36, Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_48} AuxVars[] AssignedVars[Thread1_P1_#t~ite37] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite37|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [637] L759-2-->L760: Formula: (= v_~x$r_buff0_thd2~0_37 |v_Thread1_P1_#t~ite37_3|) InVars {Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_3|} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_37, Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_4|} AuxVars[] AssignedVars[~x$r_buff0_thd2~0, Thread1_P1_#t~ite37] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [543] L718-->L718-2: Formula: (and (= |v_Thread0_P0_#t~ite5_1| 0) (not (= 0 (mod v_~x$r_buff0_thd1~0_5 256))) (not (= (mod v_~x$w_buff0_used~0_5 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} AuxVars[] AssignedVars[Thread0_P0_#t~ite5] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite5|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [546] L718-2-->L719: Formula: (= v_~x$w_buff0_used~0_7 |v_Thread0_P0_#t~ite5_3|) InVars {Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_3|} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} AuxVars[] AssignedVars[Thread0_P0_#t~ite5, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [548] L719-->L719-2: Formula: (and (= |v_Thread0_P0_#t~ite6_2| v_~x$w_buff1_used~0_5) (or (= 0 (mod v_~x$r_buff1_thd1~0_5 256)) (= 0 (mod v_~x$w_buff1_used~0_5 256))) (or (= (mod v_~x$w_buff0_used~0_9 256) 0) (= (mod v_~x$r_buff0_thd1~0_8 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_5, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_9} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_5, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_9} AuxVars[] AssignedVars[Thread0_P0_#t~ite6] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite6|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [549] L719-2-->L720: Formula: (= v_~x$w_buff1_used~0_6 |v_Thread0_P0_#t~ite6_3|) InVars {Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_6, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread0_P0_#t~ite6] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [551] L720-->L720-2: Formula: (and (= |v_Thread0_P0_#t~ite7_2| v_~x$r_buff0_thd1~0_10) (or (= (mod v_~x$w_buff0_used~0_11 256) 0) (= (mod v_~x$r_buff0_thd1~0_10 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_11} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_11} AuxVars[] AssignedVars[Thread0_P0_#t~ite7] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite7|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [552] L720-2-->L721: Formula: (= v_~x$r_buff0_thd1~0_11 |v_Thread0_P0_#t~ite7_3|) InVars {Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_3|} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_4|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_11} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, Thread0_P0_#t~ite7] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [554] L721-->L721-2: Formula: (and (or (= 0 (mod v_~x$w_buff0_used~0_13 256)) (= (mod v_~x$r_buff0_thd1~0_13 256) 0)) (= |v_Thread0_P0_#t~ite8_2| v_~x$r_buff1_thd1~0_7) (or (= (mod v_~x$r_buff1_thd1~0_7 256) 0) (= 0 (mod v_~x$w_buff1_used~0_8 256)))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_8, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_13} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_8, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_13} AuxVars[] AssignedVars[Thread0_P0_#t~ite8] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite8|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 [555] L721-2-->L726: Formula: (and (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1)) (= v_~x$r_buff1_thd1~0_8 |v_Thread0_P0_#t~ite8_3|)) InVars {Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_8, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_4|} AuxVars[] AssignedVars[~__unbuffered_cnt~0, ~x$r_buff1_thd1~0, Thread0_P0_#t~ite8] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [639] L760-->L760-2: Formula: (and (= |v_Thread1_P1_#t~ite38_2| v_~x$r_buff1_thd2~0_21) (or (= (mod v_~x$r_buff0_thd2~0_39 256) 0) (= (mod v_~x$w_buff0_used~0_51 256) 0)) (or (= (mod v_~x$r_buff1_thd2~0_21 256) 0) (= (mod v_~x$w_buff1_used~0_29 256) 0))) InVars {~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_21, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_29, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_39, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_51} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_21, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_29, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_39, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_51} AuxVars[] AssignedVars[Thread1_P1_#t~ite38] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite38|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 [640] L760-2-->L765: Formula: (and (= v_~x$r_buff1_thd2~0_22 |v_Thread1_P1_#t~ite38_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_3|} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_22, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_4|} AuxVars[] AssignedVars[~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, Thread1_P1_#t~ite38] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [513] L781-1-->L785: Formula: (= v_~main$tmp_guard0~0_1 (ite (= (ite (= v_~__unbuffered_cnt~0_5 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_2|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet41, ~main$tmp_guard0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [451] L785-->L787: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_2 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [481] L787-->L787-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_57 256)) (= (mod v_~x$r_buff0_thd0~0_4 256) 0)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_57} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_57} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [485] L787-2-->L787-4: Formula: (and (= |v_ULTIMATE.start_main_#t~ite42_3| v_~x~0_12) (or (= 0 (mod v_~x$w_buff1_used~0_34 256)) (= 0 (mod v_~x$r_buff1_thd0~0_4 256)))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_34, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_4, ~x~0=v_~x~0_12} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_34, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_4, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_3|, ~x~0=v_~x~0_12} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [491] L787-4-->L787-5: Formula: (= |v_ULTIMATE.start_main_#t~ite43_3| |v_ULTIMATE.start_main_#t~ite42_4|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [467] L787-5-->L788: Formula: (= v_~x~0_13 |v_ULTIMATE.start_main_#t~ite43_5|) InVars {ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|, ~x~0=v_~x~0_13} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [418] L788-->L788-2: Formula: (and (or (= (mod v_~x$r_buff0_thd0~0_6 256) 0) (= 0 (mod v_~x$w_buff0_used~0_59 256))) (= |v_ULTIMATE.start_main_#t~ite44_3| v_~x$w_buff0_used~0_59)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_59} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_59} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [423] L788-2-->L789: Formula: (= v_~x$w_buff0_used~0_60 |v_ULTIMATE.start_main_#t~ite44_5|) InVars {ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_5|} OutVars{ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_60} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44, ~x$w_buff0_used~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [360] L789-->L789-2: Formula: (and (or (= (mod v_~x$r_buff0_thd0~0_8 256) 0) (= (mod v_~x$w_buff0_used~0_62 256) 0)) (= |v_ULTIMATE.start_main_#t~ite45_3| v_~x$w_buff1_used~0_36) (or (= (mod v_~x$r_buff1_thd0~0_6 256) 0) (= (mod v_~x$w_buff1_used~0_36 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_8, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_36, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_8, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_36, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite45] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [522] L789-2-->L790: Formula: (= v_~x$w_buff1_used~0_37 |v_ULTIMATE.start_main_#t~ite45_5|) InVars {ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_5|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_37, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite45] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [471] L790-->L790-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd0~0_10 256)) (= 0 (mod v_~x$w_buff0_used~0_64 256))) (= |v_ULTIMATE.start_main_#t~ite46_3| v_~x$r_buff0_thd0~0_10)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_10, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_64} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_10, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_64} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [458] L790-2-->L791: Formula: (= v_~x$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite46_5|) InVars {ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_5|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_11, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [408] L791-->L791-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite47_3| v_~x$r_buff1_thd0~0_8) (or (= 0 (mod v_~x$r_buff0_thd0~0_13 256)) (= (mod v_~x$w_buff0_used~0_66 256) 0)) (or (= 0 (mod v_~x$r_buff1_thd0~0_8 256)) (= 0 (mod v_~x$w_buff1_used~0_39 256)))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_13, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_39, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_66} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_3|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_13, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_39, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_66} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [415] L791-2-->L796: Formula: (and (= v_~x$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite47_5|) (= v_~main$tmp_guard1~0_2 (ite (= 0 (ite (not (and (= 2 v_~y~0_4) (= 0 v_~__unbuffered_p1_EBX~0_2) (= 1 v_~__unbuffered_p1_EAX~0_2))) 1 0)) 0 1))) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_5|, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~y~0=v_~y~0_4} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_4|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ~y~0=v_~y~0_4, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ~main$tmp_guard1~0, ~x$r_buff1_thd0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [450] L796-->L796-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_3 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [452] L796-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [406] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [404] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 [402] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1611~0.base, main_~#t1611~0.offset, main_~#t1612~0.base, main_~#t1612~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t1611~0.base, main_~#t1611~0.offset := #Ultimate.alloc(4); srcloc: L778 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1611~0.base, main_~#t1611~0.offset, 4); srcloc: L778-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 1;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd1~0 := 1;~y~0 := 1; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite4 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 havoc main_#t~nondet40; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 SUMMARY for call main_~#t1612~0.base, main_~#t1612~0.offset := #Ultimate.alloc(4); srcloc: L780 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t1612~0.base, main_~#t1612~0.offset, 4); srcloc: L780-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 2;~z~0 := 1;~__unbuffered_p1_EAX~0 := ~z~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256);#t~ite13 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x~0 := #t~ite13;havoc #t~ite12;havoc #t~ite13; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff0~0 := #t~ite16;havoc #t~ite16;havoc #t~ite15;havoc #t~ite14; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~x$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff1~0 := #t~ite19;havoc #t~ite18;havoc #t~ite17;havoc #t~ite19; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite22;havoc #t~ite20;havoc #t~ite21;havoc #t~ite22; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite25;havoc #t~ite23;havoc #t~ite24;havoc #t~ite25; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff0_thd2~0 := #t~ite28;havoc #t~ite26;havoc #t~ite28;havoc #t~ite27; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff1_thd2~0 := #t~ite31;havoc #t~ite31;havoc #t~ite29;havoc #t~ite30;~__unbuffered_p1_EBX~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~x$flush_delayed~0 % 256;#t~ite32 := ~x$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x~0 := #t~ite4;havoc #t~ite4;havoc #t~ite3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [?] 1 ~x~0 := #t~ite32;havoc #t~ite32;~x$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256);#t~ite33 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x~0 := #t~ite34;havoc #t~ite34;havoc #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite35 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite36 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite37 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite38 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite42 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite44 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite45 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1611~0.base, main_~#t1611~0.offset, main_~#t1612~0.base, main_~#t1612~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t1611~0.base, main_~#t1611~0.offset := #Ultimate.alloc(4); srcloc: L778 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1611~0.base, main_~#t1611~0.offset, 4); srcloc: L778-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 1;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd1~0 := 1;~y~0 := 1; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite4 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 havoc main_#t~nondet40; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 SUMMARY for call main_~#t1612~0.base, main_~#t1612~0.offset := #Ultimate.alloc(4); srcloc: L780 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t1612~0.base, main_~#t1612~0.offset, 4); srcloc: L780-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 2;~z~0 := 1;~__unbuffered_p1_EAX~0 := ~z~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256);#t~ite13 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x~0 := #t~ite13;havoc #t~ite12;havoc #t~ite13; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~x$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff0~0 := #t~ite16;havoc #t~ite16;havoc #t~ite15;havoc #t~ite14; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~x$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff1~0 := #t~ite19;havoc #t~ite18;havoc #t~ite17;havoc #t~ite19; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite22;havoc #t~ite20;havoc #t~ite21;havoc #t~ite22; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite25;havoc #t~ite23;havoc #t~ite24;havoc #t~ite25; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff0_thd2~0 := #t~ite28;havoc #t~ite26;havoc #t~ite28;havoc #t~ite27; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff1_thd2~0 := #t~ite31;havoc #t~ite31;havoc #t~ite29;havoc #t~ite30;~__unbuffered_p1_EBX~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume 0 != ~x$flush_delayed~0 % 256;#t~ite32 := ~x$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x~0 := #t~ite4;havoc #t~ite4;havoc #t~ite3; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [?] 1 ~x~0 := #t~ite32;havoc #t~ite32;~x$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256);#t~ite33 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x~0 := #t~ite34;havoc #t~ite34;havoc #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite35 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=1, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite36 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite37 := ~x$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 0 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite38 := ~x$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] 1 ~x$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite42 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite44 := ~x$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite45 := ~x$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1611~0.base|=5, |ULTIMATE.start_main_~#t1611~0.offset|=0, |ULTIMATE.start_main_~#t1612~0.base|=6, |ULTIMATE.start_main_~#t1612~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L698] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L699] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1611~0.base, main_~#t1611~0.offset, main_~#t1612~0.base, main_~#t1612~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L778] -1 call main_~#t1611~0.base, main_~#t1611~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] -1 call write~int(0, main_~#t1611~0.base, main_~#t1611~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L700-L727] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L703] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L704] 0 ~x$w_buff0~0 := 1; [L705] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L706] 0 ~x$w_buff0_used~0 := 1; [L707] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L707] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L708] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L709] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L710] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L711] 0 ~x$r_buff0_thd1~0 := 1; [L714] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L717] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L717] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L779] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L780] -1 call main_~#t1612~0.base, main_~#t1612~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] -1 call write~int(1, main_~#t1612~0.base, main_~#t1612~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L728-L766] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L731] 1 ~y~0 := 2; [L734] 1 ~z~0 := 1; [L737] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L740] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L740] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L741] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L741] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L742] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L743] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256); [L744] 1 #t~ite13 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 ~x~0 := #t~ite13; [L744] 1 havoc #t~ite12; [L744] 1 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 assume 0 != ~weak$$choice2~0 % 256; [L745] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 ~x$w_buff0~0 := #t~ite16; [L745] 1 havoc #t~ite16; [L745] 1 havoc #t~ite15; [L745] 1 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 assume 0 != ~weak$$choice2~0 % 256; [L746] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 ~x$w_buff1~0 := #t~ite19; [L746] 1 havoc #t~ite18; [L746] 1 havoc #t~ite17; [L746] 1 havoc #t~ite19; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 assume 0 != ~weak$$choice2~0 % 256; [L747] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 ~x$w_buff0_used~0 := #t~ite22; [L747] 1 havoc #t~ite20; [L747] 1 havoc #t~ite21; [L747] 1 havoc #t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 assume 0 != ~weak$$choice2~0 % 256; [L748] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 ~x$w_buff1_used~0 := #t~ite25; [L748] 1 havoc #t~ite23; [L748] 1 havoc #t~ite24; [L748] 1 havoc #t~ite25; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 assume 0 != ~weak$$choice2~0 % 256; [L749] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L749] 1 havoc #t~ite26; [L749] 1 havoc #t~ite28; [L749] 1 havoc #t~ite27; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 assume 0 != ~weak$$choice2~0 % 256; [L750] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L750] 1 havoc #t~ite31; [L750] 1 havoc #t~ite29; [L750] 1 havoc #t~ite30; [L751] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L752] 1 assume 0 != ~x$flush_delayed~0 % 256; [L752] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L717] 0 ~x~0 := #t~ite4; [L717] 0 havoc #t~ite4; [L717] 0 havoc #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [L752] 1 ~x~0 := #t~ite32; [L752] 1 havoc #t~ite32; [L753] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L756] 1 #t~ite33 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 ~x~0 := #t~ite34; [L756] 1 havoc #t~ite34; [L756] 1 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L757] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 ~x$w_buff0_used~0 := #t~ite35; [L757] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L758] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 ~x$w_buff1_used~0 := #t~ite36; [L758] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L759] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L759] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L718] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 ~x$w_buff0_used~0 := #t~ite5; [L718] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L719] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 ~x$w_buff1_used~0 := #t~ite6; [L719] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L720] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L720] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L721] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L721] 0 havoc #t~ite8; [L724] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L760] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L760] 1 havoc #t~ite38; [L763] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L781] -1 havoc main_#t~nondet41; [L783] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L785] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L787] -1 main_#t~ite42 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 ~x~0 := main_#t~ite43; [L787] -1 havoc main_#t~ite42; [L787] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L788] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L788] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L789] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L789] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L790] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L790] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L791] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L791] -1 havoc main_#t~ite47; [L794] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L698] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L699] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1611~0.base, main_~#t1611~0.offset, main_~#t1612~0.base, main_~#t1612~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L778] -1 call main_~#t1611~0.base, main_~#t1611~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] -1 call write~int(0, main_~#t1611~0.base, main_~#t1611~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L700-L727] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L703] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L704] 0 ~x$w_buff0~0 := 1; [L705] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L706] 0 ~x$w_buff0_used~0 := 1; [L707] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L707] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L708] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L709] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L710] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L711] 0 ~x$r_buff0_thd1~0 := 1; [L714] 0 ~y~0 := 1; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L717] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L717] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L779] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L780] -1 call main_~#t1612~0.base, main_~#t1612~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] -1 call write~int(1, main_~#t1612~0.base, main_~#t1612~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L728-L766] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L731] 1 ~y~0 := 2; [L734] 1 ~z~0 := 1; [L737] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L740] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L740] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L741] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L741] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L742] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L743] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256); [L744] 1 #t~ite13 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 ~x~0 := #t~ite13; [L744] 1 havoc #t~ite12; [L744] 1 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 assume 0 != ~weak$$choice2~0 % 256; [L745] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 ~x$w_buff0~0 := #t~ite16; [L745] 1 havoc #t~ite16; [L745] 1 havoc #t~ite15; [L745] 1 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 assume 0 != ~weak$$choice2~0 % 256; [L746] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 ~x$w_buff1~0 := #t~ite19; [L746] 1 havoc #t~ite18; [L746] 1 havoc #t~ite17; [L746] 1 havoc #t~ite19; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 assume 0 != ~weak$$choice2~0 % 256; [L747] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 ~x$w_buff0_used~0 := #t~ite22; [L747] 1 havoc #t~ite20; [L747] 1 havoc #t~ite21; [L747] 1 havoc #t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 assume 0 != ~weak$$choice2~0 % 256; [L748] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 ~x$w_buff1_used~0 := #t~ite25; [L748] 1 havoc #t~ite23; [L748] 1 havoc #t~ite24; [L748] 1 havoc #t~ite25; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 assume 0 != ~weak$$choice2~0 % 256; [L749] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L749] 1 havoc #t~ite26; [L749] 1 havoc #t~ite28; [L749] 1 havoc #t~ite27; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 assume 0 != ~weak$$choice2~0 % 256; [L750] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L750] 1 havoc #t~ite31; [L750] 1 havoc #t~ite29; [L750] 1 havoc #t~ite30; [L751] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L752] 1 assume 0 != ~x$flush_delayed~0 % 256; [L752] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L717] 0 ~x~0 := #t~ite4; [L717] 0 havoc #t~ite4; [L717] 0 havoc #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [L752] 1 ~x~0 := #t~ite32; [L752] 1 havoc #t~ite32; [L753] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256); [L756] 1 #t~ite33 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 ~x~0 := #t~ite34; [L756] 1 havoc #t~ite34; [L756] 1 havoc #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L757] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 ~x$w_buff0_used~0 := #t~ite35; [L757] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L758] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 ~x$w_buff1_used~0 := #t~ite36; [L758] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L759] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L759] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256; [L718] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 ~x$w_buff0_used~0 := #t~ite5; [L718] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L719] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 ~x$w_buff1_used~0 := #t~ite6; [L719] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L720] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L720] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L721] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L721] 0 havoc #t~ite8; [L724] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L760] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L760] 1 havoc #t~ite38; [L763] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L781] -1 havoc main_#t~nondet41; [L783] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L785] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L787] -1 main_#t~ite42 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 ~x~0 := main_#t~ite43; [L787] -1 havoc main_#t~ite42; [L787] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L788] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L788] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L789] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L789] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L790] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L790] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L791] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L791] -1 havoc main_#t~ite47; [L794] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0.base=5, main_~#t1611~0.offset=0, main_~#t1612~0.base=6, main_~#t1612~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L698] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L699] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1611~0, main_~#t1612~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L778] FCALL -1 call main_~#t1611~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FCALL -1 call write~int(0, main_~#t1611~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L700-L727] 0 ~arg := #in~arg; [L703] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L704] 0 ~x$w_buff0~0 := 1; [L705] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L706] 0 ~x$w_buff0_used~0 := 1; [L707] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L707] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L708] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L709] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L710] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L711] 0 ~x$r_buff0_thd1~0 := 1; [L714] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L717] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L717] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L779] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L780] FCALL -1 call main_~#t1612~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FCALL -1 call write~int(1, main_~#t1612~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L728-L766] 1 ~arg := #in~arg; [L731] 1 ~y~0 := 2; [L734] 1 ~z~0 := 1; [L737] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L740] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L740] 1 havoc #t~nondet10; [L741] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L741] 1 havoc #t~nondet11; [L742] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L743] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L744] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 ~x~0 := #t~ite13; [L744] 1 havoc #t~ite12; [L744] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 ~x$w_buff0~0 := #t~ite16; [L745] 1 havoc #t~ite16; [L745] 1 havoc #t~ite15; [L745] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L746] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 ~x$w_buff1~0 := #t~ite19; [L746] 1 havoc #t~ite18; [L746] 1 havoc #t~ite17; [L746] 1 havoc #t~ite19; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 ~x$w_buff0_used~0 := #t~ite22; [L747] 1 havoc #t~ite20; [L747] 1 havoc #t~ite21; [L747] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 ~x$w_buff1_used~0 := #t~ite25; [L748] 1 havoc #t~ite23; [L748] 1 havoc #t~ite24; [L748] 1 havoc #t~ite25; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L749] 1 havoc #t~ite26; [L749] 1 havoc #t~ite28; [L749] 1 havoc #t~ite27; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L750] 1 havoc #t~ite31; [L750] 1 havoc #t~ite29; [L750] 1 havoc #t~ite30; [L751] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L752] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L752] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L717] 0 ~x~0 := #t~ite4; [L717] 0 havoc #t~ite4; [L717] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [L752] 1 ~x~0 := #t~ite32; [L752] 1 havoc #t~ite32; [L753] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L756] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 ~x~0 := #t~ite34; [L756] 1 havoc #t~ite34; [L756] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L757] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 ~x$w_buff0_used~0 := #t~ite35; [L757] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L758] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 ~x$w_buff1_used~0 := #t~ite36; [L758] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L759] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L759] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L718] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 ~x$w_buff0_used~0 := #t~ite5; [L718] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 ~x$w_buff1_used~0 := #t~ite6; [L719] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L720] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L720] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L721] 0 havoc #t~ite8; [L724] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L760] 1 havoc #t~ite38; [L763] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L781] -1 havoc main_#t~nondet41; [L783] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L785] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L787] -1 main_#t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 ~x~0 := main_#t~ite43; [L787] -1 havoc main_#t~ite42; [L787] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L788] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L788] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L789] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L789] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L790] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L790] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L791] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L791] -1 havoc main_#t~ite47; [L794] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L698] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L699] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t1611~0, main_~#t1612~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L778] FCALL -1 call main_~#t1611~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FCALL -1 call write~int(0, main_~#t1611~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L700-L727] 0 ~arg := #in~arg; [L703] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L704] 0 ~x$w_buff0~0 := 1; [L705] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L706] 0 ~x$w_buff0_used~0 := 1; [L707] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L707] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L708] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L709] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L710] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L711] 0 ~x$r_buff0_thd1~0 := 1; [L714] 0 ~y~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L717] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L717] 0 #t~ite4 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L779] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L780] FCALL -1 call main_~#t1612~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FCALL -1 call write~int(1, main_~#t1612~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L728-L766] 1 ~arg := #in~arg; [L731] 1 ~y~0 := 2; [L734] 1 ~z~0 := 1; [L737] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L740] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L740] 1 havoc #t~nondet10; [L741] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L741] 1 havoc #t~nondet11; [L742] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L743] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L744] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 ~x~0 := #t~ite13; [L744] 1 havoc #t~ite12; [L744] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 ~x$w_buff0~0 := #t~ite16; [L745] 1 havoc #t~ite16; [L745] 1 havoc #t~ite15; [L745] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L746] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 ~x$w_buff1~0 := #t~ite19; [L746] 1 havoc #t~ite18; [L746] 1 havoc #t~ite17; [L746] 1 havoc #t~ite19; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 ~x$w_buff0_used~0 := #t~ite22; [L747] 1 havoc #t~ite20; [L747] 1 havoc #t~ite21; [L747] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 ~x$w_buff1_used~0 := #t~ite25; [L748] 1 havoc #t~ite23; [L748] 1 havoc #t~ite24; [L748] 1 havoc #t~ite25; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L749] 1 havoc #t~ite26; [L749] 1 havoc #t~ite28; [L749] 1 havoc #t~ite27; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L750] 1 havoc #t~ite31; [L750] 1 havoc #t~ite29; [L750] 1 havoc #t~ite30; [L751] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L752] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L752] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L717] 0 ~x~0 := #t~ite4; [L717] 0 havoc #t~ite4; [L717] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [L752] 1 ~x~0 := #t~ite32; [L752] 1 havoc #t~ite32; [L753] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L756] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 ~x~0 := #t~ite34; [L756] 1 havoc #t~ite34; [L756] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L757] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 ~x$w_buff0_used~0 := #t~ite35; [L757] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L758] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 ~x$w_buff1_used~0 := #t~ite36; [L758] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L759] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L759] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L718] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 ~x$w_buff0_used~0 := #t~ite5; [L718] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 ~x$w_buff1_used~0 := #t~ite6; [L719] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L720] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L720] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L721] 0 havoc #t~ite8; [L724] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L760] 1 havoc #t~ite38; [L763] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L781] -1 havoc main_#t~nondet41; [L783] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L785] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L787] -1 main_#t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 ~x~0 := main_#t~ite43; [L787] -1 havoc main_#t~ite42; [L787] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L788] -1 main_#t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 ~x$w_buff0_used~0 := main_#t~ite44; [L788] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L789] -1 main_#t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 ~x$w_buff1_used~0 := main_#t~ite45; [L789] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L790] -1 main_#t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 ~x$r_buff0_thd0~0 := main_#t~ite46; [L790] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L791] -1 main_#t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 ~x$r_buff1_thd0~0 := main_#t~ite47; [L791] -1 havoc main_#t~ite47; [L794] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L796] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1611~0!base=5, main_~#t1611~0!offset=0, main_~#t1612~0!base=6, main_~#t1612~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L698] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L699] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L778] FCALL -1 call ~#t1611~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FCALL -1 call write~int(0, ~#t1611~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L700-L727] 0 ~arg := #in~arg; [L703] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L704] 0 ~x$w_buff0~0 := 1; [L705] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L706] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L708] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L709] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L710] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L711] 0 ~x$r_buff0_thd1~0 := 1; [L714] 0 ~y~0 := 1; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L717] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L717] 0 #t~ite4 := ~x$w_buff0~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L779] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L780] FCALL -1 call ~#t1612~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FCALL -1 call write~int(1, ~#t1612~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L728-L766] 1 ~arg := #in~arg; [L731] 1 ~y~0 := 2; [L734] 1 ~z~0 := 1; [L737] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L740] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L740] 1 havoc #t~nondet10; [L741] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L741] 1 havoc #t~nondet11; [L742] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L743] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L744] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 ~x~0 := #t~ite13; [L744] 1 havoc #t~ite12; [L744] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 ~x$w_buff0~0 := #t~ite16; [L745] 1 havoc #t~ite16; [L745] 1 havoc #t~ite15; [L745] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L746] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 ~x$w_buff1~0 := #t~ite19; [L746] 1 havoc #t~ite18; [L746] 1 havoc #t~ite17; [L746] 1 havoc #t~ite19; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 ~x$w_buff0_used~0 := #t~ite22; [L747] 1 havoc #t~ite20; [L747] 1 havoc #t~ite21; [L747] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 ~x$w_buff1_used~0 := #t~ite25; [L748] 1 havoc #t~ite23; [L748] 1 havoc #t~ite24; [L748] 1 havoc #t~ite25; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L749] 1 havoc #t~ite26; [L749] 1 havoc #t~ite28; [L749] 1 havoc #t~ite27; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L750] 1 havoc #t~ite31; [L750] 1 havoc #t~ite29; [L750] 1 havoc #t~ite30; [L751] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L752] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L752] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L717] 0 ~x~0 := #t~ite4; [L717] 0 havoc #t~ite4; [L717] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [L752] 1 ~x~0 := #t~ite32; [L752] 1 havoc #t~ite32; [L753] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L756] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 ~x~0 := #t~ite34; [L756] 1 havoc #t~ite34; [L756] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L757] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 ~x$w_buff0_used~0 := #t~ite35; [L757] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L758] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 ~x$w_buff1_used~0 := #t~ite36; [L758] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L759] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L759] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L718] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 ~x$w_buff0_used~0 := #t~ite5; [L718] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 ~x$w_buff1_used~0 := #t~ite6; [L719] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L720] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L720] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L721] 0 havoc #t~ite8; [L724] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L760] 1 havoc #t~ite38; [L763] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L781] -1 havoc #t~nondet41; [L783] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L785] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L787] -1 #t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 ~x~0 := #t~ite43; [L787] -1 havoc #t~ite42; [L787] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L788] -1 #t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 ~x$w_buff0_used~0 := #t~ite44; [L788] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L789] -1 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 ~x$w_buff1_used~0 := #t~ite45; [L789] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L790] -1 #t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 ~x$r_buff0_thd0~0 := #t~ite46; [L790] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L791] -1 #t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 ~x$r_buff1_thd0~0 := #t~ite47; [L791] -1 havoc #t~ite47; [L794] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L675] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L676] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L677] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L679] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L680] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L681] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L683] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L684] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L686] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L687] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L688] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L689] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L690] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L691] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L692] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L695] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L697] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L698] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L699] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L778] FCALL -1 call ~#t1611~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FCALL -1 call write~int(0, ~#t1611~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L779] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L700-L727] 0 ~arg := #in~arg; [L703] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L704] 0 ~x$w_buff0~0 := 1; [L705] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L706] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L708] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L709] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L710] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L711] 0 ~x$r_buff0_thd1~0 := 1; [L714] 0 ~y~0 := 1; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L717] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L717] 0 #t~ite4 := ~x$w_buff0~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L779] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L780] FCALL -1 call ~#t1612~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FCALL -1 call write~int(1, ~#t1612~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L781] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=1, ~z~0=0] [L728-L766] 1 ~arg := #in~arg; [L731] 1 ~y~0 := 2; [L734] 1 ~z~0 := 1; [L737] 1 ~__unbuffered_p1_EAX~0 := ~z~0; [L740] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L740] 1 havoc #t~nondet10; [L741] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L741] 1 havoc #t~nondet11; [L742] 1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L743] 1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] COND TRUE 1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd2~0 % 256 && 0 == ~x$r_buff1_thd2~0 % 256) [L744] 1 #t~ite13 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L744] 1 ~x~0 := #t~ite13; [L744] 1 havoc #t~ite12; [L744] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L745] 1 #t~ite16 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L745] 1 ~x$w_buff0~0 := #t~ite16; [L745] 1 havoc #t~ite16; [L745] 1 havoc #t~ite15; [L745] 1 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L746] 1 #t~ite19 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L746] 1 ~x$w_buff1~0 := #t~ite19; [L746] 1 havoc #t~ite18; [L746] 1 havoc #t~ite17; [L746] 1 havoc #t~ite19; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite22 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L747] 1 ~x$w_buff0_used~0 := #t~ite22; [L747] 1 havoc #t~ite20; [L747] 1 havoc #t~ite21; [L747] 1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite25 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L748] 1 ~x$w_buff1_used~0 := #t~ite25; [L748] 1 havoc #t~ite23; [L748] 1 havoc #t~ite24; [L748] 1 havoc #t~ite25; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite28 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L749] 1 ~x$r_buff0_thd2~0 := #t~ite28; [L749] 1 havoc #t~ite26; [L749] 1 havoc #t~ite28; [L749] 1 havoc #t~ite27; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite31 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L750] 1 ~x$r_buff1_thd2~0 := #t~ite31; [L750] 1 havoc #t~ite31; [L750] 1 havoc #t~ite29; [L750] 1 havoc #t~ite30; [L751] 1 ~__unbuffered_p1_EBX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L752] COND TRUE 1 0 != ~x$flush_delayed~0 % 256 [L752] 1 #t~ite32 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L717] 0 ~x~0 := #t~ite4; [L717] 0 havoc #t~ite4; [L717] 0 havoc #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=2, ~z~0=1] [L752] 1 ~x~0 := #t~ite32; [L752] 1 havoc #t~ite32; [L753] 1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256) [L756] 1 #t~ite33 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L756] 1 ~x~0 := #t~ite34; [L756] 1 havoc #t~ite34; [L756] 1 havoc #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L757] 1 #t~ite35 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L757] 1 ~x$w_buff0_used~0 := #t~ite35; [L757] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L758] 1 #t~ite36 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L758] 1 ~x$w_buff1_used~0 := #t~ite36; [L758] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L759] 1 #t~ite37 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L759] 1 ~x$r_buff0_thd2~0 := #t~ite37; [L759] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256 [L718] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L718] 0 ~x$w_buff0_used~0 := #t~ite5; [L718] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L719] 0 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L719] 0 ~x$w_buff1_used~0 := #t~ite6; [L719] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L720] 0 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L720] 0 ~x$r_buff0_thd1~0 := #t~ite7; [L720] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L721] 0 ~x$r_buff1_thd1~0 := #t~ite8; [L721] 0 havoc #t~ite8; [L724] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite38 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L760] 1 ~x$r_buff1_thd2~0 := #t~ite38; [L760] 1 havoc #t~ite38; [L763] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L781] -1 havoc #t~nondet41; [L783] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L785] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L787] -1 #t~ite42 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L787] -1 ~x~0 := #t~ite43; [L787] -1 havoc #t~ite42; [L787] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L788] -1 #t~ite44 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L788] -1 ~x$w_buff0_used~0 := #t~ite44; [L788] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L789] -1 #t~ite45 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L789] -1 ~x$w_buff1_used~0 := #t~ite45; [L789] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L790] -1 #t~ite46 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L790] -1 ~x$r_buff0_thd0~0 := #t~ite46; [L790] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L791] -1 #t~ite47 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L791] -1 ~x$r_buff1_thd0~0 := #t~ite47; [L791] -1 havoc #t~ite47; [L794] -1 ~main$tmp_guard1~0 := (if 0 == (if !((2 == ~y~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=1, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=1, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=2, ~z~0=1] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L675] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L676] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0] [L677] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L679] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L680] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0] [L681] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0] [L682] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L683] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L684] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L685] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L686] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L687] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L688] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L689] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L690] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L691] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L692] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L693] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L695] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L697] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L698] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L699] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L778] -1 pthread_t t1611; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L779] FCALL, FORK -1 pthread_create(&t1611, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L703] 0 x$w_buff1 = x$w_buff0 [L704] 0 x$w_buff0 = 1 [L705] 0 x$w_buff1_used = x$w_buff0_used [L706] 0 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L708] 0 x$r_buff1_thd0 = x$r_buff0_thd0 [L709] 0 x$r_buff1_thd1 = x$r_buff0_thd1 [L710] 0 x$r_buff1_thd2 = x$r_buff0_thd2 [L711] 0 x$r_buff0_thd1 = (_Bool)1 [L714] 0 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L717] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L780] -1 pthread_t t1612; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L781] FCALL, FORK -1 pthread_create(&t1612, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L731] 1 y = 2 [L734] 1 z = 1 [L737] 1 __unbuffered_p1_EAX = z [L740] 1 weak$$choice0 = __VERIFIER_nondet_pointer() [L741] 1 weak$$choice2 = __VERIFIER_nondet_pointer() [L742] 1 x$flush_delayed = weak$$choice2 [L743] 1 x$mem_tmp = x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L744] EXPR 1 !x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1) VAL [!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L744] 1 x = !x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1) [L745] EXPR 1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0))=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L745] 1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)) [L746] EXPR 1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L746] 1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)) [L747] EXPR 1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used))=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L747] 1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used)) [L748] EXPR 1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L748] 1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L749] EXPR 1 weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L749] 1 x$r_buff0_thd2 = weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2)) [L750] EXPR 1 weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L750] 1 x$r_buff1_thd2 = weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L751] 1 __unbuffered_p1_EBX = x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L752] EXPR 1 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=1, x$flush_delayed ? x$mem_tmp : x=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L717] 0 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L752] 1 x = x$flush_delayed ? x$mem_tmp : x [L753] 1 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L756] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L756] EXPR 1 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=2, z=1] [L756] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x)=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=2, z=1] [L756] 1 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L757] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L757] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L758] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L758] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L759] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L759] 1 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L718] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L718] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L719] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L719] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L720] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L720] 0 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L721] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L721] 0 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L724] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L760] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L760] 1 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L763] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L783] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L788] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L788] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L789] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L789] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L790] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L790] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L791] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L791] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L794] -1 main$tmp_guard1 = !(y == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] ----- [2018-11-23 06:10:48,827 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_5cdf24fd-48ab-48ae-a66e-eca19a330999/bin-2019/uautomizer/witness.graphml [2018-11-23 06:10:48,827 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 06:10:48,828 INFO L168 Benchmark]: Toolchain (without parser) took 39836.35 ms. Allocated memory was 1.0 GB in the beginning and 4.5 GB in the end (delta: 3.5 GB). Free memory was 955.5 MB in the beginning and 2.3 GB in the end (delta: -1.4 GB). Peak memory consumption was 2.1 GB. Max. memory is 11.5 GB. [2018-11-23 06:10:48,829 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 06:10:48,829 INFO L168 Benchmark]: CACSL2BoogieTranslator took 410.21 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.8 MB). Free memory was 955.5 MB in the beginning and 1.1 GB in the end (delta: -157.0 MB). Peak memory consumption was 35.5 MB. Max. memory is 11.5 GB. [2018-11-23 06:10:48,830 INFO L168 Benchmark]: Boogie Procedure Inliner took 41.99 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.5 MB). Peak memory consumption was 3.5 MB. Max. memory is 11.5 GB. [2018-11-23 06:10:48,830 INFO L168 Benchmark]: Boogie Preprocessor took 21.85 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 06:10:48,830 INFO L168 Benchmark]: RCFGBuilder took 523.82 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.8 MB). Peak memory consumption was 50.8 MB. Max. memory is 11.5 GB. [2018-11-23 06:10:48,830 INFO L168 Benchmark]: TraceAbstraction took 34088.21 ms. Allocated memory was 1.2 GB in the beginning and 4.5 GB in the end (delta: 3.4 GB). Free memory was 1.1 GB in the beginning and 2.5 GB in the end (delta: -1.4 GB). Peak memory consumption was 2.0 GB. Max. memory is 11.5 GB. [2018-11-23 06:10:48,830 INFO L168 Benchmark]: Witness Printer took 4746.79 ms. Allocated memory is still 4.5 GB. Free memory was 2.5 GB in the beginning and 2.3 GB in the end (delta: 126.6 MB). Peak memory consumption was 126.6 MB. Max. memory is 11.5 GB. [2018-11-23 06:10:48,832 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 410.21 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.8 MB). Free memory was 955.5 MB in the beginning and 1.1 GB in the end (delta: -157.0 MB). Peak memory consumption was 35.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 41.99 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.5 MB). Peak memory consumption was 3.5 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 21.85 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 523.82 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.8 MB). Peak memory consumption was 50.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 34088.21 ms. Allocated memory was 1.2 GB in the beginning and 4.5 GB in the end (delta: 3.4 GB). Free memory was 1.1 GB in the beginning and 2.5 GB in the end (delta: -1.4 GB). Peak memory consumption was 2.0 GB. Max. memory is 11.5 GB. * Witness Printer took 4746.79 ms. Allocated memory is still 4.5 GB. Free memory was 2.5 GB in the beginning and 2.3 GB in the end (delta: 126.6 MB). Peak memory consumption was 126.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L675] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L676] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0] [L677] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L679] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L680] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0] [L681] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0] [L682] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L683] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L684] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L685] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L686] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L687] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L688] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L689] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L690] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L691] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L692] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L693] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L695] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L697] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L698] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L699] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L778] -1 pthread_t t1611; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L779] FCALL, FORK -1 pthread_create(&t1611, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L703] 0 x$w_buff1 = x$w_buff0 [L704] 0 x$w_buff0 = 1 [L705] 0 x$w_buff1_used = x$w_buff0_used [L706] 0 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L708] 0 x$r_buff1_thd0 = x$r_buff0_thd0 [L709] 0 x$r_buff1_thd1 = x$r_buff0_thd1 [L710] 0 x$r_buff1_thd2 = x$r_buff0_thd2 [L711] 0 x$r_buff0_thd1 = (_Bool)1 [L714] 0 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L717] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L780] -1 pthread_t t1612; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L781] FCALL, FORK -1 pthread_create(&t1612, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L731] 1 y = 2 [L734] 1 z = 1 [L737] 1 __unbuffered_p1_EAX = z [L740] 1 weak$$choice0 = __VERIFIER_nondet_pointer() [L741] 1 weak$$choice2 = __VERIFIER_nondet_pointer() [L742] 1 x$flush_delayed = weak$$choice2 [L743] 1 x$mem_tmp = x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L744] EXPR 1 !x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1) VAL [!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L744] 1 x = !x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff1) [L745] EXPR 1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0))=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L745] 1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)) [L746] EXPR 1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L746] 1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)) [L747] EXPR 1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used))=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L747] 1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used)) [L748] EXPR 1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L748] 1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L749] EXPR 1 weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L749] 1 x$r_buff0_thd2 = weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2)) [L750] EXPR 1 weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L750] 1 x$r_buff1_thd2 = weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used || !x$r_buff0_thd2 && !x$w_buff1_used || !x$r_buff0_thd2 && !x$r_buff1_thd2 ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L751] 1 __unbuffered_p1_EBX = x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L752] EXPR 1 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=1, x$flush_delayed ? x$mem_tmp : x=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L717] 0 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L752] 1 x = x$flush_delayed ? x$mem_tmp : x [L753] 1 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L756] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L756] EXPR 1 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=2, z=1] [L756] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x)=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x=0, y=2, z=1] [L756] 1 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L757] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L757] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L758] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L758] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L759] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L759] 1 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L718] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L718] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L719] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L719] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L720] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L720] 0 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L721] EXPR 0 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L721] 0 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L724] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L760] EXPR 1 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L760] 1 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L763] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L783] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L788] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L788] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L789] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L789] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L790] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L790] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L791] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L791] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L794] -1 main$tmp_guard1 = !(y == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 223 locations, 3 error locations. UNSAFE Result, 33.9s OverallTime, 44 OverallIterations, 1 TraceHistogramMax, 14.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 11452 SDtfs, 12843 SDslu, 27898 SDs, 0 SdLazy, 13775 SolverSat, 721 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 7.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 471 GetRequests, 111 SyntacticMatches, 43 SemanticMatches, 317 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 481 ImplicationChecksByTransitivity, 2.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=74881occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 11.5s AutomataMinimizationTime, 43 MinimizatonAttempts, 189568 StatesRemovedByMinimization, 42 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 2.6s InterpolantComputationTime, 3391 NumberOfCodeBlocks, 3391 NumberOfCodeBlocksAsserted, 44 NumberOfCheckSat, 3252 ConstructedInterpolants, 0 QuantifiedInterpolants, 875852 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 43 InterpolantComputations, 43 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...